Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\hpram.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW1NSR-LV4CQN48PC7/I6
Device	GW1NSR-4C
Created Time	Wed May 28 14:59:40 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C7/I6
Hold Delay Model	Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed	6160
Numbers of Endpoints Analyzed	3279
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	osc_clk_in	Base	20.000	50.000	0.000	10.000			clk
2	memory_clk	Generated	5.000	200.000	0.000	2.500	clk	osc_clk_in	your_instance_name/pllvr_inst/CLKOUT
3	clk_x1	Generated	10.000	100.000	0.000	5.000	your_instance_name/pllvr_inst/CLKOUT	memory_clk	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
4	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_ibuf/I
5	your_instance_name/pllvr_inst/CLKOUTP.default_gen_clk	Generated	5.000	200.000	0.000	2.500	clk_ibuf/I	osc_clk_in	your_instance_name/pllvr_inst/CLKOUTP
6	your_instance_name/pllvr_inst/CLKOUTD.default_gen_clk	Generated	10.000	100.000	0.000	5.000	clk_ibuf/I	osc_clk_in	your_instance_name/pllvr_inst/CLKOUTD
7	your_instance_name/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	15.000	66.667	0.000	7.500	clk_ibuf/I	osc_clk_in	your_instance_name/pllvr_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	osc_clk_in	50.000(MHz)	152.572(MHz)	6	TOP
2	clk_x1	100.000(MHz)	115.531(MHz)	5	TOP
3	tck_pad_i	20.000(MHz)	92.815(MHz)	6	TOP

No timing paths to get frequency of memory_clk!

No timing paths to get frequency of your_instance_name/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of your_instance_name/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
osc_clk_in	Setup	0.000	0
osc_clk_in	Hold	0.000	0
memory_clk	Setup	0.000	0
memory_clk	Hold	0.000	0
clk_x1	Setup	0.000	0
clk_x1	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
your_instance_name/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
your_instance_name/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
your_instance_name/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.344	u_test/curr_state_2_s0/Q	u_test/addr_add_r_19_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.624
2	1.344	u_test/curr_state_2_s0/Q	u_test/addr_add_r_20_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.624
3	1.344	u_test/curr_state_2_s0/Q	u_test/addr_add_r_21_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.624
4	1.620	u_test/curr_state_2_s0/Q	u_test/addr_add_r_14_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.348
5	1.784	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/Q	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_7_s1/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.184
6	1.892	u_test/curr_state_2_s0/Q	u_test/addr_add_r_18_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.812
7	1.892	u_test/curr_state_2_s0/Q	u_test/addr_add_r_10_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.075
8	1.892	u_test/curr_state_2_s0/Q	u_test/addr_add_r_11_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.075
9	1.892	u_test/curr_state_2_s0/Q	u_test/addr_add_r_15_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.075
10	1.892	u_test/curr_state_2_s0/Q	u_test/addr_add_r_18_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.075
11	1.903	u_test/curr_state_2_s0/Q	u_test/addr_add_r_12_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.065
12	1.952	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/Q	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_25_s1/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	8.015
13	1.955	u_test/curr_state_2_s0/Q	u_test/addr_add_r_6_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.749
14	1.955	u_test/curr_state_2_s0/Q	u_test/addr_add_r_9_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.749
15	1.955	u_test/curr_state_2_s0/Q	u_test/addr_add_r_13_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.749
16	2.097	u_test/curr_state_2_s0/Q	u_test/addr_add_r_12_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.606
17	2.097	u_test/curr_state_2_s0/Q	u_test/addr_add_r_21_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.606
18	2.104	u_test/curr_state_2_s0/Q	u_test/addr_add_r_17_s0/D	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.600
19	2.175	u_test/curr_state_2_s0/Q	u_test/addr_add_r_13_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.793
20	2.175	u_test/curr_state_2_s0/Q	u_test/addr_add_r_16_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.793
21	2.175	u_test/curr_state_2_s0/Q	u_test/addr_add_r_17_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.793
22	2.178	u_test/curr_state_2_s0/Q	u_test/addr_add_r_7_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.789
23	2.178	u_test/curr_state_2_s0/Q	u_test/addr_add_r_8_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.789
24	2.178	u_test/curr_state_2_s0/Q	u_test/addr_add_r_9_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.789
25	2.243	u_test/curr_state_2_s0/Q	u_test/addr_add_r_6_s0/CE	clk_x1:[R]	clk_x1:[R]	10.000	0.000	7.725

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.420	rst_glb_cnt_28_s4/Q	rst_glb_cnt_25_s0/CE	osc_clk_in:[R]	osc_clk_in:[R]	0.000	0.000	0.429
2	0.420	rst_glb_cnt_28_s4/Q	rst_glb_cnt_26_s0/CE	osc_clk_in:[R]	osc_clk_in:[R]	0.000	0.000	0.429
3	0.420	rst_glb_cnt_28_s4/Q	rst_glb_cnt_27_s0/CE	osc_clk_in:[R]	osc_clk_in:[R]	0.000	0.000	0.429
4	0.422	u_la0_top/data_register_33_s0/Q	u_la0_top/data_register_32_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.422
5	0.422	u_la0_top/u_ao_mem_ctrl/data_reg_dly_48_s0/Q	u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.422
6	0.422	u_la0_top/internal_reg_force_triger_syn_0_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.422
7	0.422	u_la0_top/rst_ao_syn_s0/Q	u_la0_top/rst_ao_s0/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.422
8	0.423	u_la0_top/data_register_63_s0/Q	u_la0_top/internal_register_select_10_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
9	0.423	u_la0_top/data_register_13_s0/Q	u_la0_top/data_register_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
10	0.423	u_la0_top/data_register_52_s0/Q	u_la0_top/data_register_51_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
11	0.423	u_la0_top/data_register_72_s0/Q	u_la0_top/data_register_71_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
12	0.423	u_icon_top/input_shift_reg_4_s0/Q	u_icon_top/input_shift_reg_3_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
13	0.423	u_icon_top/enable_reg_1_s0/Q	u_icon_top/enable_reg_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.423
14	0.424	u_la0_top/data_register_64_s0/Q	u_la0_top/internal_register_select_11_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
15	0.424	u_la0_top/data_register_65_s0/Q	u_la0_top/internal_register_select_12_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
16	0.424	u_la0_top/data_register_66_s0/Q	u_la0_top/internal_register_select_13_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
17	0.424	u_la0_top/data_register_62_s0/Q	u_la0_top/data_register_61_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
18	0.424	u_la0_top/data_register_66_s0/Q	u_la0_top/data_register_65_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
19	0.424	u_la0_top/data_register_68_s0/Q	u_la0_top/data_register_67_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
20	0.424	u_la0_top/data_register_70_s0/Q	u_la0_top/data_register_69_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.424
21	0.425	u_la0_top/data_register_5_s0/Q	u_la0_top/data_register_4_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.425
22	0.426	u_la0_top/data_register_1_s0/Q	u_la0_top/internal_reg_trig_level_max_1_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.426
23	0.524	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/Q	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/D	osc_clk_in:[R]	osc_clk_in:[R]	0.000	0.000	0.524
24	0.524	rst_glb_cnt_0_s2/Q	rst_glb_cnt_0_s2/D	osc_clk_in:[R]	osc_clk_in:[R]	0.000	0.000	0.524
25	0.524	u_test/check_data_2_s1/Q	u_test/check_data_2_s1/D	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.657	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	2.311
2	7.657	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	2.311
3	7.812	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	2.156
4	8.016	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.952
5	8.016	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.952
6	8.016	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.952
7	8.016	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.952
8	8.030	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.938
9	8.030	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.938
10	8.030	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.938
11	8.030	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.938
12	8.030	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.938
13	8.141	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.826
14	8.155	u_la0_top/rst_ao_s0/Q	u_la0_top/trigger_seq_start_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.813
15	8.155	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.813
16	8.155	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.813
17	8.159	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.809
18	8.159	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.809
19	8.159	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.809
20	8.159	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.809
21	8.160	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.808
22	8.160	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.808
23	8.160	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.808
24	8.160	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_5_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.808
25	8.160	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_6_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	10.000	0.000	1.808

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.825	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.835
2	0.830	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.839
3	0.830	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.839
4	0.830	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.839
5	0.830	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.839
6	0.862	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.871
7	0.862	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.871
8	0.865	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_end_dly_s0/PRESET	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.874
9	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
10	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
11	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
12	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
13	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
14	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_level_cnt_3_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
15	0.868	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.877
16	0.877	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_4_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.887
17	0.878	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.888
18	0.878	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.888
19	0.879	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_0_s3/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.888
20	0.879	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_1_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.888
21	0.879	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.888
22	0.880	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.889
23	0.880	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.889
24	0.882	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.892
25	0.882	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk_x1:[R]	clk_x1:[R]	0.000	0.000	0.892

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rd_data_d_31_s0
2	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rd_data_d_30_s0
3	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rdbk_data_13_s0
4	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rdbk_data_5_s0
5	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rdbk_data_1_s0
6	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rvld_s0
7	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/rd_data_valid_d_0_s0
8	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_35_s0
9	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_test/addr_add_r_21_s0
10	4.019	4.945	0.926	Low Pulse Width	clk_x1	u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.344
Data Arrival Time	8.803
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_19_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.803	1.422	tNET	RR	1	R17C21[2][A]	u_test/addr_add_r_19_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R17C21[2][A]	u_test/addr_add_r_19_s0/CLK
10.147	-0.032	tSu		1	R17C21[2][A]	u_test/addr_add_r_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 28.485%; route: 5.828, 67.577%; tC2Q: 0.340, 3.938%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path2

Path Summary:

Slack	1.344
Data Arrival Time	8.803
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_20_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.803	1.422	tNET	RR	1	R17C21[2][B]	u_test/addr_add_r_20_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R17C21[2][B]	u_test/addr_add_r_20_s0/CLK
10.147	-0.032	tSu		1	R17C21[2][B]	u_test/addr_add_r_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 28.485%; route: 5.828, 67.577%; tC2Q: 0.340, 3.938%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path3

Path Summary:

Slack	1.344
Data Arrival Time	8.803
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_21_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.803	1.422	tNET	RR	1	R17C21[1][A]	u_test/addr_add_r_21_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R17C21[1][A]	u_test/addr_add_r_21_s0/CLK
10.147	-0.032	tSu		1	R17C21[1][A]	u_test/addr_add_r_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 28.485%; route: 5.828, 67.577%; tC2Q: 0.340, 3.938%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path4

Path Summary:

Slack	1.620
Data Arrival Time	8.527
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_14_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.527	1.146	tNET	RR	1	R17C20[2][B]	u_test/addr_add_r_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R17C20[2][B]	u_test/addr_add_r_14_s0/CLK
10.147	-0.032	tSu		1	R17C20[2][B]	u_test/addr_add_r_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 29.426%; route: 5.552, 66.506%; tC2Q: 0.340, 4.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path5

Path Summary:

Slack	1.784
Data Arrival Time	8.364
Data Required Time	10.147
From	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1
To	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R13C14[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/CLK
0.519	0.340	tC2Q	RF	2	R13C14[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/Q
1.835	1.316	tNET	FF	1	R13C14[3][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s4/I2
2.649	0.814	tINS	FF	1	R13C14[3][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s4/F
3.245	0.596	tNET	FF	1	R12C15[2][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s1/I3
3.855	0.609	tINS	FF	3	R12C15[2][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s1/F
4.458	0.603	tNET	FF	1	R11C14[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s6/I1
5.272	0.814	tINS	FF	36	R11C14[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s6/F
6.642	1.369	tNET	FF	1	R14C11[0][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1258_s0/I2
7.236	0.594	tINS	FR	1	R14C11[0][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1258_s0/F
8.364	1.128	tNET	RR	1	R14C11[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C11[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_7_s1/CLK
10.147	-0.032	tSu		1	R14C11[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.832, 34.604%; route: 5.013, 61.247%; tC2Q: 0.340, 4.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path6

Path Summary:

Slack	1.892
Data Arrival Time	7.991
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_18_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.177	1.728	tNET	FF	1	R16C20[1][A]	u_test/n605_s1/I0
7.991	0.814	tINS	FF	1	R16C20[1][A]	u_test/n605_s1/F
7.991	0.000	tNET	FF	1	R16C20[1][A]	u_test/addr_add_r_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C20[1][A]	u_test/addr_add_r_18_s0/CLK
9.883	-0.296	tSu		1	R16C20[1][A]	u_test/addr_add_r_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.808, 35.942%; route: 4.664, 59.711%; tC2Q: 0.340, 4.348%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path7

Path Summary:

Slack	1.892
Data Arrival Time	8.255
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_10_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.255	0.874	tNET	RR	1	R16C20[2][A]	u_test/addr_add_r_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C20[2][A]	u_test/addr_add_r_10_s0/CLK
10.147	-0.032	tSu		1	R16C20[2][A]	u_test/addr_add_r_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 30.419%; route: 5.279, 65.376%; tC2Q: 0.340, 4.206%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path8

Path Summary:

Slack	1.892
Data Arrival Time	8.255
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_11_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.255	0.874	tNET	RR	1	R16C20[2][B]	u_test/addr_add_r_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C20[2][B]	u_test/addr_add_r_11_s0/CLK
10.147	-0.032	tSu		1	R16C20[2][B]	u_test/addr_add_r_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 30.419%; route: 5.279, 65.376%; tC2Q: 0.340, 4.206%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path9

Path Summary:

Slack	1.892
Data Arrival Time	8.255
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_15_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.255	0.874	tNET	RR	1	R16C20[1][B]	u_test/addr_add_r_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C20[1][B]	u_test/addr_add_r_15_s0/CLK
10.147	-0.032	tSu		1	R16C20[1][B]	u_test/addr_add_r_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 30.419%; route: 5.279, 65.376%; tC2Q: 0.340, 4.206%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path10

Path Summary:

Slack	1.892
Data Arrival Time	8.255
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_18_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.255	0.874	tNET	RR	1	R16C20[1][A]	u_test/addr_add_r_18_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C20[1][A]	u_test/addr_add_r_18_s0/CLK
10.147	-0.032	tSu		1	R16C20[1][A]	u_test/addr_add_r_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 30.419%; route: 5.279, 65.376%; tC2Q: 0.340, 4.206%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path11

Path Summary:

Slack	1.903
Data Arrival Time	8.245
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_12_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
8.245	0.863	tNET	RR	1	R16C19[0][A]	u_test/addr_add_r_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C19[0][A]	u_test/addr_add_r_12_s0/CLK
10.147	-0.032	tSu		1	R16C19[0][A]	u_test/addr_add_r_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 30.457%; route: 5.269, 65.332%; tC2Q: 0.340, 4.211%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path12

Path Summary:

Slack	1.952
Data Arrival Time	8.195
Data Required Time	10.147
From	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1
To	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_25_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R13C14[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/CLK
0.519	0.340	tC2Q	RF	2	R13C14[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_4_s1/Q
1.835	1.316	tNET	FF	1	R13C14[3][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s4/I2
2.649	0.814	tINS	FF	1	R13C14[3][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s4/F
3.245	0.596	tNET	FF	1	R12C15[2][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s1/I3
3.855	0.609	tINS	FF	3	R12C15[2][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s1/F
4.458	0.603	tNET	FF	1	R11C14[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s6/I1
5.272	0.814	tINS	FF	36	R11C14[1][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_s6/F
6.281	1.009	tNET	FF	1	R14C12[0][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1240_s0/I2
7.067	0.786	tINS	FR	1	R14C12[0][B]	u_hpram_top/u_hpram_top_0/u_hpram_init/n1240_s0/F
8.195	1.128	tNET	RR	1	R14C12[2][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_25_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C12[2][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_25_s1/CLK
10.147	-0.032	tSu		1	R14C12[2][A]	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].id_reg_25_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 3.024, 37.727%; route: 4.652, 58.036%; tC2Q: 0.340, 4.237%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path13

Path Summary:

Slack	1.955
Data Arrival Time	7.928
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_6_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.163	1.715	tNET	FF	1	R16C16[0][A]	u_test/n617_s1/I1
7.928	0.765	tINS	FF	1	R16C16[0][A]	u_test/n617_s1/F
7.928	0.000	tNET	FF	1	R16C16[0][A]	u_test/addr_add_r_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C16[0][A]	u_test/addr_add_r_6_s0/CLK
9.883	-0.296	tSu		1	R16C16[0][A]	u_test/addr_add_r_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.758, 35.594%; route: 4.651, 60.023%; tC2Q: 0.340, 4.383%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path14

Path Summary:

Slack	1.955
Data Arrival Time	7.928
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_9_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.163	1.715	tNET	FF	1	R16C17[1][A]	u_test/n614_s1/I2
7.928	0.765	tINS	FF	1	R16C17[1][A]	u_test/n614_s1/F
7.928	0.000	tNET	FF	1	R16C17[1][A]	u_test/addr_add_r_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C17[1][A]	u_test/addr_add_r_9_s0/CLK
9.883	-0.296	tSu		1	R16C17[1][A]	u_test/addr_add_r_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.758, 35.594%; route: 4.651, 60.023%; tC2Q: 0.340, 4.383%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path15

Path Summary:

Slack	1.955
Data Arrival Time	7.928
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_13_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.163	1.715	tNET	FF	1	R16C18[1][A]	u_test/n610_s1/I2
7.928	0.765	tINS	FF	1	R16C18[1][A]	u_test/n610_s1/F
7.928	0.000	tNET	FF	1	R16C18[1][A]	u_test/addr_add_r_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C18[1][A]	u_test/addr_add_r_13_s0/CLK
9.883	-0.296	tSu		1	R16C18[1][A]	u_test/addr_add_r_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.758, 35.594%; route: 4.651, 60.023%; tC2Q: 0.340, 4.383%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path16

Path Summary:

Slack	2.097
Data Arrival Time	7.786
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_12_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.177	1.728	tNET	FF	1	R16C19[0][A]	u_test/n611_s1/I2
7.786	0.609	tINS	FF	1	R16C19[0][A]	u_test/n611_s1/F
7.786	0.000	tNET	FF	1	R16C19[0][A]	u_test/addr_add_r_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C19[0][A]	u_test/addr_add_r_12_s0/CLK
9.883	-0.296	tSu		1	R16C19[0][A]	u_test/addr_add_r_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.602, 34.213%; route: 4.664, 61.322%; tC2Q: 0.340, 4.465%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path17

Path Summary:

Slack	2.097
Data Arrival Time	7.786
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_21_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.177	1.728	tNET	FF	1	R17C21[1][A]	u_test/n602_s1/I2
7.786	0.609	tINS	FF	1	R17C21[1][A]	u_test/n602_s1/F
7.786	0.000	tNET	FF	1	R17C21[1][A]	u_test/addr_add_r_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R17C21[1][A]	u_test/addr_add_r_21_s0/CLK
9.883	-0.296	tSu		1	R17C21[1][A]	u_test/addr_add_r_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.602, 34.213%; route: 4.664, 61.322%; tC2Q: 0.340, 4.465%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path18

Path Summary:

Slack	2.104
Data Arrival Time	7.779
Data Required Time	9.883
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_17_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
7.170	1.722	tNET	FF	1	R16C18[0][A]	u_test/n606_s1/I2
7.779	0.609	tINS	FF	1	R16C18[0][A]	u_test/n606_s1/F
7.779	0.000	tNET	FF	1	R16C18[0][A]	u_test/addr_add_r_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C18[0][A]	u_test/addr_add_r_17_s0/CLK
9.883	-0.296	tSu		1	R16C18[0][A]	u_test/addr_add_r_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.602, 34.243%; route: 4.658, 61.288%; tC2Q: 0.340, 4.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path19

Path Summary:

Slack	2.175
Data Arrival Time	7.972
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_13_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.972	0.591	tNET	RR	1	R16C18[1][A]	u_test/addr_add_r_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C18[1][A]	u_test/addr_add_r_13_s0/CLK
10.147	-0.032	tSu		1	R16C18[1][A]	u_test/addr_add_r_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.521%; route: 4.997, 64.120%; tC2Q: 0.340, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path20

Path Summary:

Slack	2.175
Data Arrival Time	7.972
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_16_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.972	0.591	tNET	RR	1	R16C18[0][B]	u_test/addr_add_r_16_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C18[0][B]	u_test/addr_add_r_16_s0/CLK
10.147	-0.032	tSu		1	R16C18[0][B]	u_test/addr_add_r_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.521%; route: 4.997, 64.120%; tC2Q: 0.340, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path21

Path Summary:

Slack	2.175
Data Arrival Time	7.972
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_17_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.972	0.591	tNET	RR	1	R16C18[0][A]	u_test/addr_add_r_17_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C18[0][A]	u_test/addr_add_r_17_s0/CLK
10.147	-0.032	tSu		1	R16C18[0][A]	u_test/addr_add_r_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.521%; route: 4.997, 64.120%; tC2Q: 0.340, 4.358%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path22

Path Summary:

Slack	2.178
Data Arrival Time	7.969
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_7_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.969	0.588	tNET	RR	1	R16C17[2][A]	u_test/addr_add_r_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C17[2][A]	u_test/addr_add_r_7_s0/CLK
10.147	-0.032	tSu		1	R16C17[2][A]	u_test/addr_add_r_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.535%; route: 4.993, 64.105%; tC2Q: 0.340, 4.360%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path23

Path Summary:

Slack	2.178
Data Arrival Time	7.969
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_8_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.969	0.588	tNET	RR	1	R16C17[2][B]	u_test/addr_add_r_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C17[2][B]	u_test/addr_add_r_8_s0/CLK
10.147	-0.032	tSu		1	R16C17[2][B]	u_test/addr_add_r_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.535%; route: 4.993, 64.105%; tC2Q: 0.340, 4.360%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path24

Path Summary:

Slack	2.178
Data Arrival Time	7.969
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_9_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.969	0.588	tNET	RR	1	R16C17[1][A]	u_test/addr_add_r_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C17[1][A]	u_test/addr_add_r_9_s0/CLK
10.147	-0.032	tSu		1	R16C17[1][A]	u_test/addr_add_r_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.535%; route: 4.993, 64.105%; tC2Q: 0.340, 4.360%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path25

Path Summary:

Slack	2.243
Data Arrival Time	7.904
Data Required Time	10.147
From	u_test/curr_state_2_s0
To	u_test/addr_add_r_6_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R8C17[0][A]	u_test/curr_state_2_s0/CLK
0.519	0.340	tC2Q	RF	7	R8C17[0][A]	u_test/curr_state_2_s0/Q
1.494	0.975	tNET	FF	1	R9C19[0][A]	u_test/n303_s3/I2
2.259	0.765	tINS	FF	8	R9C19[0][A]	u_test/n303_s3/F
3.004	0.745	tNET	FF	1	R7C17[3][A]	u_test/RD_CNT_5_s4/I2
3.468	0.464	tINS	FF	7	R7C17[3][A]	u_test/RD_CNT_5_s4/F
4.683	1.215	tNET	FF	1	R11C21[2][A]	u_test/wr_data_31_s3/I2
5.448	0.765	tINS	FF	66	R11C21[2][A]	u_test/wr_data_31_s3/F
6.918	1.470	tNET	FF	1	R15C16[0][A]	u_test/addr_add_r_21_s5/I0
7.381	0.463	tINS	FR	16	R15C16[0][A]	u_test/addr_add_r_21_s5/F
7.904	0.523	tNET	RR	1	R16C16[0][A]	u_test/addr_add_r_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C16[0][A]	u_test/addr_add_r_6_s0/CLK
10.147	-0.032	tSu		1	R16C16[0][A]	u_test/addr_add_r_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 2.456, 31.799%; route: 4.929, 63.804%; tC2Q: 0.340, 4.397%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.420
Data Arrival Time	3.693
Data Required Time	3.272
From	rst_glb_cnt_28_s4
To	rst_glb_cnt_25_s0
Launch Clk	osc_clk_in:[R]
Latch Clk	osc_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[2][A]	rst_glb_cnt_28_s4/CLK
3.510	0.247	tC2Q	RR	30	R3C19[2][A]	rst_glb_cnt_28_s4/Q
3.693	0.182	tNET	RR	1	R3C19[0][A]	rst_glb_cnt_25_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[0][A]	rst_glb_cnt_25_s0/CLK
3.272	0.009	tHld		1	R3C19[0][A]	rst_glb_cnt_25_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 42.477%; tC2Q: 0.247, 57.523%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.420
Data Arrival Time	3.693
Data Required Time	3.272
From	rst_glb_cnt_28_s4
To	rst_glb_cnt_26_s0
Launch Clk	osc_clk_in:[R]
Latch Clk	osc_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[2][A]	rst_glb_cnt_28_s4/CLK
3.510	0.247	tC2Q	RR	30	R3C19[2][A]	rst_glb_cnt_28_s4/Q
3.693	0.182	tNET	RR	1	R3C19[0][B]	rst_glb_cnt_26_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[0][B]	rst_glb_cnt_26_s0/CLK
3.272	0.009	tHld		1	R3C19[0][B]	rst_glb_cnt_26_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 42.477%; tC2Q: 0.247, 57.523%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.420
Data Arrival Time	3.693
Data Required Time	3.272
From	rst_glb_cnt_28_s4
To	rst_glb_cnt_27_s0
Launch Clk	osc_clk_in:[R]
Latch Clk	osc_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[2][A]	rst_glb_cnt_28_s4/CLK
3.510	0.247	tC2Q	RR	30	R3C19[2][A]	rst_glb_cnt_28_s4/Q
3.693	0.182	tNET	RR	1	R3C19[1][A]	rst_glb_cnt_27_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C19[1][A]	rst_glb_cnt_27_s0/CLK
3.272	0.009	tHld		1	R3C19[1][A]	rst_glb_cnt_27_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 42.477%; tC2Q: 0.247, 57.523%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.422
Data Arrival Time	4.890
Data Required Time	4.468
From	u_la0_top/data_register_33_s0
To	u_la0_top/data_register_32_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_33_s0/CLK
4.715	0.247	tC2Q	RR	1		u_la0_top/data_register_33_s0/Q
4.890	0.175	tNET	RR	1		u_la0_top/data_register_32_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_32_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_32_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path5

Path Summary:

Slack	0.422
Data Arrival Time	0.558
Data Required Time	0.136
From	u_la0_top/u_ao_mem_ctrl/data_reg_dly_48_s0
To	u_la0_top/u_ao_mem_ctrl/data_reg_48_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R7C14[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_48_s0/CLK
0.383	0.247	tC2Q	RR	1	R7C14[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_dly_48_s0/Q
0.558	0.175	tNET	RR	1	R7C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R7C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/CLK
0.136	0.000	tHld		1	R7C14[0][A]	u_la0_top/u_ao_mem_ctrl/data_reg_48_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack	0.422
Data Arrival Time	0.558
Data Required Time	0.136
From	u_la0_top/internal_reg_force_triger_syn_0_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R4C2[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.383	0.247	tC2Q	RR	1	R4C2[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/Q
0.558	0.175	tNET	RR	1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.136	0.000	tHld		1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack	0.422
Data Arrival Time	0.558
Data Required Time	0.136
From	u_la0_top/rst_ao_syn_s0
To	u_la0_top/rst_ao_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][A]	u_la0_top/rst_ao_syn_s0/CLK
0.383	0.247	tC2Q	RR	1	R5C5[1][A]	u_la0_top/rst_ao_syn_s0/Q
0.558	0.175	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.136	0.000	tHld		1	R5C5[1][B]	u_la0_top/rst_ao_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_la0_top/data_register_63_s0
To	u_la0_top/internal_register_select_10_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_63_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_63_s0/Q
4.891	0.176	tNET	RR	1		u_la0_top/internal_register_select_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/internal_register_select_10_s0/CLK
4.468	0.000	tHld		1		u_la0_top/internal_register_select_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path9

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_la0_top/data_register_13_s0
To	u_la0_top/data_register_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_13_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_13_s0/Q
4.891	0.176	tNET	RR	1		u_la0_top/data_register_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_12_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path10

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_la0_top/data_register_52_s0
To	u_la0_top/data_register_51_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_52_s0/CLK
4.715	0.247	tC2Q	RR	2		u_la0_top/data_register_52_s0/Q
4.891	0.176	tNET	RR	1		u_la0_top/data_register_51_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_51_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_51_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path11

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_la0_top/data_register_72_s0
To	u_la0_top/data_register_71_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_72_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_72_s0/Q
4.891	0.176	tNET	RR	1		u_la0_top/data_register_71_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_71_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_71_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path12

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_icon_top/input_shift_reg_4_s0
To	u_icon_top/input_shift_reg_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_icon_top/input_shift_reg_4_s0/CLK
4.715	0.247	tC2Q	RR	2		u_icon_top/input_shift_reg_4_s0/Q
4.891	0.176	tNET	RR	1		u_icon_top/input_shift_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_icon_top/input_shift_reg_3_s0/CLK
4.468	0.000	tHld		1		u_icon_top/input_shift_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path13

Path Summary:

Slack	0.423
Data Arrival Time	4.891
Data Required Time	4.468
From	u_icon_top/enable_reg_1_s0
To	u_icon_top/enable_reg_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_icon_top/enable_reg_1_s0/CLK
4.715	0.247	tC2Q	RR	3		u_icon_top/enable_reg_1_s0/Q
4.891	0.176	tNET	RR	1		u_icon_top/enable_reg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_icon_top/enable_reg_0_s0/CLK
4.468	0.000	tHld		1		u_icon_top/enable_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path14

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_64_s0
To	u_la0_top/internal_register_select_11_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_64_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_64_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/internal_register_select_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/internal_register_select_11_s0/CLK
4.468	0.000	tHld		1		u_la0_top/internal_register_select_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path15

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_65_s0
To	u_la0_top/internal_register_select_12_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_65_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_65_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/internal_register_select_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/internal_register_select_12_s0/CLK
4.468	0.000	tHld		1		u_la0_top/internal_register_select_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path16

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_66_s0
To	u_la0_top/internal_register_select_13_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_66_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_66_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/internal_register_select_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/internal_register_select_13_s0/CLK
4.468	0.000	tHld		1		u_la0_top/internal_register_select_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path17

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_62_s0
To	u_la0_top/data_register_61_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_62_s0/CLK
4.715	0.247	tC2Q	RR	4		u_la0_top/data_register_62_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/data_register_61_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_61_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_61_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path18

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_66_s0
To	u_la0_top/data_register_65_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_66_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_66_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/data_register_65_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_65_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_65_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path19

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_68_s0
To	u_la0_top/data_register_67_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_68_s0/CLK
4.715	0.247	tC2Q	RR	5		u_la0_top/data_register_68_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/data_register_67_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_67_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_67_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path20

Path Summary:

Slack	0.424
Data Arrival Time	4.892
Data Required Time	4.468
From	u_la0_top/data_register_70_s0
To	u_la0_top/data_register_69_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_70_s0/CLK
4.715	0.247	tC2Q	RR	3		u_la0_top/data_register_70_s0/Q
4.892	0.177	tNET	RR	1		u_la0_top/data_register_69_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_69_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_69_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	4.893
Data Required Time	4.468
From	u_la0_top/data_register_5_s0
To	u_la0_top/data_register_4_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_5_s0/CLK
4.715	0.247	tC2Q	RR	4		u_la0_top/data_register_5_s0/Q
4.893	0.178	tNET	RR	1		u_la0_top/data_register_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_4_s0/CLK
4.468	0.000	tHld		1		u_la0_top/data_register_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.178, 41.854%; tC2Q: 0.247, 58.146%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path22

Path Summary:

Slack	0.426
Data Arrival Time	4.894
Data Required Time	4.468
From	u_la0_top/data_register_1_s0
To	u_la0_top/internal_reg_trig_level_max_1_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/data_register_1_s0/CLK
4.715	0.247	tC2Q	RR	8		u_la0_top/data_register_1_s0/Q
4.894	0.179	tNET	RR	1		u_la0_top/internal_reg_trig_level_max_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1		tck_ibuf/I
3.126	3.126	tINS	RR	1		tck_ibuf/O
3.126	0.000	tNET	RR	1		u_gw_jtag/tck_pad_i
3.752	0.626	tINS	RR	291		u_gw_jtag/tck_o
4.468	0.716	tNET	RR	1		u_la0_top/internal_reg_trig_level_max_1_s0/CLK
4.468	0.000	tHld		1		u_la0_top/internal_reg_trig_level_max_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.179, 41.973%; tC2Q: 0.247, 58.027%
Required Clock Path Delay	cell: 3.752, 83.979%; route: 0.716, 16.021%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1
To	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1
Launch Clk	osc_clk_in:[R]
Latch Clk	osc_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/CLK
3.510	0.247	tC2Q	RR	3	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/Q
3.512	0.002	tNET	RR	1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/n39_s1/I2
3.788	0.276	tINS	RF	1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/n39_s1/F
3.788	0.000	tNET	FF	1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1/CLK
3.263	0.000	tHld		1	R6C8[0][A]	u_hpram_top/u_hpram_top_0/u_hpram_sync/lock_cnt_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	rst_glb_cnt_0_s2
To	rst_glb_cnt_0_s2
Launch Clk	osc_clk_in:[R]
Latch Clk	osc_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C14[0][A]	rst_glb_cnt_0_s2/CLK
3.510	0.247	tC2Q	RR	2	R3C14[0][A]	rst_glb_cnt_0_s2/Q
3.512	0.002	tNET	RR	1	R3C14[0][A]	n34_s3/I0
3.788	0.276	tINS	RF	1	R3C14[0][A]	n34_s3/F
3.788	0.000	tNET	FF	1	R3C14[0][A]	rst_glb_cnt_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					osc_clk_in
0.000	0.000	tCL	RR	1	IOB22[A]	clk_ibuf/I
3.126	3.126	tINS	RR	62	IOB22[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R3C14[0][A]	rst_glb_cnt_0_s2/CLK
3.263	0.000	tHld		1	R3C14[0][A]	rst_glb_cnt_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.660
Data Required Time	0.136
From	u_test/check_data_2_s1
To	u_test/check_data_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R9C16[0][A]	u_test/check_data_2_s1/CLK
0.383	0.247	tC2Q	RR	4	R9C16[0][A]	u_test/check_data_2_s1/Q
0.384	0.002	tNET	RR	1	R9C16[0][A]	u_test/n1229_s4/I1
0.660	0.276	tINS	RF	1	R9C16[0][A]	u_test/n1229_s4/F
0.660	0.000	tNET	FF	1	R9C16[0][A]	u_test/check_data_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R9C16[0][A]	u_test/check_data_2_s1/CLK
0.136	0.000	tHld		1	R9C16[0][A]	u_test/check_data_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.657
Data Arrival Time	2.490
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.490	1.971	tNET	FF	1	R11C16[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R11C16[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.147	-0.032	tSu		1	R11C16[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.971, 85.303%; tC2Q: 0.340, 14.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path2

Path Summary:

Slack	7.657
Data Arrival Time	2.490
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.490	1.971	tNET	FF	1	R15C16[1][A]	u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R15C16[1][A]	u_la0_top/internal_reg_start_dly_1_s0/CLK
10.147	-0.032	tSu		1	R15C16[1][A]	u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.971, 85.303%; tC2Q: 0.340, 14.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path3

Path Summary:

Slack	7.812
Data Arrival Time	2.335
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.335	1.816	tNET	FF	1	R16C14[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R16C14[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.147	-0.032	tSu		1	R16C14[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.816, 84.248%; tC2Q: 0.340, 15.752%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path4

Path Summary:

Slack	8.016
Data Arrival Time	2.131
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.131	1.612	tNET	FF	1	R13C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R13C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.147	-0.032	tSu		1	R13C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.612, 82.599%; tC2Q: 0.340, 17.401%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path5

Path Summary:

Slack	8.016
Data Arrival Time	2.131
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.131	1.612	tNET	FF	1	R13C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R13C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.147	-0.032	tSu		1	R13C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.612, 82.599%; tC2Q: 0.340, 17.401%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path6

Path Summary:

Slack	8.016
Data Arrival Time	2.131
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.131	1.612	tNET	FF	1	R13C15[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R13C15[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.147	-0.032	tSu		1	R13C15[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.612, 82.599%; tC2Q: 0.340, 17.401%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path7

Path Summary:

Slack	8.016
Data Arrival Time	2.131
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.131	1.612	tNET	FF	1	R13C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R13C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.147	-0.032	tSu		1	R13C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.612, 82.599%; tC2Q: 0.340, 17.401%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path8

Path Summary:

Slack	8.030
Data Arrival Time	2.118
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.118	1.599	tNET	FF	1	R14C15[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C15[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.147	-0.032	tSu		1	R14C15[0][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.599, 82.479%; tC2Q: 0.340, 17.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path9

Path Summary:

Slack	8.030
Data Arrival Time	2.118
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.118	1.599	tNET	FF	1	R14C15[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C15[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.147	-0.032	tSu		1	R14C15[0][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.599, 82.479%; tC2Q: 0.340, 17.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path10

Path Summary:

Slack	8.030
Data Arrival Time	2.118
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.118	1.599	tNET	FF	1	R14C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.147	-0.032	tSu		1	R14C15[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.599, 82.479%; tC2Q: 0.340, 17.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path11

Path Summary:

Slack	8.030
Data Arrival Time	2.118
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.118	1.599	tNET	FF	1	R14C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.147	-0.032	tSu		1	R14C15[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.599, 82.479%; tC2Q: 0.340, 17.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path12

Path Summary:

Slack	8.030
Data Arrival Time	2.118
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.118	1.599	tNET	FF	1	R14C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R14C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.147	-0.032	tSu		1	R14C15[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.599, 82.479%; tC2Q: 0.340, 17.521%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path13

Path Summary:

Slack	8.141
Data Arrival Time	2.006
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
2.006	1.487	tNET	FF	1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.147	-0.032	tSu		1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.487, 81.405%; tC2Q: 0.340, 18.595%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path14

Path Summary:

Slack	8.155
Data Arrival Time	1.992
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/trigger_seq_start_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.992	1.473	tNET	FF	1	R4C2[2][A]	u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R4C2[2][A]	u_la0_top/trigger_seq_start_s1/CLK
10.147	-0.032	tSu		1	R4C2[2][A]	u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.473, 81.267%; tC2Q: 0.340, 18.733%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path15

Path Summary:

Slack	8.155
Data Arrival Time	1.992
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.992	1.473	tNET	FF	1	R4C2[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R4C2[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.147	-0.032	tSu		1	R4C2[1][A]	u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.473, 81.267%; tC2Q: 0.340, 18.733%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path16

Path Summary:

Slack	8.155
Data Arrival Time	1.992
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.992	1.473	tNET	FF	1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.147	-0.032	tSu		1	R4C2[1][B]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.473, 81.267%; tC2Q: 0.340, 18.733%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path17

Path Summary:

Slack	8.159
Data Arrival Time	1.988
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.988	1.470	tNET	FF	1	R15C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R15C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.147	-0.032	tSu		1	R15C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.470, 81.228%; tC2Q: 0.340, 18.772%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path18

Path Summary:

Slack	8.159
Data Arrival Time	1.988
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.988	1.470	tNET	FF	1	R15C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R15C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
10.147	-0.032	tSu		1	R15C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.470, 81.228%; tC2Q: 0.340, 18.772%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path19

Path Summary:

Slack	8.159
Data Arrival Time	1.988
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.988	1.470	tNET	FF	1	R15C2[2][A]	u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R15C2[2][A]	u_la0_top/triger_level_cnt_1_s1/CLK
10.147	-0.032	tSu		1	R15C2[2][A]	u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.470, 81.228%; tC2Q: 0.340, 18.772%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path20

Path Summary:

Slack	8.159
Data Arrival Time	1.988
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.988	1.470	tNET	FF	1	R15C2[2][B]	u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R15C2[2][B]	u_la0_top/triger_level_cnt_2_s1/CLK
10.147	-0.032	tSu		1	R15C2[2][B]	u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.470, 81.228%; tC2Q: 0.340, 18.772%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path21

Path Summary:

Slack	8.160
Data Arrival Time	1.987
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.987	1.468	tNET	FF	1	R2C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R2C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.147	-0.032	tSu		1	R2C11[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.468, 81.216%; tC2Q: 0.340, 18.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path22

Path Summary:

Slack	8.160
Data Arrival Time	1.987
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.987	1.468	tNET	FF	1	R2C11[2][B]	u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R2C11[2][B]	u_la0_top/capture_window_sel_2_s1/CLK
10.147	-0.032	tSu		1	R2C11[2][B]	u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.468, 81.216%; tC2Q: 0.340, 18.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path23

Path Summary:

Slack	8.160
Data Arrival Time	1.987
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.987	1.468	tNET	FF	1	R2C11[2][A]	u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R2C11[2][A]	u_la0_top/capture_window_sel_3_s1/CLK
10.147	-0.032	tSu		1	R2C11[2][A]	u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.468, 81.216%; tC2Q: 0.340, 18.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path24

Path Summary:

Slack	8.160
Data Arrival Time	1.987
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.987	1.468	tNET	FF	1	R2C11[0][B]	u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R2C11[0][B]	u_la0_top/capture_window_sel_5_s1/CLK
10.147	-0.032	tSu		1	R2C11[0][B]	u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.468, 81.216%; tC2Q: 0.340, 18.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Path25

Path Summary:

Slack	8.160
Data Arrival Time	1.987
Data Required Time	10.147
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_6_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.179	0.179	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.519	0.340	tC2Q	RF	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.987	1.468	tNET	FF	1	R2C11[0][A]	u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_x1
10.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.179	0.179	tNET	RR	1	R2C11[0][A]	u_la0_top/capture_window_sel_6_s1/CLK
10.147	-0.032	tSu		1	R2C11[0][A]	u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.468, 81.216%; tC2Q: 0.340, 18.784%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.179, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.825
Data Arrival Time	0.970
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
0.970	0.588	tNET	RR	1	R3C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R3C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.145	0.009	tHld		1	R3C9[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.588, 70.402%; tC2Q: 0.247, 29.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path2

Path Summary:

Slack	0.830
Data Arrival Time	0.975
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
0.975	0.592	tNET	RR	1	R6C9[2][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C9[2][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
0.145	0.009	tHld		1	R6C9[2][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.592, 70.564%; tC2Q: 0.247, 29.436%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path3

Path Summary:

Slack	0.830
Data Arrival Time	0.975
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
0.975	0.592	tNET	RR	1	R6C9[2][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C9[2][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
0.145	0.009	tHld		1	R6C9[2][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.592, 70.564%; tC2Q: 0.247, 29.436%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path4

Path Summary:

Slack	0.830
Data Arrival Time	0.975
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
0.975	0.592	tNET	RR	1	R6C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
0.145	0.009	tHld		1	R6C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.592, 70.564%; tC2Q: 0.247, 29.436%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path5

Path Summary:

Slack	0.830
Data Arrival Time	0.975
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
0.975	0.592	tNET	RR	1	R6C9[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C9[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
0.145	0.009	tHld		1	R6C9[1][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.592, 70.564%; tC2Q: 0.247, 29.436%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path6

Path Summary:

Slack	0.862
Data Arrival Time	1.007
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.007	0.624	tNET	RR	1	R6C8[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C8[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.145	0.009	tHld		1	R6C8[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 71.656%; tC2Q: 0.247, 28.344%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path7

Path Summary:

Slack	0.862
Data Arrival Time	1.007
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.007	0.624	tNET	RR	1	R6C2[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C2[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
0.145	0.009	tHld		1	R6C2[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 71.656%; tC2Q: 0.247, 28.344%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path8

Path Summary:

Slack	0.865
Data Arrival Time	1.010
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_end_dly_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.010	0.627	tNET	RR	1	R2C4[1][A]	u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R2C4[1][A]	u_la0_top/capture_end_dly_s0/CLK
0.145	0.009	tHld		1	R2C4[1][A]	u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.627, 71.746%; tC2Q: 0.247, 28.254%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path9

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C10[2][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C10[2][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.145	0.009	tHld		1	R5C10[2][A]	u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path10

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.145	0.009	tHld		1	R5C9[1][B]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path11

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C10[2][B]	u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C10[2][B]	u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
0.145	0.009	tHld		1	R5C10[2][B]	u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path12

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C9[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C9[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
0.145	0.009	tHld		1	R5C9[1][A]	u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path13

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C10[1][A]	u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C10[1][A]	u_la0_top/triger_level_cnt_0_s3/CLK
0.145	0.009	tHld		1	R5C10[1][A]	u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path14

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C9[0][A]	u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C9[0][A]	u_la0_top/triger_level_cnt_3_s1/CLK
0.145	0.009	tHld		1	R5C9[0][A]	u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path15

Path Summary:

Slack	0.868
Data Arrival Time	1.013
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.013	0.630	tNET	RR	1	R5C10[1][B]	u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C10[1][B]	u_la0_top/triger_s0/CLK
0.145	0.009	tHld		1	R5C10[1][B]	u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.630, 71.850%; tC2Q: 0.247, 28.150%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path16

Path Summary:

Slack	0.877
Data Arrival Time	1.022
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.022	0.640	tNET	RR	1	R6C15[0][A]	u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R6C15[0][A]	u_la0_top/capture_window_sel_4_s1/CLK
0.145	0.009	tHld		1	R6C15[0][A]	u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.640, 72.142%; tC2Q: 0.247, 27.858%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path17

Path Summary:

Slack	0.878
Data Arrival Time	1.023
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.023	0.641	tNET	RR	1	R15C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R15C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.145	0.009	tHld		1	R15C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.641, 72.174%; tC2Q: 0.247, 27.826%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path18

Path Summary:

Slack	0.878
Data Arrival Time	1.023
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.023	0.641	tNET	RR	1	R15C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R15C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.145	0.009	tHld		1	R15C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.641, 72.174%; tC2Q: 0.247, 27.826%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path19

Path Summary:

Slack	0.879
Data Arrival Time	1.024
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_0_s3
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.024	0.641	tNET	RR	1	R12C7[1][B]	u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R12C7[1][B]	u_la0_top/capture_window_sel_0_s3/CLK
0.145	0.009	tHld		1	R12C7[1][B]	u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.641, 72.195%; tC2Q: 0.247, 27.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path20

Path Summary:

Slack	0.879
Data Arrival Time	1.024
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_1_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.024	0.641	tNET	RR	1	R12C7[2][A]	u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R12C7[2][A]	u_la0_top/capture_window_sel_1_s1/CLK
0.145	0.009	tHld		1	R12C7[2][A]	u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.641, 72.195%; tC2Q: 0.247, 27.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path21

Path Summary:

Slack	0.879
Data Arrival Time	1.024
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.024	0.641	tNET	RR	1	R12C7[1][A]	u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R12C7[1][A]	u_la0_top/internal_reg_start_dly_0_s0/CLK
0.145	0.009	tHld		1	R12C7[1][A]	u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.641, 72.195%; tC2Q: 0.247, 27.805%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path22

Path Summary:

Slack	0.880
Data Arrival Time	1.024
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.024	0.642	tNET	RR	1	R13C8[0][A]	u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R13C8[0][A]	u_la0_top/internal_reg_start_syn_0_s0/CLK
0.145	0.009	tHld		1	R13C8[0][A]	u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.642, 72.210%; tC2Q: 0.247, 27.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path23

Path Summary:

Slack	0.880
Data Arrival Time	1.024
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.024	0.642	tNET	RR	1	R13C8[0][B]	u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R13C8[0][B]	u_la0_top/internal_reg_start_syn_1_s0/CLK
0.145	0.009	tHld		1	R13C8[0][B]	u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.642, 72.210%; tC2Q: 0.247, 27.790%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path24

Path Summary:

Slack	0.882
Data Arrival Time	1.027
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.027	0.645	tNET	RR	1	R3C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R3C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.145	0.009	tHld		1	R3C10[2][A]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.645, 72.296%; tC2Q: 0.247, 27.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Path25

Path Summary:

Slack	0.882
Data Arrival Time	1.027
Data Required Time	0.145
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk_x1:[R]
Latch Clk	clk_x1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R5C5[1][B]	u_la0_top/rst_ao_s0/CLK
0.383	0.247	tC2Q	RR	61	R5C5[1][B]	u_la0_top/rst_ao_s0/Q
1.027	0.645	tNET	RR	1	R3C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_x1
0.000	0.000	tCL	RR	853	BOTTOMSIDE[1]	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
0.136	0.136	tNET	RR	1	R3C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.145	0.009	tHld		1	R3C10[2][B]	u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.645, 72.296%; tC2Q: 0.247, 27.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.136, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rd_data_d_31_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rd_data_d_31_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rd_data_d_31_s0/CLK

MPW2

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rd_data_d_30_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rd_data_d_30_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rd_data_d_30_s0/CLK

MPW3

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rdbk_data_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rdbk_data_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rdbk_data_13_s0/CLK

MPW4

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rdbk_data_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rdbk_data_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rdbk_data_5_s0/CLK

MPW5

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rdbk_data_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rdbk_data_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rdbk_data_1_s0/CLK

MPW6

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rvld_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rvld_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rvld_s0/CLK

MPW7

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/rd_data_valid_d_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/rd_data_valid_d_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/rd_data_valid_d_0_s0/CLK

MPW8

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_35_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_35_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/CA_35_s0/CLK

MPW9

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_test/addr_add_r_21_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_test/addr_add_r_21_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_test/addr_add_r_21_s0/CLK

MPW10

MPW Summary:

Slack:	4.019
Actual Width:	4.945
Required Width:	0.926
Type:	Low Pulse Width
Clock:	clk_x1
Objects:	u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk_x1
5.000	0.000	tCL	FF	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
5.190	0.190	tNET	FF	u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk_x1
10.000	0.000	tCL	RR	u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT
10.136	0.136	tNET	RR	u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
853	clk_x1	1.344	0.190
265	n536_6	16.740	2.429
124	init_calib_d	2.785	3.511
66	u_test/wr_data_31_5	1.344	1.728
65	u_hpram_top/u_hpram_top_0/rd_data_valid_d0[0]	6.452	2.646
65	u_test/wr_data_add_31_11	3.673	1.398
62	clk_d	13.446	0.195
51	u_test/n303_7	3.567	1.482
40	u_hpram_top/u_hpram_top_0/u_hpram_init/read_calibration[0].wr_ptr[0]	3.651	1.463
36	u_hpram_top/u_hpram_top_0/u_hpram_init/n1663_10	1.784	1.369

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R7C17	45.83%
R13C11	45.83%
R10C3	45.83%
R8C8	41.67%
R8C14	41.67%
R12C12	41.67%
R10C4	41.67%
R14C8	38.89%
R8C13	38.89%
R13C14	38.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name osc_clk_in -period 20 -waveform {0 10} [get_ports {clk}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name memory_clk -source [get_ports {clk}] -master_clock osc_clk_in -multiply_by 4 [get_pins {your_instance_name/pllvr_inst/CLKOUT}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name clk_x1 -source [get_pins {your_instance_name/pllvr_inst/CLKOUT}] -master_clock memory_clk -divide_by 2 -multiply_by 1 [get_pins {u_hpram_top/u_hpram_top_0/clkdiv/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {osc_clk_in}] -group [get_clocks {memory_clk}] -group [get_clocks {clk_x1}]