PnR Messages

Report Title PnR Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\hpram.vg
Gao Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\impl\gao\gao.v
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.cst
Timing Constraints File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.sdc
Tool Version V1.9.11.02 (64-bit)
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Wed May 28 14:59:40 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.182s, Elapsed time = 0h 0m 0.182s Placement Phase 1: CPU time = 0h 0m 0.081s, Elapsed time = 0h 0m 0.081s Placement Phase 2: CPU time = 0h 0m 0.186s, Elapsed time = 0h 0m 0.186s Placement Phase 3: CPU time = 0h 0m 0.85s, Elapsed time = 0h 0m 0.85s Placement Phase GAO : CPU time = 0h 0m 0.05s, Elapsed time = 0h 0m 0.05s Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.094s, Elapsed time = 0h 0m 0.094s Routing Phase 2: CPU time = 0h 0m 0.49s, Elapsed time = 0h 0m 0.49s Routing Phase 3: CPU time = 0h 0m 0.636s, Elapsed time = 0h 0m 0.635s Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 330MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1035/4608 23%
    --LUT,ALU,ROM16 1035(954 LUT, 81 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 715/3651 20%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 714/3456 21%
    --I/O Register as Latch 0/195 0%
    --I/O Register as FF 1/195 <1%
CLS 671/2304 30%
I/O Port 3/39 8%
I/O Buf 3 -
    --Input Buf 1 -
    --Output Buf 2 -
    --Inout Buf 0 -
IOLOGIC 8 IDES4
12 OSER4
10 IODELAY
 38%
BSRAM 1 SDPB
1 SDPX9B
 20%

GAO Resource Usage Summary:

Resource Usage
Logic 482
    --LUT,ALU,ROM16 482(469 LUT, 13 ALU, 0 ROM16)
    --SSRAM(RAM16) 0
Register 460
I/O Port 57
I/O Buf 4
    --Input Buf 3
    --Output Buf 1
    --Inout Buf 0
BSRAM 3

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/90%
bank 1 1/1010%
bank 2 0/90%
bank 3 2/1119%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 3/8 38%
GCLK_PIN 1/5 20%
CLKDIV 1/6 17%
DHCEN 1/12 9%
DLL 1/2 50%
PLLVR 1/2 50%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY LEFT RIGHT
clk_x1 PRIMARY LEFT RIGHT
n536_6 LW -
u_hpram_top/u_hpram_top_0/ddr_rsti LW -
u_test/wr_data_31_5 LW -
memory_clk HCLK BANK0_BANK1_HCLK1 BANK4_BANK5_HCLK1

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 22/3 Y in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
O_hpram_ck[0] - p1-13/3 - out IOB23[A] - LVCMOS18 - NONE - - - - - - -
O_hpram_ck_n[0] - p1-14/3 - out IOB15[B] - LVCMOS18 - NONE - - - - - - -
O_hpram_reset_n[0] - p1-22/3 - out IOB5[B] - LVCMOS18 - NONE - - - - - - -
O_hpram_cs_n[0] - p1-15/3 - out IOB15[A] - LVCMOS18 - NONE - - - - - - -
init_calib - 45/1 N out IOT13[A] LPLL_T_in LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
error - 21/3 N out IOB16[B] GCLKC_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
IO_hpram_rwds[0] - p1-6/3 - io IOB29[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[0] - p1-19/3 - io IOB7[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[1] - p1-18/3 - io IOB7[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[2] - p1-17/3 - io IOB14[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[3] - p1-16/3 - io IOB14[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[4] - p1-10/3 - io IOB24[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[5] - p1-9/3 - io IOB25[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[6] - p1-8/3 - io IOB25[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[7] - p1-7/3 - io IOB29[A] - LVCMOS18 - UP - - - - - - -

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 tdi_pad_i in IOT2[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 tdo_pad_o out IOT2[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 tms_pad_i in IOT3[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 tck_pad_i in IOT3[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/0 - in IOT5[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/1 - in IOT11[B] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/1 init_calib out IOT13[A] LPLL_T_in LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
46/1 - in IOT13[B] LPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/1 - in IOT17[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/1 - in IOT17[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/1 - in IOT20[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/1 - in IOT20[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/1 - in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/1 - in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 - in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-22/3 O_hpram_reset_n[0] out IOB5[B] - LVCMOS18 - NONE - - - - - - -
16/3 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-19/3 IO_hpram_dq[0] io IOB7[A] - LVCMOS18 - UP - - - - - - -
p1-18/3 IO_hpram_dq[1] io IOB7[B] - LVCMOS18 - UP - - - - - - -
18/3 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-17/3 IO_hpram_dq[2] io IOB14[A] - LVCMOS18 - UP - - - - - - -
p1-16/3 IO_hpram_dq[3] io IOB14[B] - LVCMOS18 - UP - - - - - - -
p1-15/3 O_hpram_cs_n[0] out IOB15[A] - LVCMOS18 - NONE - - - - - - -
p1-14/3 O_hpram_ck_n[0] out IOB15[B] - LVCMOS18 - NONE - - - - - - -
20/3 - in IOB16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 error out IOB16[B] GCLKC_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
22/3 clk in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 - in IOB22[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-13/3 O_hpram_ck[0] out IOB23[A] - LVCMOS18 - NONE - - - - - - -
p1-10/3 IO_hpram_dq[4] io IOB24[B] - LVCMOS18 - UP - - - - - - -
p1-9/3 IO_hpram_dq[5] io IOB25[A] - LVCMOS18 - UP - - - - - - -
p1-8/3 IO_hpram_dq[6] io IOB25[B] - LVCMOS18 - UP - - - - - - -
p1-7/3 IO_hpram_dq[7] io IOB29[A] - LVCMOS18 - UP - - - - - - -
p1-6/3 IO_hpram_rwds[0] io IOB29[B] - LVCMOS18 - UP - - - - - - -
35/2 - in IOR2[A] RPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOR2[B] RPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 - in IOR9[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOR11[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/2 - in IOR11[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOR15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOR15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8