Power Messages
| Report Title | Power Analysis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\hpram.vg |
| Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.cst |
| Timing Constraints File | E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram.sdc |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW1NSR-LV4CQN48PC7/I6 |
| Device | GW1NSR-4C |
| Created Time | Wed May 28 14:59:40 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
| Grade | Commercial |
| Process | Typical |
| Ambient Temperature | 25.000 |
| Use Custom Theta JA | false |
| Heat Sink | None |
| Air Flow | LFM_0 |
| Use Custom Theta SA | false |
| Board Thermal Model | None |
| Use Custom Theta JB | false |
| Related Vcd File | |
| Related Saif File | |
| Filter Glitches | false |
| Default IO Toggle Rate | 0.125 |
| Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
| Total Power (mW) | 55.131 |
| Quiescent Power (mW) | 26.029 |
| Dynamic Power (mW) | 29.101 |
Thermal Information:
| Junction Temperature | 26.794 |
| Theta JA | 41.340 |
| Max Allowed Ambient Temperature | 83.206 |
Supply Information:
| Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
|---|---|---|---|---|
| VCC | 1.200 | 22.810 | 11.993 | 41.764 |
| VCCX | 3.300 | 0.340 | 3.000 | 11.021 |
| VCCIO18 | 1.800 | 0.338 | 0.965 | 2.346 |
Power Details
Power By Block Type:
| Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
|---|---|---|---|
| Logic | 0.433 | NA | 11.818 |
| IO | 4.464 | 2.290 | 24.250 |
| BSRAM | 8.616 | NA | NA |
| PLL | 5.579 | NA | NA |
| DLL | 12.288 | NA | NA |
Power By Hierarchy:
| Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
|---|---|---|
| hpram_syn_top | 26.916 | 26.916(26.885) |
| hpram_syn_top/u_hpram_top/ | 21.172 | 21.172(21.172) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/ | 21.172 | 21.172(8.837) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/matched_rvld[0].u_matched_rvld_fifo/ | 4.251 | 4.251(0.000) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_init/ | 0.119 | 0.119(0.000) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_sync/ | 0.012 | 0.012(0.000) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_wd/ | 4.456 | 4.456(4.429) |
| hpram_syn_top/u_hpram_top/u_hpram_top_0/u_hpram_wd/data_lane_gen[0].u_hpram_lane/ | 4.429 | 4.429(0.000) |
| hpram_syn_top/u_test/ | 0.134 | 0.134(0.000) |
| hpram_syn_top/your_instance_name/ | 5.579 | 5.579(0.000) |
Power By Clock Domain:
| Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
|---|---|---|
| clk_x1 | 100.000 | 9.007 |
| osc_clk_in | 50.000 | 5.623 |
| NO CLOCK DOMAIN | 0.000 | 0.000 |
| memory_clk | 200.000 | 12.297 |