Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP\PSRAM\HyperRAM_Memory_Interface\RefDesign\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\gowin_pllvr\gowin_pllvr.v E:\IP\PSRAM\HyperRAM_Memory_Interface\RefDesign\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram_syn_top.v E:\IP\PSRAM\HyperRAM_Memory_Interface\RefDesign\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hpram_test.v E:\IP\PSRAM\HyperRAM_Memory_Interface\RefDesign\Gowin_HyperRAM_Memory_Interface_RefDesign\project\src\hyperram_memory_interface\hyperram_memory_interface.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW1NSR-LV4CQN48PC7/I6 |
| Device | GW1NSR-4C |
| Created Time | Wed May 28 13:43:55 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | hpram_syn_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.266s, Peak memory usage = 214.684MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 214.684MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 214.684MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 214.684MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 214.684MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 214.684MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 214.684MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 214.684MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 214.684MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 214.684MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 214.684MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 1s, Peak memory usage = 242.918MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.191s, Peak memory usage = 242.918MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 242.918MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 242.918MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 3 |
| Embedded Port | 13 |
| I/O Buf | 16 |
| IBUF | 1 |
| OBUF | 6 |
| IOBUF | 9 |
| Register | 715 |
| DFF | 3 |
| DFFE | 28 |
| DFFP | 5 |
| DFFPE | 3 |
| DFFC | 334 |
| DFFCE | 342 |
| LUT | 948 |
| LUT2 | 216 |
| LUT3 | 291 |
| LUT4 | 441 |
| ALU | 72 |
| ALU | 72 |
| INV | 8 |
| INV | 8 |
| IOLOGIC | 30 |
| IDES4 | 8 |
| OSER4 | 12 |
| IODELAY | 10 |
| BSRAM | 2 |
| SDPB | 1 |
| SDPX9B | 1 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCEN | 1 |
| PLLVR | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1028(956 LUT, 72 ALU) / 4608 | 23% |
| Register | 715 / 3612 | 20% |
| --Register as Latch | 0 / 3612 | 0% |
| --Register as FF | 715 / 3612 | 20% |
| BSRAM | 2 / 10 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | your_instance_name/pllvr_inst/CLKOUT |
| 3 | your_instance_name/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 5.000 | 200.000 | 0.000 | 2.500 | clk_ibuf/I | clk | your_instance_name/pllvr_inst/CLKOUTP |
| 4 | your_instance_name/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | clk_ibuf/I | clk | your_instance_name/pllvr_inst/CLKOUTD |
| 5 | your_instance_name/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 15.000 | 66.667 | 0.000 | 7.500 | clk_ibuf/I | clk | your_instance_name/pllvr_inst/CLKOUTD3 |
| 6 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | your_instance_name/pllvr_inst/CLKOUT | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 118.762(MHz) | 6 | TOP |
| 2 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 134.223(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -2.238 |
| Data Arrival Time | 12.988 |
| Data Required Time | 10.750 |
| From | u_hpram_top/u_hpram_top/u_dll |
| To | u_hpram_top/u_hpram_top/u_hpram_wd/step_0_s1 |
| Launch Clk | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | |||
| 5.857 | 0.857 | tCL | RR | 1 | your_instance_name/pllvr_inst/CLKOUT |
| 6.395 | 0.538 | tNET | RR | 3 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN |
| 6.579 | 0.184 | tINS | RR | 22 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT |
| 7.117 | 0.538 | tNET | RR | 8 | u_hpram_top/u_hpram_top/u_dll/CLKIN |
| 7.536 | 0.420 | tINS | RF | 1 | u_hpram_top/u_hpram_top/u_dll/STEP[0] |
| 8.247 | 0.711 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/I1 |
| 9.022 | 0.774 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/COUT |
| 9.022 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/CIN |
| 9.064 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/COUT |
| 9.064 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/CIN |
| 9.106 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/COUT |
| 9.106 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/CIN |
| 9.149 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/COUT |
| 9.149 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/CIN |
| 9.191 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/COUT |
| 9.191 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/CIN |
| 9.233 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/COUT |
| 9.233 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/CIN |
| 9.275 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/COUT |
| 9.987 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/I1 |
| 10.801 | 0.814 | tINS | FF | 9 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/F |
| 11.512 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n203_s3/I0 |
| 12.277 | 0.765 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n203_s3/F |
| 12.988 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 10.539 | 0.539 | tCL | RR | 678 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
| 11.077 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_0_s1/CLK |
| 11.047 | -0.030 | tUnc | u_hpram_top/u_hpram_top/u_hpram_wd/step_0_s1 | ||
| 10.750 | -0.296 | tSu | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_0_s1 |
| Clock Skew: | -0.502 |
| Setup Relationship: | 5.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
| Arrival Data Path Delay: | cell: 3.026, 47.215%; route: 2.845, 44.392%; tC2Q: 0.538, 8.393% |
| Required Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
Path 2
Path Summary:| Slack | -0.296 |
| Data Arrival Time | 11.311 |
| Data Required Time | 11.015 |
| From | u_hpram_top/u_hpram_top/u_dll |
| To | u_hpram_top/u_hpram_top/u_hpram_wd/step_1_s0 |
| Launch Clk | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | |||
| 5.857 | 0.857 | tCL | RR | 1 | your_instance_name/pllvr_inst/CLKOUT |
| 6.395 | 0.538 | tNET | RR | 3 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN |
| 6.579 | 0.184 | tINS | RR | 22 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT |
| 7.117 | 0.538 | tNET | RR | 8 | u_hpram_top/u_hpram_top/u_dll/CLKIN |
| 7.536 | 0.420 | tINS | RF | 1 | u_hpram_top/u_hpram_top/u_dll/STEP[0] |
| 8.247 | 0.711 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/I1 |
| 9.022 | 0.774 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/COUT |
| 9.022 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/CIN |
| 9.064 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/COUT |
| 9.064 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/CIN |
| 9.106 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/COUT |
| 9.106 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/CIN |
| 9.149 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/COUT |
| 9.149 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/CIN |
| 9.191 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/COUT |
| 9.191 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/CIN |
| 9.233 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/COUT |
| 9.233 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/CIN |
| 9.275 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/COUT |
| 9.987 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/I1 |
| 10.773 | 0.786 | tINS | FR | 9 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/F |
| 11.311 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 10.539 | 0.539 | tCL | RR | 678 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
| 11.077 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_1_s0/CLK |
| 11.047 | -0.030 | tUnc | u_hpram_top/u_hpram_top/u_hpram_wd/step_1_s0 | ||
| 11.015 | -0.032 | tSu | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_1_s0 |
| Clock Skew: | -0.502 |
| Setup Relationship: | 5.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
| Arrival Data Path Delay: | cell: 2.234, 47.199%; route: 1.961, 41.433%; tC2Q: 0.538, 11.368% |
| Required Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
Path 3
Path Summary:| Slack | -0.296 |
| Data Arrival Time | 11.311 |
| Data Required Time | 11.015 |
| From | u_hpram_top/u_hpram_top/u_dll |
| To | u_hpram_top/u_hpram_top/u_hpram_wd/step_2_s0 |
| Launch Clk | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | |||
| 5.857 | 0.857 | tCL | RR | 1 | your_instance_name/pllvr_inst/CLKOUT |
| 6.395 | 0.538 | tNET | RR | 3 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN |
| 6.579 | 0.184 | tINS | RR | 22 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT |
| 7.117 | 0.538 | tNET | RR | 8 | u_hpram_top/u_hpram_top/u_dll/CLKIN |
| 7.536 | 0.420 | tINS | RF | 1 | u_hpram_top/u_hpram_top/u_dll/STEP[0] |
| 8.247 | 0.711 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/I1 |
| 9.022 | 0.774 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/COUT |
| 9.022 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/CIN |
| 9.064 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/COUT |
| 9.064 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/CIN |
| 9.106 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/COUT |
| 9.106 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/CIN |
| 9.149 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/COUT |
| 9.149 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/CIN |
| 9.191 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/COUT |
| 9.191 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/CIN |
| 9.233 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/COUT |
| 9.233 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/CIN |
| 9.275 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/COUT |
| 9.987 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/I1 |
| 10.773 | 0.786 | tINS | FR | 9 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/F |
| 11.311 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 10.539 | 0.539 | tCL | RR | 678 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
| 11.077 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_2_s0/CLK |
| 11.047 | -0.030 | tUnc | u_hpram_top/u_hpram_top/u_hpram_wd/step_2_s0 | ||
| 11.015 | -0.032 | tSu | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_2_s0 |
| Clock Skew: | -0.502 |
| Setup Relationship: | 5.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
| Arrival Data Path Delay: | cell: 2.234, 47.199%; route: 1.961, 41.433%; tC2Q: 0.538, 11.368% |
| Required Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
Path 4
Path Summary:| Slack | -0.296 |
| Data Arrival Time | 11.311 |
| Data Required Time | 11.015 |
| From | u_hpram_top/u_hpram_top/u_dll |
| To | u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s0 |
| Launch Clk | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | |||
| 5.857 | 0.857 | tCL | RR | 1 | your_instance_name/pllvr_inst/CLKOUT |
| 6.395 | 0.538 | tNET | RR | 3 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN |
| 6.579 | 0.184 | tINS | RR | 22 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT |
| 7.117 | 0.538 | tNET | RR | 8 | u_hpram_top/u_hpram_top/u_dll/CLKIN |
| 7.536 | 0.420 | tINS | RF | 1 | u_hpram_top/u_hpram_top/u_dll/STEP[0] |
| 8.247 | 0.711 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/I1 |
| 9.022 | 0.774 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/COUT |
| 9.022 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/CIN |
| 9.064 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/COUT |
| 9.064 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/CIN |
| 9.106 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/COUT |
| 9.106 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/CIN |
| 9.149 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/COUT |
| 9.149 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/CIN |
| 9.191 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/COUT |
| 9.191 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/CIN |
| 9.233 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/COUT |
| 9.233 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/CIN |
| 9.275 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/COUT |
| 9.987 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/I1 |
| 10.773 | 0.786 | tINS | FR | 9 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/F |
| 11.311 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 10.539 | 0.539 | tCL | RR | 678 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
| 11.077 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s0/CLK |
| 11.047 | -0.030 | tUnc | u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s0 | ||
| 11.015 | -0.032 | tSu | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_3_s0 |
| Clock Skew: | -0.502 |
| Setup Relationship: | 5.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
| Arrival Data Path Delay: | cell: 2.234, 47.199%; route: 1.961, 41.433%; tC2Q: 0.538, 11.368% |
| Required Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
Path 5
Path Summary:| Slack | -0.296 |
| Data Arrival Time | 11.311 |
| Data Required Time | 11.015 |
| From | u_hpram_top/u_hpram_top/u_dll |
| To | u_hpram_top/u_hpram_top/u_hpram_wd/step_4_s0 |
| Launch Clk | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | your_instance_name/pllvr_inst/CLKOUT.default_gen_clk | |||
| 5.857 | 0.857 | tCL | RR | 1 | your_instance_name/pllvr_inst/CLKOUT |
| 6.395 | 0.538 | tNET | RR | 3 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKIN |
| 6.579 | 0.184 | tINS | RR | 22 | u_hpram_top/u_hpram_top/u_dqce_clk_x2p/CLKOUT |
| 7.117 | 0.538 | tNET | RR | 8 | u_hpram_top/u_hpram_top/u_dll/CLKIN |
| 7.536 | 0.420 | tINS | RF | 1 | u_hpram_top/u_hpram_top/u_dll/STEP[0] |
| 8.247 | 0.711 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/I1 |
| 9.022 | 0.774 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s19/COUT |
| 9.022 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/CIN |
| 9.064 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s20/COUT |
| 9.064 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/CIN |
| 9.106 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s21/COUT |
| 9.106 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/CIN |
| 9.149 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s22/COUT |
| 9.149 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/CIN |
| 9.191 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s23/COUT |
| 9.191 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/CIN |
| 9.233 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s24/COUT |
| 9.233 | 0.000 | tNET | FF | 2 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/CIN |
| 9.275 | 0.042 | tINS | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n193_s25/COUT |
| 9.987 | 0.711 | tNET | FF | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/I1 |
| 10.773 | 0.786 | tINS | FR | 9 | u_hpram_top/u_hpram_top/u_hpram_wd/n259_s2/F |
| 11.311 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_4_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | |||
| 10.539 | 0.539 | tCL | RR | 678 | u_hpram_top/u_hpram_top/clkdiv/CLKOUT |
| 11.077 | 0.538 | tNET | RR | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_4_s0/CLK |
| 11.047 | -0.030 | tUnc | u_hpram_top/u_hpram_top/u_hpram_wd/step_4_s0 | ||
| 11.015 | -0.032 | tSu | 1 | u_hpram_top/u_hpram_top/u_hpram_wd/step_4_s0 |
| Clock Skew: | -0.502 |
| Setup Relationship: | 5.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |
| Arrival Data Path Delay: | cell: 2.234, 47.199%; route: 1.961, 41.433%; tC2Q: 0.538, 11.368% |
| Required Clock Path Delay: | cell: 0.184, 25.476%; route: 0.538, 74.524% |