Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.10.01_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.10.01\Gowin_HyperRAM_Memory_Interface_refDesign\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NSR-LV4CQN48PC7/I6
Device GW1NSR-4C
Created Time Thu Aug 8 10:19:24 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 101.203MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 101.203MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 101.203MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 101.203MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 101.203MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 101.203MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 101.203MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 101.203MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 101.203MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 101.203MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 101.203MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 101.203MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 130.371MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 130.371MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 130.371MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 130.371MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 57
I/O Buf 57
    IBUF 56
    OBUF 1
Register 460
    DFF 111
    DFFR 1
    DFFP 3
    DFFPE 33
    DFFC 33
    DFFCE 279
LUT 460
    LUT2 61
    LUT3 117
    LUT4 282
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 3
    SDPX9B 3
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 485(472 LUT, 13 ALU) / 4608 11%
Register 460 / 3570 13%
  --Register as Latch 0 / 3570 0%
  --Register as FF 460 / 3570 13%
BSRAM 3 / 10 30%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_x1 Base 20.000 50.0 0.000 10.000 clk_x1_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 50.000(MHz) 136.037(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.649
Data Arrival Time 7.593
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 175 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.878 0.340 tC2Q RF 3 u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n375_s2/I1
2.403 0.814 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n375_s2/F
3.115 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n372_s3/I0
3.879 0.765 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n372_s3/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n371_s1/I1
5.405 0.814 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n371_s1/F
6.116 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n371_s2/I0
6.881 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n371_s2/F
7.593 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 175 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.699
Data Arrival Time 7.543
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
To u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 175 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.878 0.340 tC2Q RF 3 u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n375_s2/I1
2.403 0.814 tINS FF 4 u_la0_top/u_ao_mem_ctrl/n375_s2/F
3.115 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n372_s3/I0
3.879 0.765 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n372_s3/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n370_s4/I0
5.355 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n370_s4/F
6.067 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n370_s5/I0
6.832 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n370_s5/F
7.543 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 175 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.108, 44.376%; route: 3.557, 50.776%; tC2Q: 0.340, 4.848%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.854
Data Arrival Time 7.387
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 175 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.878 0.340 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s5/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n465_s5/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s4/I0
5.355 0.765 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n465_s4/F
6.067 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n473_s1/I2
6.676 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n473_s1/F
7.387 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 175 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.953, 43.112%; route: 3.557, 51.929%; tC2Q: 0.340, 4.959%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.854
Data Arrival Time 7.387
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 175 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.878 0.340 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s5/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n465_s5/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s4/I0
5.355 0.765 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n465_s4/F
6.067 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n471_s1/I2
6.676 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n471_s1/F
7.387 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 175 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.953, 43.112%; route: 3.557, 51.929%; tC2Q: 0.340, 4.959%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.854
Data Arrival Time 7.387
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 175 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.878 0.340 tC2Q RF 5 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n465_s8/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s5/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n465_s5/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s4/I0
5.355 0.765 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n465_s4/F
6.067 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n468_s1/I2
6.676 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n468_s1/F
7.387 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 175 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.953, 43.112%; route: 3.557, 51.929%; tC2Q: 0.340, 4.959%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%