Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\impl\gwsynthesis\MJPEG_Decoder_proj.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\src\mjpeg_decoder.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\src\mjpeg_decoder.sdc
Tool Version	V1.9.10 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Thu Jun 20 15:22:42 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	51590
Numbers of Endpoints Analyzed	48607
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	20.000	50.000	0.000	10.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	50.152(MHz)	12	TOP
2	tck_pad_i	20.000(MHz)	76.125(MHz)	3	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.061	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[10]	clk:[R]	clk:[R]	20.000	-0.002	20.014
2	0.546	mem_data_1_mem_data_1_0_1_s/DO[0]	mem_data_1_mem_data_1_0_25_s/CE	clk:[R]	clk:[R]	20.000	0.000	19.363
3	0.582	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[9]	clk:[R]	clk:[R]	20.000	-0.002	19.493
4	0.583	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[11]	clk:[R]	clk:[R]	20.000	-0.002	19.491
5	0.619	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_1_s1/CE	clk:[R]	clk:[R]	20.000	-0.014	19.084
6	0.619	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_3_s1/CE	clk:[R]	clk:[R]	20.000	-0.014	19.084
7	0.643	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_4_s1/CE	clk:[R]	clk:[R]	20.000	0.002	19.044
8	0.643	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_5_s1/CE	clk:[R]	clk:[R]	20.000	0.002	19.044
9	0.763	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/rd_ptr_q1_0_s3/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	19.174
10	0.773	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[8]	clk:[R]	clk:[R]	20.000	-0.002	19.301
11	0.802	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_5_s1/CE	clk:[R]	clk:[R]	20.000	-0.007	18.894
12	0.830	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_ptr_q[8]_1_s1/CE	clk:[R]	clk:[R]	20.000	-0.029	18.888
13	0.871	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_12_s1/D	clk:[R]	clk:[R]	20.000	-0.004	19.069
14	0.891	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_0_s1/CE	clk:[R]	clk:[R]	20.000	-0.006	18.804
15	0.891	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_1_s1/CE	clk:[R]	clk:[R]	20.000	-0.006	18.804
16	0.891	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_2_s1/CE	clk:[R]	clk:[R]	20.000	-0.006	18.804
17	0.900	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_6_s1/D	clk:[R]	clk:[R]	20.000	-0.004	19.040
18	0.977	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_5_s1/D	clk:[R]	clk:[R]	20.000	0.006	18.954
19	1.071	mem_data_1_mem_data_1_0_1_s/DO[0]	mem_data_1_mem_data_1_0_23_s/CE	clk:[R]	clk:[R]	20.000	-0.009	18.848
20	1.072	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_9_s1/D	clk:[R]	clk:[R]	20.000	-0.002	18.866
21	1.108	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_ptr_q[14]_0_s1/CE	clk:[R]	clk:[R]	20.000	0.007	18.574
22	1.113	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_2_s1/CE	clk:[R]	clk:[R]	20.000	0.013	18.563
23	1.113	mem_data_1_mem_data_1_0_24_s/DO[0]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_6_s1/CE	clk:[R]	clk:[R]	20.000	0.013	18.563
24	1.131	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_3_s1/D	clk:[R]	clk:[R]	20.000	-0.013	18.819
25	1.261	mem_data_1_mem_data_1_0_1_s/DO[0]	mem_data_1_mem_data_1_0_21_s/CE	clk:[R]	clk:[R]	20.000	0.000	18.648

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.216	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/rd_addr_Cx_T_4_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s/ADB[8]	clk:[R]	clk:[R]	0.000	0.006	0.245
2	0.275	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
3	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_1_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
4	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
5	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_8_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
6	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
7	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_11_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_12_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
8	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_15_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
9	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_19_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
10	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
11	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_22_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
12	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_24_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
13	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_28_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
14	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_30_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
15	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_32_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
16	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_34_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
17	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_35_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
18	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_37_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
19	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_39_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
20	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_41_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
21	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_44_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
22	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_46_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
23	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_47_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_48_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
24	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_49_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_50_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
25	0.275	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_51_s0/Q	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_52_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.268	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	3.375
2	7.201	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.010	2.461
3	7.201	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.010	2.461
4	7.965	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.003	1.685
5	7.965	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.003	1.685
6	8.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.482
7	8.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.482
8	8.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.482
9	8.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.482
10	8.177	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.482
11	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
12	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
13	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
14	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
15	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
16	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
17	8.232	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.411
18	8.247	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR	clk:[F]	clk:[R]	10.000	0.012	1.394
19	8.247	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	10.000	0.012	1.394
20	8.259	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.010	1.384
21	8.543	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.116
22	8.543	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.007	1.116
23	8.560	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.005	1.097
24	8.637	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR	clk:[F]	clk:[R]	10.000	-0.002	1.017
25	8.637	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	-0.002	1.017

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.417	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.360
2	10.417	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.360
3	10.417	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.360
4	10.417	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.360
5	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	-10.000	0.003	0.368
6	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.368
7	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.368
8	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.368
9	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.368
10	10.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.003	0.368
11	10.489	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	-0.001	0.437
12	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
13	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
14	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
15	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
16	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
17	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
18	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
19	10.504	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.006	0.445
20	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458
21	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458
22	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458
23	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458
24	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458
25	10.516	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.004	0.458

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	7.751	8.751	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_2_s
2	7.751	8.751	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_7_s
3	7.751	8.751	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_15_s
4	7.751	8.751	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_22_s
5	7.751	8.751	1.000	Low Pulse Width	clk	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s
6	7.751	8.751	1.000	Low Pulse Width	clk	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cr_ram_inst/ram_ram_0_0_s
7	7.751	8.751	1.000	Low Pulse Width	clk	mem_data_1_mem_data_1_0_14_s
8	7.751	8.751	1.000	Low Pulse Width	clk	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/Y0/AllinOne/ram_ram_0_2_s
9	7.751	8.751	1.000	Low Pulse Width	clk	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s
10	7.751	8.751	1.000	Low Pulse Width	clk	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.061
Data Arrival Time	22.635
Data Required Time	22.696
From	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.621	1.939	tNET	RR	1	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/CLK
3.004	0.382	tC2Q	RR	26	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q
4.035	1.031	tNET	RR	1	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/I1
4.532	0.498	tINS	RR	6	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/F
5.851	1.319	tNET	RR	1	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/S0
6.104	0.252	tINS	RF	635	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/O
8.475	2.371	tNET	FF	1	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/I2
8.936	0.461	tINS	FR	2	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/F
10.352	1.416	tNET	RR	1	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/I1
10.869	0.516	tINS	RR	2	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/F
11.624	0.755	tNET	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/I0
12.085	0.461	tINS	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/F
12.243	0.157	tNET	RR	1	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/I3
12.508	0.265	tINS	RR	4	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/F
14.749	2.241	tNET	RR	2	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/I0
15.305	0.556	tINS	RF	1	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/COUT
15.305	0.000	tNET	FF	2	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/CIN
15.355	0.050	tINS	FR	1	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/COUT
15.355	0.000	tNET	RR	2	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/CIN
15.651	0.296	tINS	RR	1	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/SUM
16.926	1.275	tNET	RR	2	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/I0
17.489	0.563	tINS	RF	1	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/COUT
17.489	0.000	tNET	FF	2	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/CIN
17.539	0.050	tINS	FR	1	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/COUT
17.539	0.000	tNET	RR	2	R29C34[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21588_s0/CIN
17.835	0.296	tINS	RR	1	R29C34[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21588_s0/SUM
18.724	0.889	tNET	RR	1	R25C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_7_s9/I1
19.139	0.415	tINS	RR	1	R25C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_7_s9/F
19.139	0.000	tNET	RR	1	R25C35[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_7_s7/I1
19.275	0.136	tINS	RR	1	R25C35[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_7_s7/O
22.635	3.360	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/CLKB
22.696	0.072	tSu		1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%
Arrival Data Path Delay	cell: 4.816, 24.065%; route: 14.815, 74.024%; tC2Q: 0.382, 1.911%
Required Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%

Path2

Path Summary:

Slack	0.546
Data Arrival Time	21.977
Data Required Time	22.523
From	mem_data_1_mem_data_1_0_1_s
To	mem_data_1_mem_data_1_0_25_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/DO[0]
6.228	1.604	tNET	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/I3
6.643	0.415	tINS	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/F
7.990	1.348	tNET	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/I1
8.405	0.415	tINS	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/F
8.405	0.000	tNET	RR	1	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/I1
8.542	0.136	tINS	RR	82	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/O
9.864	1.322	tNET	RR	1	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/I0
10.279	0.415	tINS	RR	8	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/F
10.442	0.162	tNET	RR	1	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/I3
10.903	0.461	tINS	RR	7	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/F
12.405	1.502	tNET	RR	1	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/I1
12.927	0.521	tINS	RR	2	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/F
13.277	0.350	tNET	RR	1	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/I0
13.774	0.498	tINS	RR	7	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/F
15.033	1.259	tNET	RR	1	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/I2
15.448	0.415	tINS	RR	3	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/F
16.697	1.249	tNET	RR	1	R7C46[3][B]	mem_data_1_s572/I1
17.112	0.415	tINS	RR	32	R7C46[3][B]	mem_data_1_s572/F
21.977	4.865	tNET	RR	1	BSRAM_R28[18]	mem_data_1_mem_data_1_0_25_s/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.614	1.932	tNET	RR	1	BSRAM_R28[18]	mem_data_1_mem_data_1_0_25_s/CLK
22.523	-0.091	tSu		1	BSRAM_R28[18]	mem_data_1_mem_data_1_0_25_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.691, 19.064%; route: 13.661, 70.555%; tC2Q: 2.010, 10.381%
Required Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%

Path3

Path Summary:

Slack	0.582
Data Arrival Time	22.114
Data Required Time	22.696
From	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.621	1.939	tNET	RR	1	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/CLK
3.004	0.382	tC2Q	RR	26	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q
4.035	1.031	tNET	RR	1	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/I1
4.532	0.498	tINS	RR	6	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/F
5.851	1.319	tNET	RR	1	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/S0
6.104	0.252	tINS	RF	635	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/O
8.475	2.371	tNET	FF	1	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/I2
8.936	0.461	tINS	FR	2	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/F
10.352	1.416	tNET	RR	1	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/I1
10.869	0.516	tINS	RR	2	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/F
11.624	0.755	tNET	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/I0
12.085	0.461	tINS	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/F
12.243	0.157	tNET	RR	1	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/I3
12.508	0.265	tINS	RR	4	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/F
14.749	2.241	tNET	RR	2	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/I0
15.305	0.556	tINS	RF	1	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/COUT
15.305	0.000	tNET	FF	2	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/CIN
15.355	0.050	tINS	FR	1	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/COUT
15.355	0.000	tNET	RR	2	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/CIN
15.651	0.296	tINS	RR	1	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/SUM
16.926	1.275	tNET	RR	2	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/I0
17.489	0.563	tINS	RF	1	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/COUT
17.489	0.000	tNET	FF	2	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/CIN
17.733	0.244	tINS	FR	1	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/SUM
18.466	0.734	tNET	RR	1	R26C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_6_s9/I1
18.964	0.498	tINS	RR	1	R26C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_6_s9/F
18.964	0.000	tNET	RR	1	R26C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_6_s7/I1
19.100	0.136	tINS	RR	1	R26C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_6_s7/O
22.114	3.014	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/CLKB
22.696	0.072	tSu		1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%
Arrival Data Path Delay	cell: 4.796, 24.606%; route: 14.314, 73.432%; tC2Q: 0.382, 1.962%
Required Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%

Path4

Path Summary:

Slack	0.583
Data Arrival Time	22.112
Data Required Time	22.696
From	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.621	1.939	tNET	RR	1	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/CLK
3.004	0.382	tC2Q	RR	26	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q
4.035	1.031	tNET	RR	1	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/I1
4.532	0.498	tINS	RR	6	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/F
5.851	1.319	tNET	RR	1	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/S0
6.104	0.252	tINS	RF	635	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/O
8.475	2.371	tNET	FF	1	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/I2
8.936	0.461	tINS	FR	2	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/F
10.352	1.416	tNET	RR	1	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/I1
10.869	0.516	tINS	RR	2	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/F
11.624	0.755	tNET	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/I0
12.085	0.461	tINS	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/F
12.243	0.157	tNET	RR	1	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/I3
12.508	0.265	tINS	RR	4	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/F
14.749	2.241	tNET	RR	2	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/I0
15.305	0.556	tINS	RF	1	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/COUT
15.305	0.000	tNET	FF	2	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/CIN
15.355	0.050	tINS	FR	1	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/COUT
15.355	0.000	tNET	RR	2	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/CIN
15.651	0.296	tINS	RR	1	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/SUM
16.926	1.275	tNET	RR	2	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/I0
17.489	0.563	tINS	RF	1	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/COUT
17.489	0.000	tNET	FF	2	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/CIN
17.539	0.050	tINS	FR	1	R29C34[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21589_s0/COUT
17.539	0.000	tNET	RR	2	R29C34[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21588_s0/CIN
17.589	0.050	tINS	RR	1	R29C34[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21588_s0/COUT
17.589	0.000	tNET	RR	2	R29C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21587_s0/CIN
17.832	0.244	tINS	RR	1	R29C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21587_s0/SUM
18.376	0.544	tNET	RR	1	R27C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_8_s9/I1
18.791	0.415	tINS	RR	1	R27C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_8_s9/F
18.791	0.000	tNET	RR	1	R27C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_8_s7/I1
18.927	0.136	tINS	RR	1	R27C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_8_s7/O
22.112	3.185	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/CLKB
22.696	0.072	tSu		1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%
Arrival Data Path Delay	cell: 4.814, 24.697%; route: 14.295, 73.341%; tC2Q: 0.382, 1.962%
Required Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%

Path5

Path Summary:

Slack	0.619
Data Arrival Time	21.698
Data Required Time	22.317
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.595	4.463	tNET	RR	1	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/I2
17.093	0.498	tINS	RR	34	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/F
21.698	4.605	tNET	RR	1	R8C42[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.628	1.946	tNET	RR	1	R8C42[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_1_s1/CLK
22.317	-0.311	tSu		1	R8C42[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_1_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 13.873%; route: 14.426, 75.594%; tC2Q: 2.010, 10.533%
Required Clock Path Delay	cell: 0.683, 25.966%; route: 1.946, 74.034%

Path6

Path Summary:

Slack	0.619
Data Arrival Time	21.698
Data Required Time	22.317
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.595	4.463	tNET	RR	1	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/I2
17.093	0.498	tINS	RR	34	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/F
21.698	4.605	tNET	RR	1	R8C42[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.628	1.946	tNET	RR	1	R8C42[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_3_s1/CLK
22.317	-0.311	tSu		1	R8C42[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_3_s1

Path Statistics:

Clock Skew	0.014
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 13.873%; route: 14.426, 75.594%; tC2Q: 2.010, 10.533%
Required Clock Path Delay	cell: 0.683, 25.966%; route: 1.946, 74.034%

Path7

Path Summary:

Slack	0.643
Data Arrival Time	21.658
Data Required Time	22.301
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_4_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
15.834	3.701	tNET	RR	1	R11C19[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[9]_8_s3/I3
16.099	0.265	tINS	RR	34	R11C19[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[9]_8_s3/F
21.658	5.559	tNET	RR	1	R35C48[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R35C48[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_4_s1/CLK
22.301	-0.311	tSu		1	R35C48[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_4_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.415, 12.681%; route: 14.619, 76.764%; tC2Q: 2.010, 10.555%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path8

Path Summary:

Slack	0.643
Data Arrival Time	21.658
Data Required Time	22.301
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
15.834	3.701	tNET	RR	1	R11C19[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[9]_8_s3/I3
16.099	0.265	tINS	RR	34	R11C19[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[9]_8_s3/F
21.658	5.559	tNET	RR	1	R35C48[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R35C48[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_5_s1/CLK
22.301	-0.311	tSu		1	R35C48[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_max_code_q[9]_5_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.415, 12.681%; route: 14.619, 76.764%; tC2Q: 2.010, 10.555%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path9

Path Summary:

Slack	0.763
Data Arrival Time	21.781
Data Required Time	22.543
From	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/rd_ptr_q1_0_s3
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.607	1.924	tNET	RR	1	R29C32[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/rd_ptr_q1_0_s3/CLK
2.974	0.368	tC2Q	RF	34	R29C32[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/rd_ptr_q1_0_s3/Q
4.887	1.913	tNET	FF	1	R33C23[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_11_s4/I2
5.413	0.526	tINS	FR	2	R33C23[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_11_s4/F
5.573	0.160	tNET	RR	1	R34C23[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n4_s4/I1
6.034	0.461	tINS	RR	2	R34C23[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n4_s4/F
6.872	0.838	tNET	RR	1	R32C19[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n4_s3/I1
7.393	0.521	tINS	RR	2	R32C19[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n4_s3/F
7.553	0.160	tNET	RR	1	R32C18[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_12_s1/I1
8.014	0.461	tINS	RR	8	R32C18[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_12_s1/F
9.326	1.311	tNET	RR	1	R24C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_12_s/I1
9.591	0.265	tINS	RR	76	R24C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_12_s/F
14.584	4.994	tNET	RR	1	R18C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s138/I1
14.999	0.415	tINS	RR	1	R18C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s138/F
15.002	0.003	tNET	RR	1	R18C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s87/I0
15.417	0.415	tINS	RR	1	R18C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s87/F
15.574	0.157	tNET	RR	1	R18C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s45/I2
16.036	0.461	tINS	RR	1	R18C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s45/F
16.038	0.003	tNET	RR	1	R18C35[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s16/I0
16.559	0.521	tINS	RR	3	R18C35[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s16/F
18.109	1.550	tNET	RR	1	R26C20[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21035_s23/I3
18.626	0.516	tINS	RR	2	R26C20[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21035_s23/F
19.856	1.230	tNET	RR	1	R26C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21034_s2/I0
20.317	0.461	tINS	RR	2	R26C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21034_s2/F
21.781	1.464	tNET	RR	1	R29C32[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.607	1.924	tNET	RR	1	R29C32[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_3_s0/CLK
22.543	-0.064	tSu		1	R29C32[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	12
Arrival Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%
Arrival Data Path Delay	cell: 5.025, 26.208%; route: 13.781, 71.876%; tC2Q: 0.368, 1.917%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path10

Path Summary:

Slack	0.773
Data Arrival Time	21.922
Data Required Time	22.696
From	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.621	1.939	tNET	RR	1	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/CLK
3.004	0.382	tC2Q	RR	26	R27C36[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/id0/block_type_q_1_s1/Q
4.035	1.031	tNET	RR	1	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/I1
4.532	0.498	tINS	RR	6	R30C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/mcu0/n591_s6/F
5.851	1.319	tNET	RR	1	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/S0
6.104	0.252	tINS	RF	635	R30C14[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_width_r_0_s5/O
8.475	2.371	tNET	FF	1	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/I2
8.936	0.461	tINS	FR	2	R26C30[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21226_s2/F
10.352	1.416	tNET	RR	1	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/I1
10.869	0.516	tINS	RR	2	R29C19[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21224_s2/F
11.624	0.755	tNET	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/I0
12.085	0.461	tINS	RR	1	R34C20[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s1/F
12.243	0.157	tNET	RR	1	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/I3
12.508	0.265	tINS	RR	4	R33C20[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21228_s/F
14.749	2.241	tNET	RR	2	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/I0
15.305	0.556	tINS	RF	1	R29C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21592_s/COUT
15.305	0.000	tNET	FF	2	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/CIN
15.355	0.050	tINS	FR	1	R29C35[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21591_s/COUT
15.355	0.000	tNET	RR	2	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/CIN
15.651	0.296	tINS	RR	1	R29C35[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s/SUM
16.926	1.275	tNET	RR	2	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/I0
17.656	0.730	tINS	RR	1	R29C33[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21590_s0/SUM
18.335	0.679	tNET	RR	1	R27C33[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_5_s9/I1
18.832	0.498	tINS	RR	1	R27C33[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_5_s9/F
18.832	0.000	tNET	RR	1	R27C33[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_5_s7/I1
18.969	0.136	tINS	RR	1	R27C33[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_addr_r_5_s7/O
21.922	2.954	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/ADB[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s/CLKB
22.696	0.072	tSu		1	BSRAM_R28[25]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_ram_0_0_s

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	11
Arrival Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%
Arrival Data Path Delay	cell: 4.720, 24.454%; route: 14.199, 73.564%; tC2Q: 0.382, 1.982%
Required Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%

Path11

Path Summary:

Slack	0.802
Data Arrival Time	21.508
Data Required Time	22.310
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.595	4.463	tNET	RR	1	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/I2
17.093	0.498	tINS	RR	34	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/F
21.508	4.415	tNET	RR	1	R9C42[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.621	1.939	tNET	RR	1	R9C42[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_5_s1/CLK
22.310	-0.311	tSu		1	R9C42[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_5_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 14.013%; route: 14.236, 75.349%; tC2Q: 2.010, 10.638%
Required Clock Path Delay	cell: 0.683, 26.037%; route: 1.939, 73.963%

Path12

Path Summary:

Slack	0.830
Data Arrival Time	21.502
Data Required Time	22.332
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_ptr_q[8]_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
15.617	3.484	tNET	RR	1	R12C21[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[8]_8_s3/I3
16.114	0.498	tINS	RR	34	R12C21[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[8]_8_s3/F
21.502	5.388	tNET	RR	1	R4C54[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_ptr_q[8]_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.643	1.961	tNET	RR	1	R4C54[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_ptr_q[8]_1_s1/CLK
22.332	-0.311	tSu		1	R4C54[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_ptr_q[8]_1_s1

Path Statistics:

Clock Skew	0.029
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 14.017%; route: 14.230, 75.341%; tC2Q: 2.010, 10.642%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path13

Path Summary:

Slack	0.871
Data Arrival Time	21.679
Data Required Time	22.550
From	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_12_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.610	1.928	tNET	RR	1	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/CLK
2.993	0.382	tC2Q	RR	7	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q
4.190	1.197	tNET	RR	2	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/I1
4.682	0.493	tINS	RR	1	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/COUT
4.682	0.000	tNET	RR	2	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/CIN
4.733	0.050	tINS	RR	1	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/COUT
4.733	0.000	tNET	RR	2	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/CIN
4.783	0.050	tINS	RR	1	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/COUT
4.783	0.000	tNET	RR	2	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/CIN
4.833	0.050	tINS	RR	1	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/COUT
4.833	0.000	tNET	RR	2	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/CIN
4.883	0.050	tINS	RR	1	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/COUT
4.883	0.000	tNET	RR	2	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/CIN
4.933	0.050	tINS	RR	1	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/COUT
4.933	0.000	tNET	RR	2	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/CIN
4.983	0.050	tINS	RR	1	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/COUT
4.983	0.000	tNET	RR	2	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/CIN
5.279	0.296	tINS	RR	1	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/SUM
5.416	0.137	tNET	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/I3
5.914	0.498	tINS	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/F
6.071	0.157	tNET	RR	1	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/I2
6.361	0.290	tINS	RF	29	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/F
11.416	5.055	tNET	FF	1	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/I3
11.831	0.415	tINS	FR	9	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/F
15.918	4.086	tNET	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/I1
16.379	0.461	tINS	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/F
16.536	0.157	tNET	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/I3
17.063	0.526	tINS	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/F
17.733	0.670	tNET	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/I3
18.230	0.498	tINS	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/F
18.698	0.468	tNET	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/I3
18.960	0.262	tINS	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/F
18.963	0.003	tNET	RR	1	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/I1
19.479	0.516	tINS	RR	26	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/F
21.153	1.674	tNET	RR	1	R36C42[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n434_s4/I1
21.679	0.526	tINS	RR	1	R36C42[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n434_s4/F
21.679	0.000	tNET	RR	1	R36C42[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.614	1.931	tNET	RR	1	R36C42[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_12_s1/CLK
22.550	-0.064	tSu		1	R36C42[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_12_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%
Arrival Data Path Delay	cell: 5.081, 26.647%; route: 13.605, 71.347%; tC2Q: 0.382, 2.006%
Required Clock Path Delay	cell: 0.683, 26.112%; route: 1.931, 73.888%

Path14

Path Summary:

Slack	0.891
Data Arrival Time	21.404
Data Required Time	22.296
From	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.601	1.918	tNET	RR	1	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/CLK
2.983	0.382	tC2Q	RR	14	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q
4.934	1.951	tNET	RR	1	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/I0
5.432	0.498	tINS	RR	5	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/F
6.521	1.089	tNET	RR	1	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/I3
6.936	0.415	tINS	RR	4	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/F
7.458	0.522	tNET	RR	1	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/I3
7.974	0.516	tINS	RR	4	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/F
7.982	0.008	tNET	RR	1	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/I1
8.503	0.521	tINS	RR	6	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/F
8.886	0.382	tNET	RR	1	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/I0
9.301	0.415	tINS	RR	33	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/F
9.493	0.193	tNET	RR	1	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/I1
9.756	0.262	tINS	RR	34	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/F
11.714	1.959	tNET	RR	1	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/I3
11.979	0.265	tINS	RR	16	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/F
14.567	2.587	tNET	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/I3
14.982	0.415	tINS	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/F
15.139	0.157	tNET	RR	1	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/I0
15.554	0.415	tINS	RR	34	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/F
21.404	5.850	tNET	RR	1	R29C4[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.607	1.924	tNET	RR	1	R29C4[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_0_s1/CLK
22.296	-0.311	tSu		1	R29C4[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_0_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	20.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%
Arrival Data Path Delay	cell: 3.722, 19.797%; route: 14.699, 78.169%; tC2Q: 0.382, 2.034%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path15

Path Summary:

Slack	0.891
Data Arrival Time	21.404
Data Required Time	22.296
From	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_1_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.601	1.918	tNET	RR	1	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/CLK
2.983	0.382	tC2Q	RR	14	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q
4.934	1.951	tNET	RR	1	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/I0
5.432	0.498	tINS	RR	5	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/F
6.521	1.089	tNET	RR	1	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/I3
6.936	0.415	tINS	RR	4	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/F
7.458	0.522	tNET	RR	1	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/I3
7.974	0.516	tINS	RR	4	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/F
7.982	0.008	tNET	RR	1	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/I1
8.503	0.521	tINS	RR	6	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/F
8.886	0.382	tNET	RR	1	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/I0
9.301	0.415	tINS	RR	33	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/F
9.493	0.193	tNET	RR	1	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/I1
9.756	0.262	tINS	RR	34	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/F
11.714	1.959	tNET	RR	1	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/I3
11.979	0.265	tINS	RR	16	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/F
14.567	2.587	tNET	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/I3
14.982	0.415	tINS	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/F
15.139	0.157	tNET	RR	1	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/I0
15.554	0.415	tINS	RR	34	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/F
21.404	5.850	tNET	RR	1	R29C4[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.607	1.924	tNET	RR	1	R29C4[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_1_s1/CLK
22.296	-0.311	tSu		1	R29C4[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_1_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	20.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%
Arrival Data Path Delay	cell: 3.722, 19.797%; route: 14.699, 78.169%; tC2Q: 0.382, 2.034%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path16

Path Summary:

Slack	0.891
Data Arrival Time	21.404
Data Required Time	22.296
From	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.601	1.918	tNET	RR	1	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/CLK
2.983	0.382	tC2Q	RR	14	R16C55[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_0_s1/Q
4.934	1.951	tNET	RR	1	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/I0
5.432	0.498	tINS	RR	5	R12C34[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n131_s2/F
6.521	1.089	tNET	RR	1	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/I3
6.936	0.415	tINS	RR	4	R9C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n43_s4/F
7.458	0.522	tNET	RR	1	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/I3
7.974	0.516	tINS	RR	4	R5C36[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n92_s2/F
7.982	0.008	tNET	RR	1	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/I1
8.503	0.521	tINS	RR	6	R5C36[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s4/F
8.886	0.382	tNET	RR	1	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/I0
9.301	0.415	tINS	RR	33	R6C38[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/idx_q_10_s3/F
9.493	0.193	tNET	RR	1	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/I1
9.756	0.262	tINS	RR	34	R6C37[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_min_code_q[0]_8_s4/F
11.714	1.959	tNET	RR	1	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/I3
11.979	0.265	tINS	RR	16	R11C23[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[0]_8_s5/F
14.567	2.587	tNET	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/I3
14.982	0.415	tINS	RR	1	R9C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s4/F
15.139	0.157	tNET	RR	1	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/I0
15.554	0.415	tINS	RR	34	R8C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_min_code_q[5]_8_s5/F
21.404	5.850	tNET	RR	1	R29C4[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.607	1.924	tNET	RR	1	R29C4[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_2_s1/CLK
22.296	-0.311	tSu		1	R29C4[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_max_code_q[5]_2_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	20.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%
Arrival Data Path Delay	cell: 3.722, 19.797%; route: 14.699, 78.169%; tC2Q: 0.382, 2.034%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path17

Path Summary:

Slack	0.900
Data Arrival Time	21.650
Data Required Time	22.550
From	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_6_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.610	1.928	tNET	RR	1	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/CLK
2.993	0.382	tC2Q	RR	7	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q
4.190	1.197	tNET	RR	2	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/I1
4.682	0.493	tINS	RR	1	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/COUT
4.682	0.000	tNET	RR	2	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/CIN
4.733	0.050	tINS	RR	1	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/COUT
4.733	0.000	tNET	RR	2	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/CIN
4.783	0.050	tINS	RR	1	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/COUT
4.783	0.000	tNET	RR	2	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/CIN
4.833	0.050	tINS	RR	1	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/COUT
4.833	0.000	tNET	RR	2	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/CIN
4.883	0.050	tINS	RR	1	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/COUT
4.883	0.000	tNET	RR	2	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/CIN
4.933	0.050	tINS	RR	1	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/COUT
4.933	0.000	tNET	RR	2	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/CIN
4.983	0.050	tINS	RR	1	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/COUT
4.983	0.000	tNET	RR	2	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/CIN
5.279	0.296	tINS	RR	1	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/SUM
5.416	0.137	tNET	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/I3
5.914	0.498	tINS	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/F
6.071	0.157	tNET	RR	1	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/I2
6.361	0.290	tINS	RF	29	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/F
11.416	5.055	tNET	FF	1	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/I3
11.831	0.415	tINS	FR	9	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/F
15.918	4.086	tNET	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/I1
16.379	0.461	tINS	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/F
16.536	0.157	tNET	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/I3
17.063	0.526	tINS	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/F
17.733	0.670	tNET	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/I3
18.230	0.498	tINS	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/F
18.698	0.468	tNET	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/I3
18.960	0.262	tINS	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/F
18.963	0.003	tNET	RR	1	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/I1
19.479	0.516	tINS	RR	26	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/F
21.153	1.674	tNET	RR	1	R36C42[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n440_s4/I1
21.650	0.498	tINS	RR	1	R36C42[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n440_s4/F
21.650	0.000	tNET	RR	1	R36C42[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.614	1.931	tNET	RR	1	R36C42[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_6_s1/CLK
22.550	-0.064	tSu		1	R36C42[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_6_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%
Arrival Data Path Delay	cell: 5.052, 26.536%; route: 13.605, 71.455%; tC2Q: 0.382, 2.009%
Required Clock Path Delay	cell: 0.683, 26.112%; route: 1.931, 73.888%

Path18

Path Summary:

Slack	0.977
Data Arrival Time	21.564
Data Required Time	22.541
From	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_5_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.610	1.928	tNET	RR	1	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/CLK
2.993	0.382	tC2Q	RR	7	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q
4.190	1.197	tNET	RR	2	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/I1
4.682	0.493	tINS	RR	1	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/COUT
4.682	0.000	tNET	RR	2	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/CIN
4.733	0.050	tINS	RR	1	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/COUT
4.733	0.000	tNET	RR	2	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/CIN
4.783	0.050	tINS	RR	1	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/COUT
4.783	0.000	tNET	RR	2	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/CIN
4.833	0.050	tINS	RR	1	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/COUT
4.833	0.000	tNET	RR	2	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/CIN
4.883	0.050	tINS	RR	1	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/COUT
4.883	0.000	tNET	RR	2	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/CIN
4.933	0.050	tINS	RR	1	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/COUT
4.933	0.000	tNET	RR	2	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/CIN
4.983	0.050	tINS	RR	1	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/COUT
4.983	0.000	tNET	RR	2	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/CIN
5.279	0.296	tINS	RR	1	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/SUM
5.416	0.137	tNET	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/I3
5.914	0.498	tINS	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/F
6.071	0.157	tNET	RR	1	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/I2
6.361	0.290	tINS	RF	29	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/F
11.416	5.055	tNET	FF	1	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/I3
11.831	0.415	tINS	FR	9	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/F
15.918	4.086	tNET	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/I1
16.379	0.461	tINS	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/F
16.536	0.157	tNET	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/I3
17.063	0.526	tINS	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/F
17.733	0.670	tNET	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/I3
18.230	0.498	tINS	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/F
18.698	0.468	tNET	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/I3
18.960	0.262	tINS	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/F
18.963	0.003	tNET	RR	1	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/I1
19.479	0.516	tINS	RR	26	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/F
21.038	1.559	tNET	RR	1	R36C43[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n441_s4/I1
21.564	0.526	tINS	RR	1	R36C43[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n441_s4/F
21.564	0.000	tNET	RR	1	R36C43[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.604	1.922	tNET	RR	1	R36C43[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_5_s1/CLK
22.541	-0.064	tSu		1	R36C43[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_5_s1

Path Statistics:

Clock Skew	-0.006
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%
Arrival Data Path Delay	cell: 5.081, 26.809%; route: 13.490, 71.173%; tC2Q: 0.382, 2.018%
Required Clock Path Delay	cell: 0.683, 26.206%; route: 1.922, 73.794%

Path19

Path Summary:

Slack	1.071
Data Arrival Time	21.462
Data Required Time	22.532
From	mem_data_1_mem_data_1_0_1_s
To	mem_data_1_mem_data_1_0_23_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/DO[0]
6.228	1.604	tNET	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/I3
6.643	0.415	tINS	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/F
7.990	1.348	tNET	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/I1
8.405	0.415	tINS	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/F
8.405	0.000	tNET	RR	1	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/I1
8.542	0.136	tINS	RR	82	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/O
9.864	1.322	tNET	RR	1	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/I0
10.279	0.415	tINS	RR	8	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/F
10.442	0.162	tNET	RR	1	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/I3
10.903	0.461	tINS	RR	7	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/F
12.405	1.502	tNET	RR	1	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/I1
12.927	0.521	tINS	RR	2	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/F
13.277	0.350	tNET	RR	1	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/I0
13.774	0.498	tINS	RR	7	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/F
15.033	1.259	tNET	RR	1	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/I2
15.448	0.415	tINS	RR	3	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/F
16.697	1.249	tNET	RR	1	R7C46[3][B]	mem_data_1_s572/I1
17.112	0.415	tINS	RR	32	R7C46[3][B]	mem_data_1_s572/F
21.462	4.350	tNET	RR	1	BSRAM_R28[17]	mem_data_1_mem_data_1_0_23_s/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	BSRAM_R28[17]	mem_data_1_mem_data_1_0_23_s/CLK
22.532	-0.091	tSu		1	BSRAM_R28[17]	mem_data_1_mem_data_1_0_23_s

Path Statistics:

Clock Skew	0.009
Setup Relationship	20.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.691, 19.585%; route: 13.146, 69.751%; tC2Q: 2.010, 10.665%
Required Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%

Path20

Path Summary:

Slack	1.072
Data Arrival Time	21.476
Data Required Time	22.548
From	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_9_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.610	1.928	tNET	RR	1	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/CLK
2.993	0.382	tC2Q	RR	7	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q
4.190	1.197	tNET	RR	2	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/I1
4.682	0.493	tINS	RR	1	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/COUT
4.682	0.000	tNET	RR	2	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/CIN
4.733	0.050	tINS	RR	1	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/COUT
4.733	0.000	tNET	RR	2	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/CIN
4.783	0.050	tINS	RR	1	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/COUT
4.783	0.000	tNET	RR	2	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/CIN
4.833	0.050	tINS	RR	1	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/COUT
4.833	0.000	tNET	RR	2	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/CIN
4.883	0.050	tINS	RR	1	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/COUT
4.883	0.000	tNET	RR	2	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/CIN
4.933	0.050	tINS	RR	1	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/COUT
4.933	0.000	tNET	RR	2	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/CIN
4.983	0.050	tINS	RR	1	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/COUT
4.983	0.000	tNET	RR	2	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/CIN
5.279	0.296	tINS	RR	1	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/SUM
5.416	0.137	tNET	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/I3
5.914	0.498	tINS	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/F
6.071	0.157	tNET	RR	1	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/I2
6.361	0.290	tINS	RF	29	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/F
11.416	5.055	tNET	FF	1	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/I3
11.831	0.415	tINS	FR	9	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/F
15.918	4.086	tNET	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/I1
16.379	0.461	tINS	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/F
16.536	0.157	tNET	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/I3
17.063	0.526	tINS	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/F
17.733	0.670	tNET	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/I3
18.230	0.498	tINS	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/F
18.698	0.468	tNET	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/I3
18.960	0.262	tINS	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/F
18.963	0.003	tNET	RR	1	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/I1
19.479	0.516	tINS	RR	26	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/F
20.960	1.481	tNET	RR	1	R35C42[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n437_s4/I1
21.476	0.516	tINS	RR	1	R35C42[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n437_s4/F
21.476	0.000	tNET	RR	1	R35C42[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R35C42[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_9_s1/CLK
22.548	-0.064	tSu		1	R35C42[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_9_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%
Arrival Data Path Delay	cell: 5.071, 26.880%; route: 13.413, 71.093%; tC2Q: 0.382, 2.027%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path21

Path Summary:

Slack	1.108
Data Arrival Time	21.188
Data Required Time	22.296
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_ptr_q[14]_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.888	4.755	tNET	RR	1	R11C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[14]_8_s3/I3
17.153	0.265	tINS	RR	34	R11C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_min_code_q[14]_8_s3/F
21.188	4.035	tNET	RR	1	R29C38[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_ptr_q[14]_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.607	1.924	tNET	RR	1	R29C38[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_ptr_q[14]_0_s1/CLK
22.296	-0.311	tSu		1	R29C38[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_ptr_q[14]_0_s1

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.415, 13.002%; route: 14.149, 76.176%; tC2Q: 2.010, 10.822%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path22

Path Summary:

Slack	1.113
Data Arrival Time	21.177
Data Required Time	22.289
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_2_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.595	4.463	tNET	RR	1	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/I2
17.093	0.498	tINS	RR	34	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/F
21.177	4.084	tNET	RR	1	R16C43[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.601	1.918	tNET	RR	1	R16C43[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_2_s1/CLK
22.289	-0.311	tSu		1	R16C43[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_2_s1

Path Statistics:

Clock Skew	-0.013
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 14.263%; route: 13.905, 74.909%; tC2Q: 2.010, 10.828%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path23

Path Summary:

Slack	1.113
Data Arrival Time	21.177
Data Required Time	22.289
From	mem_data_1_mem_data_1_0_24_s
To	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_6_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[18]	mem_data_1_mem_data_1_0_24_s/DO[0]
5.424	0.800	tNET	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/I3
5.922	0.498	tINS	RR	1	R9C48[3][B]	mem_data_1_DOL_168G[0]_s0/F
7.215	1.294	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/I0
7.737	0.521	tINS	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s6/F
7.737	0.000	tNET	RR	1	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/I0
7.873	0.136	tINS	RR	31	R11C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_0_s5/O
9.435	1.563	tNET	RR	1	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/I0
9.933	0.498	tINS	RR	55	R15C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s3/F
11.635	1.702	tNET	RR	1	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/I2
12.133	0.498	tINS	RR	68	R4C39[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/n588_s1/F
16.595	4.463	tNET	RR	1	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/I2
17.093	0.498	tINS	RR	34	R12C16[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_min_code_q[8]_8_s3/F
21.177	4.084	tNET	RR	1	R16C43[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.601	1.918	tNET	RR	1	R16C43[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_6_s1/CLK
22.289	-0.311	tSu		1	R16C43[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_ac_ptr_q[8]_6_s1

Path Statistics:

Clock Skew	-0.013
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.647, 14.263%; route: 13.905, 74.909%; tC2Q: 2.010, 10.828%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path24

Path Summary:

Slack	1.131
Data Arrival Time	21.429
Data Required Time	22.559
From	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1
To	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.610	1.928	tNET	RR	1	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/CLK
2.993	0.382	tC2Q	RR	7	R34C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/column_q_5_s1/Q
4.190	1.197	tNET	RR	2	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/I1
4.682	0.493	tINS	RR	1	R36C34[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_5_s/COUT
4.682	0.000	tNET	RR	2	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/CIN
4.733	0.050	tINS	RR	1	R36C34[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_6_s/COUT
4.733	0.000	tNET	RR	2	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/CIN
4.783	0.050	tINS	RR	1	R36C34[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_7_s/COUT
4.783	0.000	tNET	RR	2	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/CIN
4.833	0.050	tINS	RR	1	R36C34[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_8_s/COUT
4.833	0.000	tNET	RR	2	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/CIN
4.883	0.050	tINS	RR	1	R36C35[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_9_s/COUT
4.883	0.000	tNET	RR	2	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/CIN
4.933	0.050	tINS	RR	1	R36C35[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_10_s/COUT
4.933	0.000	tNET	RR	2	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/CIN
4.983	0.050	tINS	RR	1	R36C35[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_11_s/COUT
4.983	0.000	tNET	RR	2	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/CIN
5.279	0.296	tINS	RR	1	R36C35[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/coordinate_x_d_12_s/SUM
5.416	0.137	tNET	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/I3
5.914	0.498	tINS	RR	1	R36C35[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s8/F
6.071	0.157	tNET	RR	1	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/I2
6.361	0.290	tINS	RF	29	R36C34[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/width_d_13_s1/F
11.416	5.055	tNET	FF	1	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/I3
11.831	0.415	tINS	FR	9	R2C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/height_d_3_s/F
15.918	4.086	tNET	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/I1
16.379	0.461	tINS	RR	1	R36C30[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s56/F
16.536	0.157	tNET	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/I3
17.063	0.526	tINS	RR	1	R36C31[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s45/F
17.733	0.670	tNET	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/I3
18.230	0.498	tINS	RR	1	R35C37[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s22/F
18.698	0.468	tNET	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/I3
18.960	0.262	tINS	RR	1	R35C29[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s11/F
18.963	0.003	tNET	RR	1	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/I1
19.479	0.516	tINS	RR	26	R35C29[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n1610_s5/F
20.903	1.424	tNET	RR	1	R36C41[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n443_s4/I1
21.429	0.526	tINS	RR	1	R36C41[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/n443_s4/F
21.429	0.000	tNET	RR	1	R36C41[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.623	1.941	tNET	RR	1	R36C41[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_3_s1/CLK
22.559	-0.064	tSu		1	R36C41[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/line0/BlockOfACol_3_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	20.000
Logic Level	13
Arrival Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%
Arrival Data Path Delay	cell: 5.081, 27.001%; route: 13.355, 70.966%; tC2Q: 0.382, 2.033%
Required Clock Path Delay	cell: 0.683, 26.019%; route: 1.941, 73.981%

Path25

Path Summary:

Slack	1.261
Data Arrival Time	21.262
Data Required Time	22.523
From	mem_data_1_mem_data_1_0_1_s
To	mem_data_1_mem_data_1_0_21_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/CLK
4.624	2.010	tC2Q	RR	1	BSRAM_R10[4]	mem_data_1_mem_data_1_0_1_s/DO[0]
6.228	1.604	tNET	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/I3
6.643	0.415	tINS	RR	1	R11C40[3][B]	mem_data_1_DOL_7G[0]_s0/F
7.990	1.348	tNET	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/I1
8.405	0.415	tINS	RR	1	R11C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s7/F
8.405	0.000	tNET	RR	1	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/I1
8.542	0.136	tINS	RR	82	R11C46[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/data_r_1_s5/O
9.864	1.322	tNET	RR	1	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/I0
10.279	0.415	tINS	RR	8	R4C45[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n352_s36/F
10.442	0.162	tNET	RR	1	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/I3
10.903	0.461	tINS	RR	7	R4C46[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n492_s5/F
12.405	1.502	tNET	RR	1	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/I1
12.927	0.521	tINS	RR	2	R14C44[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/n551_s2/F
13.277	0.350	tNET	RR	1	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/I0
13.774	0.498	tINS	RR	7	R15C43[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/n68_s1/F
15.033	1.259	tNET	RR	1	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/I2
15.448	0.415	tINS	RR	3	R9C46[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/out_in_accept_d_s/F
16.697	1.249	tNET	RR	1	R7C46[3][B]	mem_data_1_s572/I1
17.112	0.415	tINS	RR	32	R7C46[3][B]	mem_data_1_s572/F
21.262	4.150	tNET	RR	1	BSRAM_R28[16]	mem_data_1_mem_data_1_0_21_s/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.614	1.932	tNET	RR	1	BSRAM_R28[16]	mem_data_1_mem_data_1_0_21_s/CLK
22.523	-0.091	tSu		1	BSRAM_R28[16]	mem_data_1_mem_data_1_0_21_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.691, 19.795%; route: 12.946, 69.426%; tC2Q: 2.010, 10.779%
Required Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.216
Data Arrival Time	1.630
Data Required Time	1.413
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/rd_addr_Cx_T_4_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.385	0.709	tNET	RR	1	R8C8[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/rd_addr_Cx_T_4_s0/CLK
1.529	0.144	tC2Q	RR	2	R8C8[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/rd_addr_Cx_T_4_s0/Q
1.630	0.101	tNET	RR	1	BSRAM_R10[1]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s/ADB[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[1]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s/CLKB
1.413	0.035	tHld		1	BSRAM_R10[1]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.790%; route: 0.709, 51.210%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path2

Path Summary:

Slack	0.275
Data Arrival Time	2.797
Data Required Time	2.522
From	gw_gao_inst_0/u_la0_top/address_counter_10_s0
To	gw_gao_inst_0/u_la0_top/address_counter_10_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	233	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.497	1.146	tNET	RR	1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.638	0.141	tC2Q	RF	4	R12C2[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.644	0.006	tNET	FF	1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/I2
2.797	0.153	tINS	FF	1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/F
2.797	0.000	tNET	FF	1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	233	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.497	1.146	tNET	RR	1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.522	0.025	tHld		1	R12C2[0][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 54.105%; route: 1.146, 45.895%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 54.105%; route: 1.146, 45.895%

Path3

Path Summary:

Slack	0.275
Data Arrival Time	1.607
Data Required Time	1.332
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_1_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.385	0.710	tNET	RR	1	R7C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_1_s0/CLK
1.530	0.144	tC2Q	RR	1	R7C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_1_s0/Q
1.607	0.078	tNET	RR	1	R7C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.385	0.710	tNET	RR	1	R7C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/CLK
1.332	-0.053	tHld		1	R7C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.755%; route: 0.710, 51.245%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.755%; route: 0.710, 51.245%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.607
Data Required Time	1.332
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.385	0.710	tNET	RR	1	R7C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/CLK
1.530	0.144	tC2Q	RR	1	R7C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_2_s0/Q
1.607	0.078	tNET	RR	1	R7C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.385	0.710	tNET	RR	1	R7C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_3_s0/CLK
1.332	-0.053	tHld		1	R7C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.755%; route: 0.710, 51.245%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.755%; route: 0.710, 51.245%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_8_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_8_s0/CLK
1.535	0.144	tC2Q	RR	1	R4C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_8_s0/Q
1.613	0.078	tNET	RR	1	R4C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/CLK
1.338	-0.053	tHld		1	R4C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/CLK
1.535	0.144	tC2Q	RR	1	R4C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_9_s0/Q
1.613	0.078	tNET	RR	1	R4C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_10_s0/CLK
1.338	-0.053	tHld		1	R4C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_11_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_11_s0/CLK
1.535	0.144	tC2Q	RR	1	R4C3[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_11_s0/Q
1.613	0.078	tNET	RR	1	R4C3[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.715	tNET	RR	1	R4C3[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_12_s0/CLK
1.338	-0.053	tHld		1	R4C3[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.571%; route: 0.715, 51.429%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.620
Data Required Time	1.345
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_15_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_15_s0/CLK
1.542	0.144	tC2Q	RR	1	R2C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_15_s0/Q
1.620	0.078	tNET	RR	1	R2C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_16_s0/CLK
1.345	-0.053	tHld		1	R2C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.619
Data Required Time	1.344
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_19_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R3C26[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_19_s0/CLK
1.541	0.144	tC2Q	RR	1	R3C26[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_19_s0/Q
1.619	0.078	tNET	RR	1	R3C26[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R3C26[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/CLK
1.344	-0.053	tHld		1	R3C26[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.619
Data Required Time	1.344
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R3C26[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/CLK
1.541	0.144	tC2Q	RR	1	R3C26[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_20_s0/Q
1.619	0.078	tNET	RR	1	R3C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.397	0.721	tNET	RR	1	R3C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_21_s0/CLK
1.344	-0.053	tHld		1	R3C26[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.371%; route: 0.721, 51.629%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.620
Data Required Time	1.345
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_22_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_22_s0/CLK
1.542	0.144	tC2Q	RR	1	R2C2[3][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_22_s0/Q
1.620	0.078	tNET	RR	1	R2C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/CLK
1.345	-0.053	tHld		1	R2C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.620
Data Required Time	1.345
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/CLK
1.542	0.144	tC2Q	RR	1	R2C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_23_s0/Q
1.620	0.078	tNET	RR	1	R2C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_24_s0/CLK
1.345	-0.053	tHld		1	R2C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_24_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_28_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_28_s0/CLK
1.535	0.144	tC2Q	RR	1	R6C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_28_s0/Q
1.613	0.078	tNET	RR	1	R6C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/CLK
1.338	-0.053	tHld		1	R6C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/CLK
1.535	0.144	tC2Q	RR	1	R6C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_29_s0/Q
1.613	0.078	tNET	RR	1	R6C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_30_s0/CLK
1.338	-0.053	tHld		1	R6C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_30_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_32_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_32_s0/CLK
1.535	0.144	tC2Q	RR	1	R6C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_32_s0/Q
1.613	0.078	tNET	RR	1	R6C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/CLK
1.338	-0.053	tHld		1	R6C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.613
Data Required Time	1.338
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/CLK
1.535	0.144	tC2Q	RR	1	R6C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_33_s0/Q
1.613	0.078	tNET	RR	1	R6C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_34_s0/CLK
1.338	-0.053	tHld		1	R6C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_34_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.587
Data Required Time	1.313
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_35_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_35_s0/CLK
1.510	0.144	tC2Q	RR	1	R11C3[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_35_s0/Q
1.587	0.078	tNET	RR	1	R11C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/CLK
1.313	-0.053	tHld		1	R11C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.587
Data Required Time	1.313
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/CLK
1.510	0.144	tC2Q	RR	1	R11C3[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_36_s0/Q
1.587	0.078	tNET	RR	1	R11C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_37_s0/CLK
1.313	-0.053	tHld		1	R11C3[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_37_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.587
Data Required Time	1.313
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_39_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_39_s0/CLK
1.510	0.144	tC2Q	RR	1	R11C3[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_39_s0/Q
1.587	0.078	tNET	RR	1	R11C3[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/CLK
1.313	-0.053	tHld		1	R11C3[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.587
Data Required Time	1.313
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_41_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/CLK
1.510	0.144	tC2Q	RR	1	R11C3[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_40_s0/Q
1.587	0.078	tNET	RR	1	R11C3[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C3[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_41_s0/CLK
1.313	-0.053	tHld		1	R11C3[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_41_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.591
Data Required Time	1.316
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_44_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_44_s0/CLK
1.513	0.144	tC2Q	RR	1	R11C2[1][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_44_s0/Q
1.591	0.078	tNET	RR	1	R11C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/CLK
1.316	-0.053	tHld		1	R11C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.591
Data Required Time	1.316
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_46_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/CLK
1.513	0.144	tC2Q	RR	1	R11C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_45_s0/Q
1.591	0.078	tNET	RR	1	R11C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_46_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_46_s0/CLK
1.316	-0.053	tHld		1	R11C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_46_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.587
Data Required Time	1.312
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_47_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_48_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_47_s0/CLK
1.509	0.144	tC2Q	RR	1	R13C2[0][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_47_s0/Q
1.587	0.078	tNET	RR	1	R13C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_48_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_48_s0/CLK
1.312	-0.053	tHld		1	R13C2[0][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_48_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.615
Data Required Time	1.340
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_49_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_50_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_49_s0/CLK
1.537	0.144	tC2Q	RR	1	R5C2[2][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_49_s0/Q
1.615	0.078	tNET	RR	1	R5C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_50_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_50_s0/CLK
1.340	-0.053	tHld		1	R5C2[2][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_50_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.615
Data Required Time	1.340
From	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_51_s0
To	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_52_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C2[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_51_s0/CLK
1.537	0.144	tC2Q	RR	1	R5C2[1][B]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_51_s0/Q
1.615	0.078	tNET	RR	1	R5C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_52_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_52_s0/CLK
1.340	-0.053	tHld		1	R5C2[3][A]	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/shift_reg_52_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.268
Data Arrival Time	16.013
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
16.013	2.932	tNET	FF	1	R6C31[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C31[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
22.281	-0.347	tSu		1	R6C31[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.932, 86.889%; tC2Q: 0.442, 13.111%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path2

Path Summary:

Slack	7.201
Data Arrival Time	15.100
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.100	2.019	tNET	FF	1	R2C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R2C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0/CLK
22.301	-0.347	tSu		1	R2C20[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.019, 82.021%; tC2Q: 0.442, 17.979%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path3

Path Summary:

Slack	7.201
Data Arrival Time	15.100
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.100	2.019	tNET	FF	1	R2C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R2C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0/CLK
22.301	-0.347	tSu		1	R2C20[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.019, 82.021%; tC2Q: 0.442, 17.979%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path4

Path Summary:

Slack	7.965
Data Arrival Time	14.323
Data Required Time	22.288
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.323	1.242	tNET	FF	1	R7C12[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.636	1.953	tNET	RR	1	R7C12[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
22.288	-0.347	tSu		1	R7C12[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.242, 73.739%; tC2Q: 0.442, 26.261%
Required Clock Path Delay	cell: 0.683, 25.895%; route: 1.953, 74.105%

Path5

Path Summary:

Slack	7.965
Data Arrival Time	14.323
Data Required Time	22.288
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.323	1.242	tNET	FF	1	R7C12[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.636	1.953	tNET	RR	1	R7C12[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
22.288	-0.347	tSu		1	R7C12[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.242, 73.739%; tC2Q: 0.442, 26.261%
Required Clock Path Delay	cell: 0.683, 25.895%; route: 1.953, 74.105%

Path6

Path Summary:

Slack	8.177
Data Arrival Time	14.121
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.121	1.040	tNET	FF	1	R3C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
22.298	-0.347	tSu		1	R3C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.040, 70.152%; tC2Q: 0.442, 29.848%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path7

Path Summary:

Slack	8.177
Data Arrival Time	14.121
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.121	1.040	tNET	FF	1	R3C2[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C2[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
22.298	-0.347	tSu		1	R3C2[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.040, 70.152%; tC2Q: 0.442, 29.848%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path8

Path Summary:

Slack	8.177
Data Arrival Time	14.121
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.121	1.040	tNET	FF	1	R3C2[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C2[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
22.298	-0.347	tSu		1	R3C2[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.040, 70.152%; tC2Q: 0.442, 29.848%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path9

Path Summary:

Slack	8.177
Data Arrival Time	14.121
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.121	1.040	tNET	FF	1	R3C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
22.298	-0.347	tSu		1	R3C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.040, 70.152%; tC2Q: 0.442, 29.848%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path10

Path Summary:

Slack	8.177
Data Arrival Time	14.121
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.121	1.040	tNET	FF	1	R3C2[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C2[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
22.298	-0.347	tSu		1	R3C2[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.040, 70.152%; tC2Q: 0.442, 29.848%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path11

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
22.281	-0.347	tSu		1	R6C3[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path12

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
22.281	-0.347	tSu		1	R6C3[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path13

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
22.281	-0.347	tSu		1	R6C3[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path14

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
22.281	-0.347	tSu		1	R6C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path15

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
22.281	-0.347	tSu		1	R6C3[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path16

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
22.281	-0.347	tSu		1	R6C3[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path17

Path Summary:

Slack	8.232
Data Arrival Time	14.050
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.050	0.969	tNET	FF	1	R6C3[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.629	1.946	tNET	RR	1	R6C3[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
22.281	-0.347	tSu		1	R6C3[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355%
Required Clock Path Delay	cell: 0.683, 25.963%; route: 1.946, 74.037%

Path18

Path Summary:

Slack	8.247
Data Arrival Time	14.032
Data Required Time	22.279
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.032	0.951	tNET	FF	1	R7C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.626	1.944	tNET	RR	1	R7C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
22.279	-0.347	tSu		1	R7C3[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	-0.012
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 68.251%; tC2Q: 0.442, 31.749%
Required Clock Path Delay	cell: 0.683, 25.988%; route: 1.944, 74.012%

Path19

Path Summary:

Slack	8.247
Data Arrival Time	14.032
Data Required Time	22.279
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.032	0.951	tNET	FF	1	R7C3[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.626	1.944	tNET	RR	1	R7C3[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
22.279	-0.347	tSu		1	R7C3[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 68.251%; tC2Q: 0.442, 31.749%
Required Clock Path Delay	cell: 0.683, 25.988%; route: 1.944, 74.012%

Path20

Path Summary:

Slack	8.259
Data Arrival Time	14.022
Data Required Time	22.281
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.022	0.941	tNET	FF	1	R8C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.628	1.946	tNET	RR	1	R8C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
22.281	-0.347	tSu		1	R8C2[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.941, 68.022%; tC2Q: 0.442, 31.978%
Required Clock Path Delay	cell: 0.683, 25.966%; route: 1.946, 74.034%

Path21

Path Summary:

Slack	8.543
Data Arrival Time	13.755
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.755	0.674	tNET	FF	1	R3C4[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C4[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
22.298	-0.347	tSu		1	R3C4[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.674, 60.358%; tC2Q: 0.442, 39.642%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path22

Path Summary:

Slack	8.543
Data Arrival Time	13.755
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.755	0.674	tNET	FF	1	R3C4[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R3C4[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
22.298	-0.347	tSu		1	R3C4[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.007
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.674, 60.358%; tC2Q: 0.442, 39.642%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path23

Path Summary:

Slack	8.560
Data Arrival Time	13.736
Data Required Time	22.296
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.736	0.655	tNET	FF	1	R4C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.643	1.961	tNET	RR	1	R4C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
22.296	-0.347	tSu		1	R4C2[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.005
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.655, 59.681%; tC2Q: 0.442, 40.319%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path24

Path Summary:

Slack	8.637
Data Arrival Time	13.656
Data Required Time	22.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.656	0.575	tNET	FF	1	R5C4[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.641	1.958	tNET	RR	1	R5C4[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0/CLK
22.293	-0.347	tSu		1	R5C4[3][B]	gw_gao_inst_0/u_la0_top/u_ao_match_1/match_sep_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.575, 56.511%; tC2Q: 0.442, 43.489%
Required Clock Path Delay	cell: 0.683, 25.846%; route: 1.958, 74.154%

Path25

Path Summary:

Slack	8.637
Data Arrival Time	13.656
Data Required Time	22.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	15532	IOB29[A]	clk_ibuf/O
12.638	1.951	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.081	0.442	tC2Q	FF	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.656	0.575	tNET	FF	1	R5C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	15532	IOB29[A]	clk_ibuf/O
22.641	1.958	tNET	RR	1	R5C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
22.293	-0.347	tSu		1	R5C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.057%; route: 1.951, 73.943%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.575, 56.511%; tC2Q: 0.442, 43.489%
Required Clock Path Delay	cell: 0.683, 25.846%; route: 1.958, 74.154%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.417
Data Arrival Time	11.757
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.757	0.202	tNET	RR	1	R5C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
1.340	-0.053	tHld		1	R5C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 56.111%; tC2Q: 0.158, 43.889%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path2

Path Summary:

Slack	10.417
Data Arrival Time	11.757
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.757	0.202	tNET	RR	1	R5C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.340	-0.053	tHld		1	R5C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 56.111%; tC2Q: 0.158, 43.889%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path3

Path Summary:

Slack	10.417
Data Arrival Time	11.757
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.757	0.202	tNET	RR	1	R5C8[1][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C8[1][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.340	-0.053	tHld		1	R5C8[1][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 56.111%; tC2Q: 0.158, 43.889%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path4

Path Summary:

Slack	10.417
Data Arrival Time	11.757
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.757	0.202	tNET	RR	1	R5C8[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C8[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
1.340	-0.053	tHld		1	R5C8[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 56.111%; tC2Q: 0.158, 43.889%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path5

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
1.342	-0.053	tHld		1	R4C4[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path6

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.342	-0.053	tHld		1	R4C4[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path7

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
1.342	-0.053	tHld		1	R4C4[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path8

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.342	-0.053	tHld		1	R4C4[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path9

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.342	-0.053	tHld		1	R4C4[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path10

Path Summary:

Slack	10.424
Data Arrival Time	11.766
Data Required Time	1.342
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.766	0.210	tNET	RR	1	R4C4[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R4C4[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
1.342	-0.053	tHld		1	R4C4[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.210, 57.065%; tC2Q: 0.158, 42.935%
Required Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%

Path11

Path Summary:

Slack	10.489
Data Arrival Time	11.835
Data Required Time	1.345
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.835	0.279	tNET	RR	1	R2C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.398	0.723	tNET	RR	1	R2C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.345	-0.053	tHld		1	R2C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 63.844%; tC2Q: 0.158, 36.156%
Required Clock Path Delay	cell: 0.675, 48.310%; route: 0.723, 51.690%

Path12

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.338	-0.053	tHld		1	R6C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path13

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.338	-0.053	tHld		1	R6C8[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path14

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.338	-0.053	tHld		1	R6C8[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path15

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.338	-0.053	tHld		1	R6C8[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path16

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.338	-0.053	tHld		1	R6C8[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path17

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.338	-0.053	tHld		1	R6C8[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path18

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.338	-0.053	tHld		1	R6C8[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path19

Path Summary:

Slack	10.504
Data Arrival Time	11.843
Data Required Time	1.338
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.842	0.287	tNET	RR	1	R6C8[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.391	0.716	tNET	RR	1	R6C8[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.338	-0.053	tHld		1	R6C8[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.287, 64.494%; tC2Q: 0.158, 35.506%
Required Clock Path Delay	cell: 0.675, 48.553%; route: 0.716, 51.447%

Path20

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.340	-0.053	tHld		1	R5C10[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path21

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.340	-0.053	tHld		1	R5C10[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path22

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.340	-0.053	tHld		1	R5C10[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path23

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
1.340	-0.053	tHld		1	R5C10[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path24

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.340	-0.053	tHld		1	R5C10[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Path25

Path Summary:

Slack	10.516
Data Arrival Time	11.856
Data Required Time	1.340
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	15532	IOB29[A]	clk_ibuf/O
11.398	0.720	tNET	FF	1	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.556	0.158	tC2Q	FR	59	R4C7[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.856	0.300	tNET	RR	1	R5C10[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	15532	IOB29[A]	clk_ibuf/O
1.393	0.718	tNET	RR	1	R5C10[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.340	-0.053	tHld		1	R5C10[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 48.479%; route: 0.720, 51.521%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.300, 65.502%; tC2Q: 0.158, 34.498%
Required Clock Path Delay	cell: 0.675, 48.492%; route: 0.718, 51.508%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mem_data_1_mem_data_1_0_2_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mem_data_1_mem_data_1_0_2_s/CLK

MPW2

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mem_data_1_mem_data_1_0_7_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mem_data_1_mem_data_1_0_7_s/CLK

MPW3

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_15_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mem_data_1_mem_data_1_0_15_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mem_data_1_mem_data_1_0_15_s/CLK

MPW4

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_22_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mem_data_1_mem_data_1_0_22_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mem_data_1_mem_data_1_0_22_s/CLK

MPW5

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cb_ram_inst/ram_ram_0_0_s/CLKB

MPW6

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cr_ram_inst/ram_ram_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cr_ram_inst/ram_ram_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mjpeg_decoder_top/MJPEG_Decoder_inst/sub/cr_ram_inst/ram_ram_0_0_s/CLKA

MPW7

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mem_data_1_mem_data_1_0_14_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mem_data_1_mem_data_1_0_14_s/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mem_data_1_mem_data_1_0_14_s/CLK

MPW8

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/Y0/AllinOne/ram_ram_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/Y0/AllinOne/ram_ram_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mjpeg_decoder_top/MJPEG_Decoder_inst/bufferDHT0/Y0/AllinOne/ram_ram_0_2_s/CLKA

MPW9

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s/CLKB

MPW10

MPW Summary:

Slack:	7.751
Actual Width:	8.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
12.627	1.940	tNET	FF	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s0/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
21.378	0.703	tNET	RR	mjpeg_decoder_top/MJPEG_Decoder_inst/dqt_YUV0/table_dqt_q_table_dqt_q_0_0_s0/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
15532	clk_d	0.061	1.985
706	rd_ptr[5]	12.455	3.824
706	rd_ptr[5]	13.548	2.949
706	rd_ptr[5]	11.981	4.179
635	lookup_width_r[0]	0.061	4.468
354	rd_ptr[4]	11.666	4.000
354	rd_ptr[4]	14.393	2.757
354	rd_ptr[4]	14.380	2.463
345	lookup_width_r[1]	1.796	3.561
233	control0[0]	41.075	3.004

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R32C19	93.06%
R17C12	88.89%
R32C13	87.50%
R23C12	86.11%
R16C19	86.11%
R23C20	84.72%
R33C30	84.72%
R29C21	84.72%
R30C23	84.72%
R22C25	83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk}] -group [get_clocks {tck_pad_i}]