Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\src\mjpeg_decoder\mjpeg_decoder.v
E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\src\top.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.10\MJPEG_Decoder_RefDesign\proj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Thu Jun 20 13:57:52 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 445.137MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 445.137MB
    Optimizing Phase 1: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.597s, Peak memory usage = 445.137MB
    Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 445.137MB
Running inference:
    Inferring Phase 0: CPU time = 0h 1m 8s, Elapsed time = 0h 3m 49s, Peak memory usage = 494.707MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 494.707MB
    Inferring Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 494.707MB
    Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 494.707MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 494.707MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 494.707MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.191s, Peak memory usage = 494.707MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 494.707MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.554s, Peak memory usage = 494.707MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 633.324MB
Total Time and Memory Usage CPU time = 0h 1m 19s, Elapsed time = 0h 4m 0.813s, Peak memory usage = 633.324MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 32
I/O Buf 31
    IBUF 5
    OBUF 26
Register 15688
    DFFSE 4
    DFFRE 9564
    DFFPE 71
    DFFCE 6049
LUT 7763
    LUT2 404
    LUT3 4211
    LUT4 3148
MUX 1
    MUX16 1
ALU 6254
    ALU 6254
INV 64
    INV 64
DSP
    MULTALU27X18 3
BSRAM 53
    SDPB 15
    SDPX9B 6
    pROM 32
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 14089(7835 LUT, 6254 ALU) / 23040 62%
Register 15688 / 23685 67%
  --Register as Latch 0 / 23685 0%
  --Register as FF 15688 / 23685 67%
BSRAM 53 / 56 95%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 80.923(MHz) 14 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -2.357
Data Arrival Time 12.669
Data Required Time 10.311
From mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0
To mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 15532 clk_ibuf/O
0.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/CLK
0.757 0.382 tC2Q RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/Q
1.132 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/I0
1.659 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/F
2.034 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/I1
2.550 0.516 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/F
2.925 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/I0
3.451 0.526 tINS RR 6 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/F
3.826 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/I0
4.352 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/F
4.727 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/I2
5.189 0.461 tINS RR 31 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/F
5.564 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/I1
6.080 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/F
6.455 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/I1
6.971 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/F
7.346 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/I0
7.872 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/F
8.247 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/I0
8.774 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/F
9.149 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/I2
9.610 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/F
9.985 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/I0
10.511 0.526 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/F
10.886 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20964_s3/I1
11.402 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20964_s3/F
11.777 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20964_s1/I1
12.294 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20964_s1/F
12.669 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 15532 clk_ibuf/O
10.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_2_s0/CLK
10.311 -0.064 tSu 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 6.661, 54.184%; route: 5.250, 42.705%; tC2Q: 0.382, 3.111%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack -2.257
Data Arrival Time 12.569
Data Required Time 10.311
From mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_5_s0
To mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 15532 clk_ibuf/O
0.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_5_s0/CLK
0.757 0.382 tC2Q RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_5_s0/Q
1.132 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_21_s3/I0
1.659 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_21_s3/F
2.034 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n10_s4/I1
2.550 0.516 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n10_s4/F
2.925 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n11_s3/I0
3.451 0.526 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n11_s3/F
3.826 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_9_s0/I0
4.352 0.526 tINS RR 5 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_9_s0/F
4.727 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_9_s/I2
5.189 0.461 tINS RR 58 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_9_s/F
5.564 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s21/I1
6.080 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s21/F
6.455 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s19/I2
6.916 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s19/F
7.291 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s12/I2
7.752 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s12/F
8.127 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s10/I0
8.654 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s10/F
9.029 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s6/I0
9.555 0.526 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21036_s6/F
9.930 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s13/I0
10.456 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s13/F
10.831 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s4/I0
11.357 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s4/F
11.732 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s1/I2
12.194 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21037_s1/F
12.569 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 15532 clk_ibuf/O
10.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_0_s0/CLK
10.311 -0.064 tSu 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_ac_width_r_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 6.561, 53.808%; route: 5.250, 43.055%; tC2Q: 0.382, 3.137%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack -2.114
Data Arrival Time 12.425
Data Required Time 10.311
From mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_6_s0
To mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_width_r_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 15532 clk_ibuf/O
0.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_6_s0/CLK
0.757 0.382 tC2Q RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_6_s0/Q
1.132 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_22_s3/I0
1.659 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_22_s3/F
2.034 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n9_s4/I1
2.550 0.516 tINS RR 4 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n9_s4/F
2.925 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n10_s3/I0
3.451 0.526 tINS RR 4 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n10_s3/F
3.826 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_6_s1/I0
4.352 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_6_s1/F
4.727 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_6_s/I2
5.189 0.461 tINS RR 38 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_6_s/F
5.564 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s172/I1
6.080 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s172/F
6.455 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s132/I1
6.971 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s132/F
7.346 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s70/I3
7.609 0.262 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s70/F
7.984 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s25/I0
8.510 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s25/F
8.885 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s8/I0
9.411 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21108_s8/F
9.786 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21106_s2/I0
10.313 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21106_s2/F
10.688 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21107_s2/I2
11.149 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21107_s2/F
11.524 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21107_s1/I0
12.050 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n21107_s1/F
12.425 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_width_r_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 15532 clk_ibuf/O
10.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_width_r_1_s0/CLK
10.311 -0.064 tSu 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/cx_dc_width_r_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 6.418, 53.258%; route: 5.250, 43.568%; tC2Q: 0.382, 3.174%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack -2.114
Data Arrival Time 12.425
Data Required Time 10.311
From mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0
To mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 15532 clk_ibuf/O
0.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/CLK
0.757 0.382 tC2Q RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/Q
1.132 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/I0
1.659 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/F
2.034 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/I1
2.550 0.516 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/F
2.925 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/I0
3.451 0.526 tINS RR 6 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/F
3.826 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/I0
4.352 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/F
4.727 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/I2
5.189 0.461 tINS RR 31 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/F
5.564 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/I1
6.080 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/F
6.455 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/I1
6.971 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/F
7.346 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/I0
7.872 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/F
8.247 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/I0
8.774 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/F
9.149 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/I2
9.610 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/F
9.985 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/I0
10.511 0.526 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/F
10.886 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s2/I3
11.149 0.262 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s2/F
11.524 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s1/I0
12.050 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s1/F
12.425 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 15532 clk_ibuf/O
10.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_0_s0/CLK
10.311 -0.064 tSu 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 6.417, 53.258%; route: 5.250, 43.568%; tC2Q: 0.382, 3.174%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack -2.114
Data Arrival Time 12.425
Data Required Time 10.311
From mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0
To mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 15532 clk_ibuf/O
0.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/CLK
0.757 0.382 tC2Q RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/ram_q[1]_3_s0/Q
1.132 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/I0
1.659 0.526 tINS RR 2 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/data_19_s3/F
2.034 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/I1
2.550 0.516 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n12_s4/F
2.925 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/I0
3.451 0.526 tINS RR 6 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n13_s3/F
3.826 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/I0
4.352 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s0/F
4.727 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/I2
5.189 0.461 tINS RR 31 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/lookup_input_5_s/F
5.564 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/I1
6.080 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s171/F
6.455 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/I1
6.971 0.516 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s157/F
7.346 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/I0
7.872 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s122/F
8.247 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/I0
8.774 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s74/F
9.149 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/I2
9.610 0.461 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s31/F
9.985 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/I0
10.511 0.526 tINS RR 3 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20966_s9/F
10.886 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20965_s2/I3
11.149 0.262 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20965_s2/F
11.524 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20965_s1/I0
12.050 0.526 tINS RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/n20965_s1/F
12.425 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 15532 clk_ibuf/O
10.375 0.375 tNET RR 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_1_s0/CLK
10.311 -0.064 tSu 1 mjpeg_decoder_top/MJPEG_Decoder_inst/dht0/y_dc_width_r_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 14
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 6.417, 53.258%; route: 5.250, 43.568%; tC2Q: 0.382, 3.174%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%