Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v C:\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Mar 4 10:45:54 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.351s, Peak memory usage = 116.391MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 116.391MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 116.391MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 116.391MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 116.391MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 116.391MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 116.391MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 116.391MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 116.391MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 116.391MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 116.391MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 116.391MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 141.234MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.158s, Peak memory usage = 141.234MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.139s, Peak memory usage = 141.234MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 141.234MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 96 |
| I/O Buf | 96 |
| IBUF | 36 |
| OBUF | 60 |
| Register | 1439 |
| DFFRE | 840 |
| DFFPE | 9 |
| DFFCE | 590 |
| LUT | 942 |
| LUT2 | 59 |
| LUT3 | 587 |
| LUT4 | 296 |
| ALU | 40 |
| ALU | 40 |
| INV | 11 |
| INV | 11 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 993(953 LUT, 40 ALU) / 138240 | <1% |
| Register | 1439 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1439 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.000(MHz) | 145.666(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.135 |
| Data Arrival Time | 7.214 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_24_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n193_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s47/I0 |
| 3.839 | 0.579 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s47/F |
| 4.251 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s43/I0 |
| 4.830 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s43/F |
| 5.243 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s41/I0 |
| 5.821 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s41/F |
| 6.234 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/I1 |
| 6.801 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s39/F |
| 7.214 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.119, 45.856%; route: 3.300, 48.520%; tC2Q: 0.382, 5.624% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.135 |
| Data Arrival Time | 7.214 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I1 |
| 3.828 | 0.567 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.240 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/I0 |
| 4.819 | 0.579 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/F |
| 5.231 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s52/I0 |
| 5.810 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s52/F |
| 6.223 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/I0 |
| 6.801 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/F |
| 7.214 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.119, 45.856%; route: 3.300, 48.520%; tC2Q: 0.382, 5.624% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.146 |
| Data Arrival Time | 7.202 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I1 |
| 3.828 | 0.567 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.240 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s44/I1 |
| 4.808 | 0.567 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s44/F |
| 5.220 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s47/I0 |
| 5.799 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s47/F |
| 6.211 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I0 |
| 6.790 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F |
| 7.203 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.108, 45.766%; route: 3.300, 48.601%; tC2Q: 0.382, 5.633% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.146 |
| Data Arrival Time | 7.202 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I1 |
| 3.828 | 0.567 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.240 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s45/I1 |
| 4.808 | 0.567 | tINS | RR | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s45/F |
| 5.220 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/I0 |
| 5.799 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/F |
| 6.211 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s50/I0 |
| 6.790 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s50/F |
| 7.203 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.108, 45.766%; route: 3.300, 48.601%; tC2Q: 0.382, 5.633% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.157 |
| Data Arrival Time | 7.191 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_25_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n194_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I1 |
| 3.828 | 0.567 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.240 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s45/I1 |
| 4.808 | 0.567 | tINS | RR | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s45/F |
| 5.220 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s60/I0 |
| 5.799 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s60/F |
| 6.211 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s58/I1 |
| 6.779 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n739_s58/F |
| 7.191 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1439 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_5_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.096, 45.676%; route: 3.300, 48.681%; tC2Q: 0.382, 5.643% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |