Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK8B10B\data\RoraLink_8B10B_Top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK8B10B\data\RoraLink_8B10B_Core_encryption.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:27:35 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RoraLink_8B10B_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.906s, Peak memory usage = 116.746MB Running netlist conversion: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 116.746MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 116.746MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 116.746MB Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 116.746MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 116.746MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 116.746MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 116.746MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 116.746MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.162s, Peak memory usage = 116.746MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 116.746MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 116.746MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 121.324MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 121.324MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 121.324MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 121.324MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 300 |
| I/O Buf | 240 |
| IBUF | 96 |
| OBUF | 144 |
| Register | 1780 |
| DFFSE | 213 |
| DFFRE | 835 |
| DFFCE | 732 |
| LUT | 1622 |
| LUT2 | 175 |
| LUT3 | 473 |
| LUT4 | 974 |
| ALU | 79 |
| ALU | 79 |
| INV | 74 |
| INV | 74 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1775(1696 LUT, 79 ALU) / 138240 | 2% |
| Register | 1780 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1780 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | user_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | user_clk_i_ibuf/I | ||
| 2 | init_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | init_clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | user_clk_i | 100.000(MHz) | 183.655(MHz) | 7 | TOP |
| 2 | init_clk_i | 100.000(MHz) | 179.019(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.414 |
| Data Arrival Time | 5.667 |
| Data Required Time | 10.081 |
| From | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0 |
| To | u_RoraLink_8B10B_Core/u_watchdog/reset_o_s0 |
| Launch Clk | init_clk_i[R] |
| Latch Clk | init_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | init_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/CLK |
| 0.636 | 0.306 | tC2Q | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/I0 |
| 1.429 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/F |
| 1.759 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/I0 |
| 2.222 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/F |
| 2.552 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/I0 |
| 3.015 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/F |
| 3.345 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/I0 |
| 3.808 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/F |
| 4.138 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/I0 |
| 4.601 | 0.463 | tINS | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/F |
| 4.931 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n8_s84/I2 |
| 5.337 | 0.406 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n8_s84/F |
| 5.667 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/reset_o_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | init_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/reset_o_s0/CLK |
| 10.081 | -0.249 | tSu | 1 | u_RoraLink_8B10B_Core/u_watchdog/reset_o_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 2.721, 50.983%; route: 2.310, 43.283%; tC2Q: 0.306, 5.734% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 2
Path Summary:| Slack | 4.540 |
| Data Arrival Time | 5.492 |
| Data Required Time | 10.032 |
| From | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0 |
| To | u_RoraLink_8B10B_Core/u_watchdog/count_0_s0 |
| Launch Clk | init_clk_i[R] |
| Latch Clk | init_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | init_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/CLK |
| 0.636 | 0.306 | tC2Q | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/I0 |
| 1.429 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/F |
| 1.759 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/I0 |
| 2.222 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/F |
| 2.552 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/I0 |
| 3.015 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/F |
| 3.345 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/I0 |
| 3.808 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/F |
| 4.138 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/I0 |
| 4.601 | 0.463 | tINS | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/F |
| 4.931 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/I3 |
| 5.162 | 0.231 | tINS | RR | 28 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/F |
| 5.492 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_0_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | init_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_0_s0/CLK |
| 10.032 | -0.298 | tSu | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.322%; route: 2.310, 44.750%; tC2Q: 0.306, 5.928% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 3
Path Summary:| Slack | 4.540 |
| Data Arrival Time | 5.492 |
| Data Required Time | 10.032 |
| From | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0 |
| To | u_RoraLink_8B10B_Core/u_watchdog/count_1_s0 |
| Launch Clk | init_clk_i[R] |
| Latch Clk | init_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | init_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/CLK |
| 0.636 | 0.306 | tC2Q | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/I0 |
| 1.429 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/F |
| 1.759 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/I0 |
| 2.222 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/F |
| 2.552 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/I0 |
| 3.015 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/F |
| 3.345 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/I0 |
| 3.808 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/F |
| 4.138 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/I0 |
| 4.601 | 0.463 | tINS | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/F |
| 4.931 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/I3 |
| 5.162 | 0.231 | tINS | RR | 28 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/F |
| 5.492 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_1_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | init_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_1_s0/CLK |
| 10.032 | -0.298 | tSu | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.322%; route: 2.310, 44.750%; tC2Q: 0.306, 5.928% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 4
Path Summary:| Slack | 4.540 |
| Data Arrival Time | 5.492 |
| Data Required Time | 10.032 |
| From | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0 |
| To | u_RoraLink_8B10B_Core/u_watchdog/count_2_s0 |
| Launch Clk | init_clk_i[R] |
| Latch Clk | init_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | init_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/CLK |
| 0.636 | 0.306 | tC2Q | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/I0 |
| 1.429 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/F |
| 1.759 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/I0 |
| 2.222 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/F |
| 2.552 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/I0 |
| 3.015 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/F |
| 3.345 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/I0 |
| 3.808 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/F |
| 4.138 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/I0 |
| 4.601 | 0.463 | tINS | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/F |
| 4.931 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/I3 |
| 5.162 | 0.231 | tINS | RR | 28 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/F |
| 5.492 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_2_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | init_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_2_s0/CLK |
| 10.032 | -0.298 | tSu | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.322%; route: 2.310, 44.750%; tC2Q: 0.306, 5.928% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 5
Path Summary:| Slack | 4.540 |
| Data Arrival Time | 5.492 |
| Data Required Time | 10.032 |
| From | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0 |
| To | u_RoraLink_8B10B_Core/u_watchdog/count_3_s0 |
| Launch Clk | init_clk_i[R] |
| Latch Clk | init_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | init_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/CLK |
| 0.636 | 0.306 | tC2Q | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/count_4_s0/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/I0 |
| 1.429 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s7/F |
| 1.759 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/I0 |
| 2.222 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s5/F |
| 2.552 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/I0 |
| 3.015 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s3/F |
| 3.345 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/I0 |
| 3.808 | 0.463 | tINS | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s2/F |
| 4.138 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/I0 |
| 4.601 | 0.463 | tINS | RR | 2 | u_RoraLink_8B10B_Core/u_watchdog/n226_s1/F |
| 4.931 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/I3 |
| 5.162 | 0.231 | tINS | RR | 28 | u_RoraLink_8B10B_Core/u_watchdog/n226_s0/F |
| 5.492 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_3_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | init_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | init_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 80 | init_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_3_s0/CLK |
| 10.032 | -0.298 | tSu | 1 | u_RoraLink_8B10B_Core/u_watchdog/count_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 2.546, 49.322%; route: 2.310, 44.750%; tC2Q: 0.306, 5.928% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |