Timing Messages

Report Title	Timing Analysis Report
Design File	F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\top.cst
Timing Constraint File	F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\top.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AC2/I1
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:28:14 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	9142
Numbers of Endpoints Analyzed	14745
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Objects
1	osc_clk_i	Base	20.000	50.000	10.000	osc_clk_i
2	cfg_clk	Base	20.000	50.000	10.000	cfg_clk
3	sys_clk	Base	12.800	78.125	6.400	sys_clk
4	tck_pad_i	Base	50.000	20.000	25.000	tck_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	cfg_clk	50.000(MHz)	91.315(MHz)	9	TOP
2	sys_clk	78.125(MHz)	111.513(MHz)	7	TOP
3	tck_pad_i	20.000(MHz)	87.170(MHz)	4	TOP

No timing paths to get frequency of osc_clk_i!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
osc_clk_i	Setup	0.000	0
osc_clk_i	Hold	0.000	0
cfg_clk	Setup	0.000	0
cfg_clk	Hold	0.000	0
sys_clk	Setup	0.000	0
sys_clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.833	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_10_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.025	8.892
2	4.249	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_4_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.017	8.483
3	4.652	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_7_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.007	8.090
4	4.779	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.000	7.970
5	5.072	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_29_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.080	7.597
6	5.397	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_26_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.012	7.341
7	5.425	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_2_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.025	7.299
8	5.430	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_6_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.002	7.317
9	5.606	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_24_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.011	7.132
10	5.620	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_31_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.010	7.119
11	5.623	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_3_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.025	7.101
12	5.660	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_9_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.025	7.064
13	5.688	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_13_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.032	7.029
14	5.708	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_11_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.109	6.932
15	5.814	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_13_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.015	6.921
16	5.820	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_11_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.002	6.927
17	5.825	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_14_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.019	6.905
18	5.832	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_27_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.009	6.908
19	5.853	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_14_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	-0.008	6.904
20	5.861	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_26_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.000	6.888
21	5.866	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_4_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.000	6.883
22	5.880	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_8_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.104	6.765
23	5.899	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_0_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.032	6.818
24	5.920	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_18_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	-0.013	6.842
25	5.922	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_12_s0/D	sys_clk:[R]	sys_clk:[R]	12.800	0.050	6.777

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.189	u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17]	sys_clk:[R]	sys_clk:[R]	-0.009	0.235
2	0.212	u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]	sys_clk:[R]	sys_clk:[R]	-0.009	0.258
3	0.214	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_16_s0/Q	u_SerDes_Top/gtr12_quad_inst0/FABRIC_LN0_TXDATA_I[20]	sys_clk:[R]	sys_clk:[R]	-0.034	0.303
4	0.220	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_22_s0/Q	u_SerDes_Top/gtr12_quad_inst0/FABRIC_LN0_TXDATA_I[26]	sys_clk:[R]	sys_clk:[R]	-0.034	0.303
5	0.273	u_la0_top/address_counter_2_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADB[6]	tck_pad_i:[R]	tck_pad_i:[R]	-0.013	0.321
6	0.275	u_la0_top/bit_count_3_s1/Q	u_la0_top/bit_count_3_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.300
7	0.275	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/Q	u_la0_top/u_ao_match_0/match_sep_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.222
8	0.275	u_la0_top/data_register_35_s0/Q	u_la0_top/data_register_34_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
9	0.275	u_la0_top/data_register_38_s0/Q	u_la0_top/data_register_37_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
10	0.275	u_la0_top/data_register_39_s0/Q	u_la0_top/data_register_38_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
11	0.275	u_la0_top/data_register_42_s0/Q	u_la0_top/data_register_41_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
12	0.275	u_la0_top/data_register_46_s0/Q	u_la0_top/data_register_45_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
13	0.275	u_la0_top/data_register_47_s0/Q	u_la0_top/data_register_46_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
14	0.275	u_la0_top/data_register_50_s0/Q	u_la0_top/data_register_49_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.222
15	0.275	u_frame_check/RX_D_R_31_s3/Q	u_frame_check/RX_D_R_31_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
16	0.275	u_frame_check/RX_D_R_30_s3/Q	u_frame_check/RX_D_R_30_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
17	0.275	u_frame_check/RX_D_R_28_s3/Q	u_frame_check/RX_D_R_28_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
18	0.275	u_data_axi_to_ll_reg/new_pkt_r_s0/Q	u_data_axi_to_ll_reg/new_pkt_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
19	0.275	u_frame_gen/bytes_sent_r_0_s1/Q	u_frame_gen/bytes_sent_r_0_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
20	0.275	u_frame_gen/bytes_sent_r_5_s0/Q	u_frame_gen/bytes_sent_r_5_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
21	0.275	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
22	0.275	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
23	0.275	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
24	0.275	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300
25	0.275	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/Q	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
2	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_3_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
3	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_9_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
4	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/start_reg_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
5	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_0_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
6	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_start_dly_1_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
7	3.191	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.356	3.287
8	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
9	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
10	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
11	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
12	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
13	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
14	3.198	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.363	3.287
15	3.217	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_4_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.350	3.256
16	3.217	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_6_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.350	3.256
17	3.217	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_window_sel_7_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.350	3.256
18	3.218	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	sys_clk:[F]	sys_clk:[R]	6.400	-0.346	3.250
19	3.218	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.346	3.250
20	3.218	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.346	3.250
21	3.218	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.346	3.250
22	3.218	u_la0_top/rst_ao_s0/Q	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.346	3.250
23	3.222	u_la0_top/rst_ao_s0/Q	u_la0_top/capture_end_dly_s0/PRESET	sys_clk:[F]	sys_clk:[R]	6.400	-0.344	3.244
24	3.222	u_la0_top/rst_ao_s0/Q	u_la0_top/triger_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.344	3.244
25	3.222	u_la0_top/rst_ao_s0/Q	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	sys_clk:[F]	sys_clk:[R]	6.400	-0.344	3.244

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.385	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_10_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.013	0.345
2	0.385	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.013	0.345
3	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
4	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
5	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
6	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
7	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
8	0.398	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.347
9	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
10	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
11	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
12	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
13	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
14	0.400	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.002	0.349
15	0.416	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.029	0.392
16	0.416	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_4_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.029	0.392
17	0.416	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_5_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.029	0.392
18	0.420	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.025	0.392
19	0.420	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.025	0.392
20	0.420	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.025	0.392
21	0.420	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.025	0.392
22	0.465	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_19_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.010	0.422
23	0.465	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_20_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.010	0.422
24	0.469	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_15_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.006	0.422
25	0.469	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	-0.006	0.422

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	4.199	5.061	0.862	High Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
2	4.199	5.061	0.862	High Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
3	4.202	5.064	0.862	High Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
4	4.202	5.064	0.862	High Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
5	4.251	5.113	0.862	Low Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
6	4.251	5.113	0.862	Low Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
7	4.254	5.116	0.862	Low Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
8	4.254	5.116	0.862	Low Pulse Width	sys_clk	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
9	4.790	4.990	0.200	High Pulse Width	sys_clk	crc_err_count_6_s0
10	4.790	4.990	0.200	High Pulse Width	sys_clk	crc_err_count_5_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.833
Data Arrival Time	12.066
Data Required Time	15.899
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_10_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
10.234	1.865	tNET	RR	1	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/I0
10.688	0.454	tINS	RR	3	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/F
11.607	0.919	tNET	RR	1	R34C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s0/I2
12.066	0.459	tINS	RR	1	R34C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s0/F
12.066	0.000	tNET	RR	1	R34C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.950	3.150	tNET	RR	1	R34C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_10_s0/CLK
15.899	-0.051	tSu		1	R34C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_10_s0

Path Statistics:

Clock Skew	-0.025
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.419, 27.204%; route: 6.167, 69.354%; tC2Q: 0.306, 3.441%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.150, 100.000%

Path2

Path Summary:

Slack	4.249
Data Arrival Time	11.657
Data Required Time	15.906
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_4_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
10.234	1.865	tNET	RR	1	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/I0
10.688	0.454	tINS	RR	3	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/F
11.194	0.506	tNET	RR	1	R26C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_4_s0/I2
11.657	0.463	tINS	RR	1	R26C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_4_s0/F
11.657	0.000	tNET	RR	1	R26C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.957	3.157	tNET	RR	1	R26C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_4_s0/CLK
15.906	-0.051	tSu		1	R26C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_4_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.423, 28.563%; route: 5.754, 67.830%; tC2Q: 0.306, 3.607%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.157, 100.000%

Path3

Path Summary:

Slack	4.652
Data Arrival Time	11.264
Data Required Time	15.916
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_7_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
10.234	1.865	tNET	RR	1	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/I0
10.688	0.454	tINS	RR	3	R23C37[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_10_s3/F
10.858	0.170	tNET	RR	1	R23C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_7_s0/I2
11.264	0.406	tINS	RR	1	R23C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_7_s0/F
11.264	0.000	tNET	RR	1	R23C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.967	3.167	tNET	RR	1	R23C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_7_s0/CLK
15.916	-0.051	tSu		1	R23C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_7_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.366, 29.246%; route: 5.418, 66.972%; tC2Q: 0.306, 3.782%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.167, 100.000%

Path4

Path Summary:

Slack	4.779
Data Arrival Time	11.144
Data Required Time	15.924
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
10.234	1.865	tNET	RR	1	R23C37[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_25_s1/I0
10.688	0.454	tINS	RR	1	R23C37[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_25_s1/F
10.690	0.002	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_25_s0/I0
11.144	0.454	tINS	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_25_s0/F
11.144	0.000	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.975	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
15.924	-0.051	tSu		1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.414, 30.289%; route: 5.250, 65.872%; tC2Q: 0.306, 3.839%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%

Path5

Path Summary:

Slack	5.072
Data Arrival Time	10.771
Data Required Time	15.843
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_29_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
9.868	1.499	tNET	RR	1	R24C36[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s3/I2
10.306	0.438	tINS	RR	1	R24C36[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s3/F
10.308	0.002	tNET	RR	1	R24C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s0/I3
10.771	0.463	tINS	RR	1	R24C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s0/F
10.771	0.000	tNET	RR	1	R24C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.894	3.094	tNET	RR	1	R24C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_29_s0/CLK
15.843	-0.051	tSu		1	R24C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_29_s0

Path Statistics:

Clock Skew	-0.080
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.407, 31.684%; route: 4.884, 64.289%; tC2Q: 0.306, 4.028%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.094, 100.000%

Path6

Path Summary:

Slack	5.397
Data Arrival Time	10.516
Data Required Time	15.912
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_26_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
9.652	1.282	tNET	RR	1	R25C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s1/I1
9.907	0.255	tINS	RF	1	R25C37[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s1/F
10.062	0.155	tNET	FF	1	R25C38[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s0/I0
10.516	0.454	tINS	FR	1	R25C38[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s0/F
10.516	0.000	tNET	RR	1	R25C38[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.963	3.163	tNET	RR	1	R25C38[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_26_s0/CLK
15.912	-0.051	tSu		1	R25C38[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_26_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.215, 30.173%; route: 4.820, 65.659%; tC2Q: 0.306, 4.168%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.163, 100.000%

Path7

Path Summary:

Slack	5.425
Data Arrival Time	10.372
Data Required Time	15.797
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_2_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.163	0.460	tNET	RR	1	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/I0
9.626	0.463	tINS	RR	4	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/F
9.966	0.340	tNET	RR	1	R30C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_2_s0/I1
10.372	0.406	tINS	RR	1	R30C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_2_s0/F
10.372	0.000	tNET	RR	1	R30C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.848	3.048	tNET	RR	1	R30C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_2_s0/CLK
15.797	-0.051	tSu		1	R30C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_2_s0

Path Statistics:

Clock Skew	-0.025
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.373, 32.511%; route: 4.620, 63.296%; tC2Q: 0.306, 4.192%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.048, 100.000%

Path8

Path Summary:

Slack	5.430
Data Arrival Time	10.390
Data Required Time	15.820
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_6_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.163	0.460	tNET	RR	1	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/I0
9.626	0.463	tINS	RR	4	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/F
9.984	0.358	tNET	RR	1	R26C22[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_6_s0/I1
10.390	0.406	tINS	RR	1	R26C22[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_6_s0/F
10.390	0.000	tNET	RR	1	R26C22[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.871	3.071	tNET	RR	1	R26C22[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_6_s0/CLK
15.820	-0.051	tSu		1	R26C22[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_6_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.373, 32.431%; route: 4.638, 63.387%; tC2Q: 0.306, 4.182%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.071, 100.000%

Path9

Path Summary:

Slack	5.606
Data Arrival Time	10.205
Data Required Time	15.811
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_24_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.163	0.460	tNET	RR	1	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/I0
9.626	0.463	tINS	RR	4	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/F
9.799	0.173	tNET	RR	1	R29C25[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s0/I1
10.205	0.406	tINS	RR	1	R29C25[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s0/F
10.205	0.000	tNET	RR	1	R29C25[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.862	3.062	tNET	RR	1	R29C25[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_24_s0/CLK
15.811	-0.051	tSu		1	R29C25[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_24_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.373, 33.273%; route: 4.453, 62.437%; tC2Q: 0.306, 4.291%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.062, 100.000%

Path10

Path Summary:

Slack	5.620
Data Arrival Time	10.196
Data Required Time	15.816
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_31_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.077	3.077	tNET	RR	1	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/CLK
3.383	0.306	tC2Q	RR	3	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q
4.124	0.741	tNET	RR	1	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/I2
4.587	0.463	tINS	RR	15	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/F
5.272	0.685	tNET	RR	1	R32C38[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s5/I1
5.726	0.454	tINS	RR	6	R32C38[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s5/F
6.265	0.539	tNET	RR	1	R34C35[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s23/I3
6.724	0.459	tINS	RR	10	R34C35[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s23/F
7.143	0.419	tNET	RR	1	R24C34[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s1/I1
7.581	0.438	tINS	RR	8	R24C34[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s1/F
9.215	1.634	tNET	RR	1	R36C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s3/I2
9.621	0.406	tINS	RR	1	R36C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s3/F
9.742	0.121	tNET	RR	1	R36C35[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s17/I3
10.196	0.454	tINS	RR	1	R36C35[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s17/F
10.196	0.000	tNET	RR	1	R36C35[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.867	3.067	tNET	RR	1	R36C35[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_31_s0/CLK
15.816	-0.051	tSu		1	R36C35[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_31_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.077, 100.000%
Arrival Data Path Delay	cell: 2.674, 37.561%; route: 4.139, 58.140%; tC2Q: 0.306, 4.298%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.067, 100.000%

Path11

Path Summary:

Slack	5.623
Data Arrival Time	10.174
Data Required Time	15.797
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_3_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.163	0.460	tNET	RR	1	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/I0
9.626	0.463	tINS	RR	4	R29C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s1/F
9.768	0.142	tNET	RR	1	R30C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_3_s0/I2
10.174	0.406	tINS	RR	1	R30C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_3_s0/F
10.174	0.000	tNET	RR	1	R30C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.848	3.048	tNET	RR	1	R30C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_3_s0/CLK
15.797	-0.051	tSu		1	R30C23[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_3_s0

Path Statistics:

Clock Skew	-0.025
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.373, 33.418%; route: 4.422, 62.273%; tC2Q: 0.306, 4.309%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.048, 100.000%

Path12

Path Summary:

Slack	5.660
Data Arrival Time	10.137
Data Required Time	15.797
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_9_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.330	0.627	tNET	RR	1	R29C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_9_s2/I1
9.768	0.438	tINS	RR	1	R29C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_9_s2/F
9.906	0.138	tNET	RR	1	R30C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_9_s0/I2
10.137	0.231	tINS	RR	1	R30C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_9_s0/F
10.137	0.000	tNET	RR	1	R30C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.848	3.048	tNET	RR	1	R30C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_9_s0/CLK
15.797	-0.051	tSu		1	R30C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_9_s0

Path Statistics:

Clock Skew	-0.025
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.173, 30.762%; route: 4.585, 64.907%; tC2Q: 0.306, 4.332%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.048, 100.000%

Path13

Path Summary:

Slack	5.688
Data Arrival Time	10.102
Data Required Time	15.790
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_13_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s16/I0
6.046	0.365	tINS	RR	7	R27C26[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s16/F
6.728	0.682	tNET	RR	1	R23C22[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s4/I1
7.187	0.459	tINS	RR	8	R23C22[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s4/F
7.986	0.799	tNET	RR	1	R26C24[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s5/I2
8.440	0.454	tINS	RR	3	R26C24[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s5/F
8.749	0.309	tNET	RR	1	R27C23[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_13_s1/I1
9.187	0.438	tINS	RR	1	R27C23[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_13_s1/F
9.639	0.452	tNET	RR	1	R30C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_13_s0/I0
10.102	0.463	tINS	RR	1	R30C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_13_s0/F
10.102	0.000	tNET	RR	1	R30C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.841	3.041	tNET	RR	1	R30C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_13_s0/CLK
15.790	-0.051	tSu		1	R30C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_13_s0

Path Statistics:

Clock Skew	-0.032
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.633, 37.459%; route: 4.090, 58.188%; tC2Q: 0.306, 4.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.041, 100.000%

Path14

Path Summary:

Slack	5.708
Data Arrival Time	10.106
Data Required Time	15.815
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_11_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
8.714	0.344	tNET	RR	1	R32C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s3/I1
9.167	0.454	tINS	RR	3	R32C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s3/F
9.643	0.476	tNET	RR	1	R35C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s0/I2
10.106	0.463	tINS	RR	1	R35C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s0/F
10.106	0.000	tNET	RR	1	R35C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.866	3.066	tNET	RR	1	R35C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_11_s0/CLK
15.815	-0.051	tSu		1	R35C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_11_s0

Path Statistics:

Clock Skew	-0.109
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.423, 34.954%; route: 4.203, 60.632%; tC2Q: 0.306, 4.414%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.066, 100.000%

Path15

Path Summary:

Slack	5.814
Data Arrival Time	9.998
Data Required Time	15.812
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_13_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.077	3.077	tNET	RR	1	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/CLK
3.383	0.306	tC2Q	RR	3	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q
4.124	0.741	tNET	RR	1	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/I2
4.587	0.463	tINS	RR	15	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/F
5.073	0.486	tNET	RR	1	R32C37[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s9/I3
5.536	0.463	tINS	RR	14	R32C37[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s9/F
6.137	0.601	tNET	RR	1	R34C36[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s1/I0
6.591	0.454	tINS	RR	10	R34C36[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s1/F
7.481	0.890	tNET	RR	1	R30C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s3/I0
7.944	0.463	tINS	RR	8	R30C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s3/F
8.786	0.842	tNET	RR	1	R35C33[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_13_s3/I2
9.245	0.459	tINS	RR	2	R35C33[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_13_s3/F
9.535	0.290	tNET	RR	1	R33C33[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_13_s0/I2
9.998	0.463	tINS	RR	1	R33C33[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_13_s0/F
9.998	0.000	tNET	RR	1	R33C33[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.863	3.063	tNET	RR	1	R33C33[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_13_s0/CLK
15.812	-0.051	tSu		1	R33C33[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_13_s0

Path Statistics:

Clock Skew	-0.015
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.077, 100.000%
Arrival Data Path Delay	cell: 2.765, 39.951%; route: 3.850, 55.628%; tC2Q: 0.306, 4.421%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.063, 100.000%

Path16

Path Summary:

Slack	5.820
Data Arrival Time	10.000
Data Required Time	15.820
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_11_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C24[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s5/I3
7.290	0.231	tINS	RR	11	R23C24[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s5/F
8.032	0.742	tNET	RR	1	R25C26[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s7/I1
8.486	0.454	tINS	RR	8	R25C26[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s7/F
8.801	0.315	tNET	RR	1	R26C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_11_s3/I3
9.239	0.438	tINS	RR	2	R26C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_11_s3/F
9.546	0.307	tNET	RR	1	R26C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_11_s0/I2
10.000	0.454	tINS	RR	1	R26C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_11_s0/F
10.000	0.000	tNET	RR	1	R26C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.871	3.071	tNET	RR	1	R26C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_11_s0/CLK
15.820	-0.051	tSu		1	R26C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_11_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.262, 32.655%; route: 4.359, 62.928%; tC2Q: 0.306, 4.417%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.071, 100.000%

Path17

Path Summary:

Slack	5.825
Data Arrival Time	9.982
Data Required Time	15.807
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_14_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.077	3.077	tNET	RR	1	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/CLK
3.383	0.306	tC2Q	RR	3	R25C34[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crc_data_i_24_s0/Q
4.124	0.741	tNET	RR	1	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/I2
4.587	0.463	tINS	RR	15	R31C34[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s4/F
5.073	0.486	tNET	RR	1	R32C37[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s9/I3
5.536	0.463	tINS	RR	14	R32C37[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s9/F
6.137	0.601	tNET	RR	1	R34C36[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s1/I0
6.591	0.454	tINS	RR	10	R34C36[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_0_s1/F
7.481	0.890	tNET	RR	1	R30C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s3/I0
7.944	0.463	tINS	RR	8	R30C35[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_26_s3/F
8.834	0.890	tNET	RR	1	R35C36[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_14_s2/I2
9.240	0.406	tINS	RR	1	R35C36[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_14_s2/F
9.528	0.288	tNET	RR	1	R35C34[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_14_s0/I2
9.982	0.454	tINS	RR	1	R35C34[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_14_s0/F
9.982	0.000	tNET	RR	1	R35C34[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.858	3.058	tNET	RR	1	R35C34[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_14_s0/CLK
15.807	-0.051	tSu		1	R35C34[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_14_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.077, 100.000%
Arrival Data Path Delay	cell: 2.703, 39.146%; route: 3.896, 56.423%; tC2Q: 0.306, 4.432%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.058, 100.000%

Path18

Path Summary:

Slack	5.832
Data Arrival Time	10.006
Data Required Time	15.838
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_27_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.098	3.098	tNET	RR	1	R22C24[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/CLK
3.404	0.306	tC2Q	RR	6	R22C24[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/Q
4.003	0.599	tNET	RR	1	R25C23[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s11/I3
4.466	0.463	tINS	RR	5	R25C23[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s11/F
5.109	0.643	tNET	RR	1	R22C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s6/I0
5.563	0.454	tINS	RR	8	R22C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s6/F
7.031	1.468	tNET	RR	1	R29C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s13/I2
7.494	0.463	tINS	RR	5	R29C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s13/F
8.119	0.625	tNET	RR	1	R26C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s15/I0
8.352	0.233	tINS	RR	7	R26C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s15/F
8.784	0.432	tNET	RR	1	R24C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s1/I0
9.238	0.454	tINS	RR	1	R24C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s1/F
9.543	0.305	tNET	RR	1	R23C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s0/I0
10.006	0.463	tINS	RR	1	R23C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_27_s0/F
10.006	0.000	tNET	RR	1	R23C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.889	3.089	tNET	RR	1	R23C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_27_s0/CLK
15.838	-0.051	tSu		1	R23C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_27_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%
Arrival Data Path Delay	cell: 2.530, 36.624%; route: 4.072, 58.946%; tC2Q: 0.306, 4.430%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.089, 100.000%

Path19

Path Summary:

Slack	5.853
Data Arrival Time	9.977
Data Required Time	15.830
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_14_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
8.995	0.292	tNET	RR	1	R24C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_14_s2/I1
9.226	0.231	tINS	RR	1	R24C22[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_14_s2/F
9.514	0.288	tNET	RR	1	R23C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_14_s0/I1
9.977	0.463	tINS	RR	1	R23C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_14_s0/F
9.977	0.000	tNET	RR	1	R23C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R23C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_14_s0/CLK
15.830	-0.051	tSu		1	R23C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_14_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.198, 31.837%; route: 4.400, 63.731%; tC2Q: 0.306, 4.432%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path20

Path Summary:

Slack	5.861
Data Arrival Time	9.961
Data Required Time	15.822
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_26_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.350	0.647	tNET	RR	1	R27C26[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s8/I2
9.605	0.255	tINS	RF	1	R27C26[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s8/F
9.730	0.125	tNET	FF	1	R27C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s0/I0
9.961	0.231	tINS	FR	1	R27C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_26_s0/F
9.961	0.000	tNET	RR	1	R27C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.873	3.073	tNET	RR	1	R27C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_26_s0/CLK
15.822	-0.051	tSu		1	R27C25[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_26_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 1.990, 28.891%; route: 4.592, 66.667%; tC2Q: 0.306, 4.443%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%

Path21

Path Summary:

Slack	5.866
Data Arrival Time	9.956
Data Required Time	15.822
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_4_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.249	0.825	tNET	RR	1	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/I0
8.703	0.454	tINS	RR	7	R26C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_28_s4/F
9.183	0.480	tNET	RR	1	R27C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_4_s2/I1
9.548	0.365	tINS	RR	1	R27C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_4_s2/F
9.550	0.002	tNET	RR	1	R27C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_4_s0/I2
9.956	0.406	tINS	RR	1	R27C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_4_s0/F
9.956	0.000	tNET	RR	1	R27C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.873	3.073	tNET	RR	1	R27C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_4_s0/CLK
15.822	-0.051	tSu		1	R27C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.275, 33.052%; route: 4.302, 62.502%; tC2Q: 0.306, 4.446%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%

Path22

Path Summary:

Slack	5.880
Data Arrival Time	9.939
Data Required Time	15.819
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_8_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.175	3.175	tNET	RR	1	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/CLK
3.481	0.306	tC2Q	RR	6	R23C37[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_25_s0/Q
3.977	0.496	tNET	RR	1	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/I0
4.208	0.231	tINS	RR	16	R30C35[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_30_s12/F
5.193	0.985	tNET	RR	1	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/I2
5.599	0.406	tINS	RR	19	R34C36[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_31_s8/F
6.117	0.518	tNET	RR	1	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/I0
6.580	0.463	tINS	RR	12	R34C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_3_s3/F
7.964	1.384	tNET	RR	1	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/I1
8.370	0.406	tINS	RR	10	R35C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_29_s9/F
8.714	0.344	tNET	RR	1	R32C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s3/I1
9.167	0.454	tINS	RR	3	R32C33[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_11_s3/F
9.476	0.309	tNET	RR	1	R33C32[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_8_s0/I1
9.939	0.463	tINS	RR	1	R33C32[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/msg_8_s0/F
9.939	0.000	tNET	RR	1	R33C32[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.870	3.070	tNET	RR	1	R33C32[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_8_s0/CLK
15.819	-0.051	tSu		1	R33C32[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/tx_crc_gen[0].crc_gen/crcreg_8_s0

Path Statistics:

Clock Skew	-0.104
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.175, 100.000%
Arrival Data Path Delay	cell: 2.423, 35.817%; route: 4.036, 59.660%; tC2Q: 0.306, 4.523%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.070, 100.000%

Path23

Path Summary:

Slack	5.899
Data Arrival Time	9.891
Data Required Time	15.790
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_0_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s16/I0
6.046	0.365	tINS	RR	7	R27C26[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s16/F
6.728	0.682	tNET	RR	1	R23C22[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s4/I1
7.187	0.459	tINS	RR	8	R23C22[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s4/F
7.360	0.173	tNET	RR	1	R23C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s14/I0
7.823	0.463	tINS	RR	5	R23C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s14/F
8.466	0.643	tNET	RR	1	R26C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_23_s7/I0
8.920	0.454	tINS	RR	3	R26C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_23_s7/F
9.428	0.508	tNET	RR	1	R30C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_0_s3/I0
9.891	0.463	tINS	RR	1	R30C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_0_s3/F
9.891	0.000	tNET	RR	1	R30C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.841	3.041	tNET	RR	1	R30C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_0_s0/CLK
15.790	-0.051	tSu		1	R30C26[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_0_s0

Path Statistics:

Clock Skew	-0.032
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.658, 38.985%; route: 3.854, 56.527%; tC2Q: 0.306, 4.488%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.041, 100.000%

Path24

Path Summary:

Slack	5.920
Data Arrival Time	9.915
Data Required Time	15.835
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_18_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.073	3.073	tNET	RR	1	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/CLK
3.379	0.306	tC2Q	RR	7	R27C25[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_30_s0/Q
4.086	0.707	tNET	RR	1	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/I2
4.540	0.454	tINS	RR	19	R22C22[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_31_s21/F
5.681	1.141	tNET	RR	1	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/I2
5.912	0.231	tINS	RR	19	R27C26[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s4/F
7.059	1.147	tNET	RR	1	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/I0
7.424	0.365	tINS	RR	13	R23C25[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_24_s4/F
8.199	0.775	tNET	RR	1	R24C22[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_10_s1/I0
8.605	0.406	tINS	RR	2	R24C22[2][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_10_s1/F
8.912	0.307	tNET	RR	1	R26C23[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s3/I2
9.371	0.459	tINS	RR	1	R26C23[3][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s3/F
9.509	0.138	tNET	RR	1	R26C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s0/I3
9.915	0.406	tINS	RR	1	R26C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_18_s0/F
9.915	0.000	tNET	RR	1	R26C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.886	3.086	tNET	RR	1	R26C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_18_s0/CLK
15.835	-0.051	tSu		1	R26C24[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_18_s0

Path Statistics:

Clock Skew	0.013
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.073, 100.000%
Arrival Data Path Delay	cell: 2.321, 33.923%; route: 4.215, 61.605%; tC2Q: 0.306, 4.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.086, 100.000%

Path25

Path Summary:

Slack	5.922
Data Arrival Time	9.875
Data Required Time	15.797
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_12_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.098	3.098	tNET	RR	1	R22C24[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/CLK
3.404	0.306	tC2Q	RR	6	R22C24[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/DATA_US_2r_29_s0/Q
4.003	0.599	tNET	RR	1	R25C23[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s11/I3
4.466	0.463	tINS	RR	5	R25C23[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s11/F
5.109	0.643	tNET	RR	1	R22C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s6/I0
5.563	0.454	tINS	RR	8	R22C22[1][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_30_s6/F
7.031	1.468	tNET	RR	1	R29C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s13/I2
7.494	0.463	tINS	RR	5	R29C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s13/F
8.119	0.625	tNET	RR	1	R26C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s15/I0
8.352	0.233	tINS	RR	7	R26C25[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_29_s15/F
8.811	0.459	tNET	RR	1	R30C24[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_12_s2/I1
9.274	0.463	tINS	RR	1	R30C24[2][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_12_s2/F
9.412	0.138	tNET	RR	1	R30C23[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_12_s0/I1
9.875	0.463	tINS	RR	1	R30C23[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/msg_12_s0/F
9.875	0.000	tNET	RR	1	R30C23[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.848	3.048	tNET	RR	1	R30C23[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_12_s0/CLK
15.797	-0.051	tSu		1	R30C23[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/rx_crc_gen[0].crc_gen/crcreg_12_s0

Path Statistics:

Clock Skew	-0.050
Setup Relationship	12.800
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%
Arrival Data Path Delay	cell: 2.539, 37.465%; route: 3.932, 58.020%; tC2Q: 0.306, 4.515%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.048, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.189
Data Arrival Time	1.657
Data Required Time	1.468
From	u_la0_top/u_ao_mem_ctrl/data_reg_53_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.422	1.422	tNET	RR	1	R11C6[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK
1.563	0.141	tC2Q	RF	1	R11C6[1][B]	u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q
1.657	0.094	tNET	FF	1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.431	1.431	tNET	RR	1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.468	0.037	tHld		1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.422, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.431, 100.000%

Path2

Path Summary:

Slack	0.212
Data Arrival Time	1.680
Data Required Time	1.468
From	u_la0_top/u_ao_mem_ctrl/data_reg_47_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.422	1.422	tNET	RR	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/CLK
1.563	0.141	tC2Q	RF	1	R11C6[0][B]	u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q
1.680	0.117	tNET	FF	1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.431	1.431	tNET	RR	1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.468	0.037	tHld		1	BSRAM_R10[1][A]	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.422, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.431, 100.000%

Path3

Path Summary:

Slack	0.214
Data Arrival Time	1.739
Data Required Time	1.525
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_16_s0
To	u_SerDes_Top/gtr12_quad_inst0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R11C38[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_16_s0/CLK
1.577	0.141	tC2Q	RF	1	R11C38[3][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_16_s0/Q
1.739	0.162	tNET	FF	1	R0C38	u_SerDes_Top/gtr12_quad_inst0/FABRIC_LN0_TXDATA_I[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.470	1.470	tNET	RR	1	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_FABRIC_TX_CLK
1.525	0.054	tHld		1	R0C38	u_SerDes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.034
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.162, 53.465%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.470, 100.000%

Path4

Path Summary:

Slack	0.220
Data Arrival Time	1.739
Data Required Time	1.519
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_22_s0
To	u_SerDes_Top/gtr12_quad_inst0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R11C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_22_s0/CLK
1.577	0.141	tC2Q	RF	1	R11C38[0][B]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_data_r_22_s0/Q
1.739	0.162	tNET	FF	1	R0C38	u_SerDes_Top/gtr12_quad_inst0/FABRIC_LN0_TXDATA_I[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.470	1.470	tNET	RR	1	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_FABRIC_TX_CLK
1.519	0.049	tHld		1	R0C38	u_SerDes_Top/gtr12_quad_inst0

Path Statistics:

Clock Skew	0.034
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.162, 53.465%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.470, 100.000%

Path5

Path Summary:

Slack	0.273
Data Arrival Time	3.718
Data Required Time	3.445
From	u_la0_top/address_counter_2_s0
To	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.397	2.235	tNET	RR	1	u_la0_top/address_counter_2_s0/CLK
3.538	0.141	tC2Q	RF	7	u_la0_top/address_counter_2_s0/Q
3.718	0.180	tNET	FF	1	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.410	2.248	tNET	RR	1	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB
3.445	0.035	tHld		1	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.204%; route: 2.235, 65.796%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.180, 56.075%; tC2Q: 0.141, 43.925%
Required Clock Path Delay	cell: 1.162, 34.074%; route: 2.248, 65.926%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	3.730
Data Required Time	3.455
From	u_la0_top/bit_count_3_s1
To	u_la0_top/bit_count_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.430	2.268	tNET	RR	1	u_la0_top/bit_count_3_s1/CLK
3.571	0.141	tC2Q	RF	3	u_la0_top/bit_count_3_s1/Q
3.577	0.006	tNET	FF	1	u_la0_top/n708_s2/I0
3.730	0.153	tINS	FF	1	u_la0_top/n708_s2/F
3.730	0.000	tNET	FF	1	u_la0_top/bit_count_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.430	2.268	tNET	RR	1	u_la0_top/bit_count_3_s1/CLK
3.455	0.025	tHld		1	u_la0_top/bit_count_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.162, 33.872%; route: 2.268, 66.128%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.162, 33.872%; route: 2.268, 66.128%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.670
Data Required Time	1.395
From	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
To	u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R6C3[0][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.592	0.144	tC2Q	RR	1	R6C3[0][A]	u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/Q
1.670	0.078	tNET	RR	1	R6C3[1][A]	u_la0_top/u_ao_match_0/match_sep_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R6C3[1][A]	u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.395	-0.053	tHld		1	R6C3[1][A]	u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	3.637
Data Required Time	3.362
From	u_la0_top/data_register_35_s0
To	u_la0_top/data_register_34_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_35_s0/CLK
3.559	0.144	tC2Q	RR	1	u_la0_top/data_register_35_s0/Q
3.637	0.078	tNET	RR	1	u_la0_top/data_register_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_34_s0/CLK
3.362	-0.053	tHld		1	u_la0_top/data_register_34_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	3.637
Data Required Time	3.362
From	u_la0_top/data_register_38_s0
To	u_la0_top/data_register_37_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_38_s0/CLK
3.559	0.144	tC2Q	RR	1	u_la0_top/data_register_38_s0/Q
3.637	0.078	tNET	RR	1	u_la0_top/data_register_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_37_s0/CLK
3.362	-0.053	tHld		1	u_la0_top/data_register_37_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	3.637
Data Required Time	3.362
From	u_la0_top/data_register_39_s0
To	u_la0_top/data_register_38_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_39_s0/CLK
3.559	0.144	tC2Q	RR	1	u_la0_top/data_register_39_s0/Q
3.637	0.078	tNET	RR	1	u_la0_top/data_register_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.415	2.253	tNET	RR	1	u_la0_top/data_register_38_s0/CLK
3.362	-0.053	tHld		1	u_la0_top/data_register_38_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.024%; route: 2.253, 65.976%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	3.633
Data Required Time	3.358
From	u_la0_top/data_register_42_s0
To	u_la0_top/data_register_41_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.411	2.249	tNET	RR	1	u_la0_top/data_register_42_s0/CLK
3.555	0.144	tC2Q	RR	1	u_la0_top/data_register_42_s0/Q
3.633	0.078	tNET	RR	1	u_la0_top/data_register_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.411	2.249	tNET	RR	1	u_la0_top/data_register_41_s0/CLK
3.358	-0.053	tHld		1	u_la0_top/data_register_41_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.064%; route: 2.249, 65.936%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.064%; route: 2.249, 65.936%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	3.629
Data Required Time	3.354
From	u_la0_top/data_register_46_s0
To	u_la0_top/data_register_45_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.407	2.245	tNET	RR	1	u_la0_top/data_register_46_s0/CLK
3.551	0.144	tC2Q	RR	1	u_la0_top/data_register_46_s0/Q
3.629	0.078	tNET	RR	1	u_la0_top/data_register_45_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.407	2.245	tNET	RR	1	u_la0_top/data_register_45_s0/CLK
3.354	-0.053	tHld		1	u_la0_top/data_register_45_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.104%; route: 2.245, 65.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.104%; route: 2.245, 65.896%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	3.629
Data Required Time	3.354
From	u_la0_top/data_register_47_s0
To	u_la0_top/data_register_46_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.407	2.245	tNET	RR	1	u_la0_top/data_register_47_s0/CLK
3.551	0.144	tC2Q	RR	1	u_la0_top/data_register_47_s0/Q
3.629	0.078	tNET	RR	1	u_la0_top/data_register_46_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.407	2.245	tNET	RR	1	u_la0_top/data_register_46_s0/CLK
3.354	-0.053	tHld		1	u_la0_top/data_register_46_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.104%; route: 2.245, 65.896%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.104%; route: 2.245, 65.896%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	3.633
Data Required Time	3.358
From	u_la0_top/data_register_50_s0
To	u_la0_top/data_register_49_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.411	2.249	tNET	RR	1	u_la0_top/data_register_50_s0/CLK
3.555	0.144	tC2Q	RR	1	u_la0_top/data_register_50_s0/Q
3.633	0.078	tNET	RR	1	u_la0_top/data_register_49_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				tck_pad_i
0.000	0.000	tCL	RR	1	tck_ibuf/I
0.581	0.581	tINS	RR	1	tck_ibuf/O
0.581	0.000	tNET	RR	1	u_gw_jtag/tck_pad_i
1.162	0.581	tINS	RR	319	u_gw_jtag/tck_o
3.411	2.249	tNET	RR	1	u_la0_top/data_register_49_s0/CLK
3.358	-0.053	tHld		1	u_la0_top/data_register_49_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.162, 34.064%; route: 2.249, 65.936%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 1.162, 34.064%; route: 2.249, 65.936%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.748
Data Required Time	1.473
From	u_frame_check/RX_D_R_31_s3
To	u_frame_check/RX_D_R_31_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R24C31[1][A]	u_frame_check/RX_D_R_31_s3/CLK
1.589	0.141	tC2Q	RF	2	R24C31[1][A]	u_frame_check/RX_D_R_31_s3/Q
1.595	0.006	tNET	FF	1	R24C31[1][A]	u_frame_check/n133_s2/I2
1.748	0.153	tINS	FF	1	R24C31[1][A]	u_frame_check/n133_s2/F
1.748	0.000	tNET	FF	1	R24C31[1][A]	u_frame_check/RX_D_R_31_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R24C31[1][A]	u_frame_check/RX_D_R_31_s3/CLK
1.473	0.025	tHld		1	R24C31[1][A]	u_frame_check/RX_D_R_31_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.750
Data Required Time	1.475
From	u_frame_check/RX_D_R_30_s3
To	u_frame_check/RX_D_R_30_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R23C31[0][A]	u_frame_check/RX_D_R_30_s3/CLK
1.591	0.141	tC2Q	RF	2	R23C31[0][A]	u_frame_check/RX_D_R_30_s3/Q
1.597	0.006	tNET	FF	1	R23C31[0][A]	u_frame_check/n132_s2/I2
1.750	0.153	tINS	FF	1	R23C31[0][A]	u_frame_check/n132_s2/F
1.750	0.000	tNET	FF	1	R23C31[0][A]	u_frame_check/RX_D_R_30_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R23C31[0][A]	u_frame_check/RX_D_R_30_s3/CLK
1.475	0.025	tHld		1	R23C31[0][A]	u_frame_check/RX_D_R_30_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.750
Data Required Time	1.475
From	u_frame_check/RX_D_R_28_s3
To	u_frame_check/RX_D_R_28_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R23C31[1][A]	u_frame_check/RX_D_R_28_s3/CLK
1.591	0.141	tC2Q	RF	2	R23C31[1][A]	u_frame_check/RX_D_R_28_s3/Q
1.597	0.006	tNET	FF	1	R23C31[1][A]	u_frame_check/n130_s2/I2
1.750	0.153	tINS	FF	1	R23C31[1][A]	u_frame_check/n130_s2/F
1.750	0.000	tNET	FF	1	R23C31[1][A]	u_frame_check/RX_D_R_28_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R23C31[1][A]	u_frame_check/RX_D_R_28_s3/CLK
1.475	0.025	tHld		1	R23C31[1][A]	u_frame_check/RX_D_R_28_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.730
Data Required Time	1.455
From	u_data_axi_to_ll_reg/new_pkt_r_s0
To	u_data_axi_to_ll_reg/new_pkt_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.430	1.430	tNET	RR	1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_r_s0/CLK
1.571	0.141	tC2Q	RF	2	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_r_s0/Q
1.577	0.006	tNET	FF	1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_s1/I0
1.730	0.153	tINS	FF	1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_s1/F
1.730	0.000	tNET	FF	1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.430	1.430	tNET	RR	1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_r_s0/CLK
1.455	0.025	tHld		1	R29C28[0][A]	u_data_axi_to_ll_reg/new_pkt_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.430, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.430, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.736
Data Required Time	1.461
From	u_frame_gen/bytes_sent_r_0_s1
To	u_frame_gen/bytes_sent_r_0_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R27C33[0][A]	u_frame_gen/bytes_sent_r_0_s1/CLK
1.577	0.141	tC2Q	RF	3	R27C33[0][A]	u_frame_gen/bytes_sent_r_0_s1/Q
1.583	0.006	tNET	FF	1	R27C33[0][A]	u_frame_gen/n199_s5/I3
1.736	0.153	tINS	FF	1	R27C33[0][A]	u_frame_gen/n199_s5/F
1.736	0.000	tNET	FF	1	R27C33[0][A]	u_frame_gen/bytes_sent_r_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R27C33[0][A]	u_frame_gen/bytes_sent_r_0_s1/CLK
1.461	0.025	tHld		1	R27C33[0][A]	u_frame_gen/bytes_sent_r_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.740
Data Required Time	1.465
From	u_frame_gen/bytes_sent_r_5_s0
To	u_frame_gen/bytes_sent_r_5_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R27C32[0][A]	u_frame_gen/bytes_sent_r_5_s0/CLK
1.581	0.141	tC2Q	RF	5	R27C32[0][A]	u_frame_gen/bytes_sent_r_5_s0/Q
1.587	0.006	tNET	FF	1	R27C32[0][A]	u_frame_gen/n204_s3/I2
1.740	0.153	tINS	FF	1	R27C32[0][A]	u_frame_gen/n204_s3/F
1.740	0.000	tNET	FF	1	R27C32[0][A]	u_frame_gen/bytes_sent_r_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R27C32[0][A]	u_frame_gen/bytes_sent_r_5_s0/CLK
1.465	0.025	tHld		1	R27C32[0][A]	u_frame_gen/bytes_sent_r_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.736
Data Required Time	1.461
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/CLK
1.577	0.141	tC2Q	RF	2	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/Q
1.583	0.006	tNET	FF	1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/n35_s1/I0
1.736	0.153	tINS	FF	1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/n35_s1/F
1.736	0.000	tNET	FF	1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.436	1.436	tNET	RR	1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0/CLK
1.461	0.025	tHld		1	R35C28[1][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_RoraLink_8B10B_rx_ll/u_RoraLink_8B10B_rx_ll_pdu/u_RoraLink_8B10B_rx_sideband_out/pad_storage_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.436, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/CLK
1.592	0.141	tC2Q	RF	2	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/Q
1.598	0.006	tNET	FF	1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_c_s2/I2
1.751	0.153	tINS	FF	1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_c_s2/F
1.751	0.000	tNET	FF	1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0/CLK
1.476	0.025	tHld		1	R22C27[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/idle_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/CLK
1.592	0.141	tC2Q	RF	2	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/Q
1.598	0.006	tNET	FF	1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_c_s0/I0
1.751	0.153	tINS	FF	1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_c_s0/F
1.751	0.000	tNET	FF	1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0/CLK
1.476	0.025	tHld		1	R22C25[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_rx_crc/data_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.726
Data Required Time	1.451
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.426	1.426	tNET	RR	1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/CLK
1.567	0.141	tC2Q	RF	10	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/Q
1.573	0.006	tNET	FF	1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/n393_s3/I2
1.726	0.153	tINS	FF	1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/n393_s3/F
1.726	0.000	tNET	FF	1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.426	1.426	tNET	RR	1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2/CLK
1.451	0.025	tHld		1	R29C33[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/EOF_N_DS_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.426, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.426, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.721
Data Required Time	1.446
From	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0
To	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.421	1.421	tNET	RR	1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/CLK
1.562	0.141	tC2Q	RF	4	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/Q
1.568	0.006	tNET	FF	1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_c_s1/I2
1.721	0.153	tINS	FF	1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_c_s1/F
1.721	0.000	tNET	FF	1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
1.421	1.421	tNET	RR	1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0/CLK
1.446	0.025	tHld		1	R30C32[0][A]	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/u_tx_crc/idle_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.421, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.421, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
15.613	-0.278	tSu		1	R4C3[0][A]	u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path2

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_3_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[1][B]	u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[1][B]	u_la0_top/capture_window_sel_3_s1/CLK
15.613	-0.278	tSu		1	R4C3[1][B]	u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path3

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_9_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[1][A]	u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[1][A]	u_la0_top/capture_window_sel_9_s1/CLK
15.613	-0.278	tSu		1	R4C3[1][A]	u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path4

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/start_reg_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[2][A]	u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[2][A]	u_la0_top/start_reg_s0/CLK
15.613	-0.278	tSu		1	R4C3[2][A]	u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path5

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[2][B]	u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[2][B]	u_la0_top/internal_reg_start_dly_0_s0/CLK
15.613	-0.278	tSu		1	R4C3[2][B]	u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path6

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[3][A]	u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[3][A]	u_la0_top/internal_reg_start_dly_1_s0/CLK
15.613	-0.278	tSu		1	R4C3[3][A]	u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path7

Path Summary:

Slack	3.191
Data Arrival Time	12.422
Data Required Time	15.613
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C3[3][B]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.891	3.091	tNET	RR	1	R4C3[3][B]	u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
15.613	-0.278	tSu		1	R4C3[3][B]	u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.356
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.091, 100.000%

Path8

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
15.620	-0.278	tSu		1	R4C4[1][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path9

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
15.620	-0.278	tSu		1	R4C4[1][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path10

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
15.620	-0.278	tSu		1	R4C4[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path11

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
15.620	-0.278	tSu		1	R4C4[2][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path12

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
15.620	-0.278	tSu		1	R4C4[3][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path13

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
15.620	-0.278	tSu		1	R4C4[3][B]	u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path14

Path Summary:

Slack	3.198
Data Arrival Time	12.422
Data Required Time	15.620
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.422	2.933	tNET	FF	1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.898	3.098	tNET	RR	1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
15.620	-0.278	tSu		1	R4C4[0][B]	u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.363
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.933, 89.230%; tC2Q: 0.354, 10.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.098, 100.000%

Path15

Path Summary:

Slack	3.217
Data Arrival Time	12.391
Data Required Time	15.607
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_4_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.391	2.902	tNET	FF	1	R3C2[3][B]	u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.885	3.085	tNET	RR	1	R3C2[3][B]	u_la0_top/capture_window_sel_4_s1/CLK
15.607	-0.278	tSu		1	R3C2[3][B]	u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.350
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.902, 89.127%; tC2Q: 0.354, 10.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.085, 100.000%

Path16

Path Summary:

Slack	3.217
Data Arrival Time	12.391
Data Required Time	15.607
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_6_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.391	2.902	tNET	FF	1	R3C2[3][A]	u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.885	3.085	tNET	RR	1	R3C2[3][A]	u_la0_top/capture_window_sel_6_s1/CLK
15.607	-0.278	tSu		1	R3C2[3][A]	u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.350
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.902, 89.127%; tC2Q: 0.354, 10.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.085, 100.000%

Path17

Path Summary:

Slack	3.217
Data Arrival Time	12.391
Data Required Time	15.607
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_window_sel_7_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.391	2.902	tNET	FF	1	R3C2[2][B]	u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.885	3.085	tNET	RR	1	R3C2[2][B]	u_la0_top/capture_window_sel_7_s1/CLK
15.607	-0.278	tSu		1	R3C2[2][B]	u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.350
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.902, 89.127%; tC2Q: 0.354, 10.873%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.085, 100.000%

Path18

Path Summary:

Slack	3.218
Data Arrival Time	12.385
Data Required Time	15.603
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.385	2.896	tNET	FF	1	R5C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R5C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
15.603	-0.278	tSu		1	R5C2[0][A]	u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.346
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.109%; tC2Q: 0.354, 10.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path19

Path Summary:

Slack	3.218
Data Arrival Time	12.385
Data Required Time	15.603
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.385	2.896	tNET	FF	1	R5C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R5C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
15.603	-0.278	tSu		1	R5C2[0][B]	u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.346
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.109%; tC2Q: 0.354, 10.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path20

Path Summary:

Slack	3.218
Data Arrival Time	12.385
Data Required Time	15.603
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.385	2.896	tNET	FF	1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
15.603	-0.278	tSu		1	R5C2[1][A]	u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.346
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.109%; tC2Q: 0.354, 10.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path21

Path Summary:

Slack	3.218
Data Arrival Time	12.385
Data Required Time	15.603
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.385	2.896	tNET	FF	1	R5C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R5C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
15.603	-0.278	tSu		1	R5C2[1][B]	u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.346
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.109%; tC2Q: 0.354, 10.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path22

Path Summary:

Slack	3.218
Data Arrival Time	12.385
Data Required Time	15.603
From	u_la0_top/rst_ao_s0
To	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.385	2.896	tNET	FF	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.881	3.081	tNET	RR	1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
15.603	-0.278	tSu		1	R5C2[2][A]	u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	0.346
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.896, 89.109%; tC2Q: 0.354, 10.891%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.081, 100.000%

Path23

Path Summary:

Slack	3.222
Data Arrival Time	12.379
Data Required Time	15.601
From	u_la0_top/rst_ao_s0
To	u_la0_top/capture_end_dly_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.379	2.890	tNET	FF	1	R6C2[2][A]	u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.879	3.079	tNET	RR	1	R6C2[2][A]	u_la0_top/capture_end_dly_s0/CLK
15.601	-0.278	tSu		1	R6C2[2][A]	u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.344
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.890, 89.089%; tC2Q: 0.354, 10.911%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.079, 100.000%

Path24

Path Summary:

Slack	3.222
Data Arrival Time	12.379
Data Required Time	15.601
From	u_la0_top/rst_ao_s0
To	u_la0_top/triger_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.379	2.890	tNET	FF	1	R6C2[2][B]	u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.879	3.079	tNET	RR	1	R6C2[2][B]	u_la0_top/triger_s0/CLK
15.601	-0.278	tSu		1	R6C2[2][B]	u_la0_top/triger_s0

Path Statistics:

Clock Skew	0.344
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.890, 89.089%; tC2Q: 0.354, 10.911%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.079, 100.000%

Path25

Path Summary:

Slack	3.222
Data Arrival Time	12.379
Data Required Time	15.601
From	u_la0_top/rst_ao_s0
To	u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	sys_clk:[F]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.400	6.400					active clock edge time
6.400	0.000					sys_clk
6.400	0.000	tCL	FF	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.135	2.735	tNET	FF	1	R4C2[2][A]	u_la0_top/rst_ao_s0/CLK
9.489	0.354	tC2Q	FF	53	R4C2[2][A]	u_la0_top/rst_ao_s0/Q
12.379	2.890	tNET	FF	1	R6C2[3][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.800	12.800					active clock edge time
12.800	0.000					sys_clk
12.800	0.000	tCL	RR	2211	R0C38	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
15.879	3.079	tNET	RR	1	R6C2[3][A]	u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
15.601	-0.278	tSu		1	R6C2[3][A]	u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.344
Setup Relationship	6.400
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.735, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.890, 89.089%; tC2Q: 0.354, 10.911%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.079, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.385
Data Arrival Time	1.778
Data Required Time	1.393
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_10_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.778	0.201	tNET	RR	1	R17C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.446	1.446	tNET	RR	1	R17C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_10_s0/CLK
1.393	-0.053	tHld		1	R17C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_10_s0

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%

Path2

Path Summary:

Slack	0.385
Data Arrival Time	1.778
Data Required Time	1.393
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.778	0.201	tNET	RR	1	R17C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.446	1.446	tNET	RR	1	R17C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLK
1.393	-0.053	tHld		1	R17C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%

Path3

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLK
1.382	-0.053	tHld		1	R14C41[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path4

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLK
1.382	-0.053	tHld		1	R14C41[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path5

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLK
1.382	-0.053	tHld		1	R14C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path6

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLK
1.382	-0.053	tHld		1	R14C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path7

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLK
1.382	-0.053	tHld		1	R14C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path8

Path Summary:

Slack	0.398
Data Arrival Time	1.780
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.780	0.203	tNET	RR	1	R14C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R14C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLK
1.382	-0.053	tHld		1	R14C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.203, 58.501%; tC2Q: 0.144, 41.499%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path9

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLK
1.382	-0.053	tHld		1	R13C40[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path10

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLK
1.382	-0.053	tHld		1	R13C40[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path11

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLK
1.382	-0.053	tHld		1	R13C40[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path12

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLK
1.382	-0.053	tHld		1	R13C40[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path13

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLK
1.382	-0.053	tHld		1	R13C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path14

Path Summary:

Slack	0.400
Data Arrival Time	1.782
Data Required Time	1.382
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.782	0.205	tNET	RR	1	R13C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.435	1.435	tNET	RR	1	R13C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLK
1.382	-0.053	tHld		1	R13C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.205, 58.739%; tC2Q: 0.144, 41.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path15

Path Summary:

Slack	0.416
Data Arrival Time	1.825
Data Required Time	1.409
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.462	1.462	tNET	RR	1	R6C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1/CLK
1.409	-0.053	tHld		1	R6C40[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_0_s1

Path Statistics:

Clock Skew	0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path16

Path Summary:

Slack	0.416
Data Arrival Time	1.825
Data Required Time	1.409
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_4_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.462	1.462	tNET	RR	1	R6C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_4_s1/CLK
1.409	-0.053	tHld		1	R6C40[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_4_s1

Path Statistics:

Clock Skew	0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path17

Path Summary:

Slack	0.416
Data Arrival Time	1.825
Data Required Time	1.409
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_5_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C40[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.462	1.462	tNET	RR	1	R6C40[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_5_s0/CLK
1.409	-0.053	tHld		1	R6C40[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tb_delay_5_s0

Path Statistics:

Clock Skew	0.029
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path18

Path Summary:

Slack	0.420
Data Arrival Time	1.825
Data Required Time	1.405
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.458	1.458	tNET	RR	1	R6C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0/CLK
1.405	-0.053	tHld		1	R6C41[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_3_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path19

Path Summary:

Slack	0.420
Data Arrival Time	1.825
Data Required Time	1.405
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.458	1.458	tNET	RR	1	R6C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0/CLK
1.405	-0.053	tHld		1	R6C41[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_0_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path20

Path Summary:

Slack	0.420
Data Arrival Time	1.825
Data Required Time	1.405
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.458	1.458	tNET	RR	1	R6C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0/CLK
1.405	-0.053	tHld		1	R6C41[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_1_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path21

Path Summary:

Slack	0.420
Data Arrival Time	1.825
Data Required Time	1.405
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.825	0.248	tNET	RR	1	R6C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.458	1.458	tNET	RR	1	R6C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0/CLK
1.405	-0.053	tHld		1	R6C41[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/fsm_st_curr_2_s0

Path Statistics:

Clock Skew	0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 63.265%; tC2Q: 0.144, 36.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.458, 100.000%

Path22

Path Summary:

Slack	0.465
Data Arrival Time	1.855
Data Required Time	1.390
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_19_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.855	0.278	tNET	RR	1	R15C46[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_19_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.443	1.443	tNET	RR	1	R15C46[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_19_s0/CLK
1.390	-0.053	tHld		1	R15C46[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_19_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.278, 65.877%; tC2Q: 0.144, 34.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%

Path23

Path Summary:

Slack	0.465
Data Arrival Time	1.855
Data Required Time	1.390
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_20_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.855	0.278	tNET	RR	1	R15C46[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_20_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.443	1.443	tNET	RR	1	R15C46[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_20_s0/CLK
1.390	-0.053	tHld		1	R15C46[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_20_s0

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.278, 65.877%; tC2Q: 0.144, 34.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%

Path24

Path Summary:

Slack	0.469
Data Arrival Time	1.855
Data Required Time	1.386
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_15_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.855	0.278	tNET	RR	1	R15C45[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.439	1.439	tNET	RR	1	R15C45[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_15_s0/CLK
1.386	-0.053	tHld		1	R15C45[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_15_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.278, 65.877%; tC2Q: 0.144, 34.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path25

Path Summary:

Slack	0.469
Data Arrival Time	1.855
Data Required Time	1.386
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.433	1.433	tNET	RR	1	R15C39[1][A]	u1_reset_gen/o_rst1_s1/CLK
1.577	0.144	tC2Q	RR	441	R15C39[1][A]	u1_reset_gen/o_rst1_s1/Q
1.855	0.278	tNET	RR	1	R15C45[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2079	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.439	1.439	tNET	RR	1	R15C45[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0/CLK
1.386	-0.053	tHld		1	R15C45[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_27_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.278, 65.877%; tC2Q: 0.144, 34.123%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	4.199
Actual Width:	5.061
Required Width:	0.862
Type:	High Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.067	3.067	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.128	1.728	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW2

MPW Summary:

Slack:	4.199
Actual Width:	5.061
Required Width:	0.862
Type:	High Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.067	3.067	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.128	1.728	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW3

MPW Summary:

Slack:	4.202
Actual Width:	5.064
Required Width:	0.862
Type:	High Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.060	3.060	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.124	1.724	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	4.202
Actual Width:	5.064
Required Width:	0.862
Type:	High Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.060	3.060	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.124	1.724	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack:	4.251
Actual Width:	5.113
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.118	2.718	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.800	0.000			active clock edge time
12.800	0.000			sys_clk
12.800	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
14.231	1.431	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW6

MPW Summary:

Slack:	4.251
Actual Width:	5.113
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.118	2.718	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.800	0.000			active clock edge time
12.800	0.000			sys_clk
12.800	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
14.231	1.431	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW7

MPW Summary:

Slack:	4.254
Actual Width:	5.116
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.111	2.711	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.800	0.000			active clock edge time
12.800	0.000			sys_clk
12.800	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
14.227	1.427	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	4.254
Actual Width:	5.116
Required Width:	0.862
Type:	Low Pulse Width
Clock:	sys_clk
Objects:	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
9.111	2.711	tNET	FF	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.800	0.000			active clock edge time
12.800	0.000			sys_clk
12.800	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
14.227	1.427	tNET	RR	u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW9

MPW Summary:

Slack:	4.790
Actual Width:	4.990
Required Width:	0.200
Type:	High Pulse Width
Clock:	sys_clk
Objects:	crc_err_count_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.180	3.180	tNET	RR	crc_err_count_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.170	1.770	tNET	FF	crc_err_count_6_s0/CLK

MPW10

MPW Summary:

Slack:	4.790
Actual Width:	4.990
Required Width:	0.200
Type:	High Pulse Width
Clock:	sys_clk
Objects:	crc_err_count_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
3.180	3.180	tNET	RR	crc_err_count_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.400	0.000			active clock edge time
6.400	0.000			sys_clk
6.400	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst0/LANE0_PCS_TX_O_FABRIC_CLK
8.170	1.770	tNET	FF	crc_err_count_5_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2211	sys_clk	3.833	3.186
2079	cfg_clk	9.049	3.188
441	cfg_rst	14.685	4.821
252	sys_reset	8.851	2.218
196	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_ptr[2]	16.107	2.142
192	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_ptr[2]	15.485	2.630
121	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/tx_dst_rdy_crc	8.240	1.709
101	u_SerDes_Top/RoraLink_8B10B_Top_inst/u_RoraLink_8B10B_Core/rx_rem_crc[0]	7.942	1.546
98	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_ptr[1]	15.431	3.118
96	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_ptr[1]	14.966	3.409

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R16C32	62.50%
R25C24	62.50%
R33C36	62.50%
R35C53	61.11%
R34C54	58.33%
R33C37	58.33%
R35C54	56.94%
R32C36	56.94%
R23C24	55.56%
R24C24	55.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name osc_clk_i -period 20 -waveform {0 10} [get_ports {osc_clk_i}]
TC_CLOCK	Actived	create_clock -name cfg_clk -period 20 -waveform {0 10} [get_nets {cfg_clk}]
TC_CLOCK	Actived	create_clock -name sys_clk -period 12.8 -waveform {0 6.4} [get_nets {sys_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {cfg_clk}] -group [get_clocks {sys_clk}]