Hierarchy Module Resource
| MODULE NAME | REG NUMBER | ALU NUMBER | LUT NUMBER | DSP NUMBER | BSRAM NUMBER | SSRAM NUMBER | ROM16 NUMBER |
|---|---|---|---|---|---|---|---|
| top (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 50 | 42 | 33 | - | - | - | - | |--u_Gowin_PLL (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | - | - | - | - | - | - | - | |--u1_reset_gen (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 13 | 11 | 6 | - | - | - | - | |--u2_reset_gen (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 13 | 11 | 6 | - | - | - | - | |--u_uart_bus_top (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 1439 | 40 | 952 | - | - | - | - | |--u_apb2local (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | - | - | 35 | - | - | - | - | |--u_local2reg (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 547 | - | 485 | - | - | - | - | |--u_SerDes_Top (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | - | - | - | - | - | - | - | |--RoraLink_8B10B_Top_inst (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/serdes/serdes.v) | 1776 | 79 | 1695 | - | - | - | - | |--u_data_ll_to_axi_reg (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | - | - | 4 | - | - | - | - | |--u_frame_gen (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 81 | 27 | 66 | - | - | - | - | |--u_data_axi_to_ll_reg (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 38 | - | 6 | - | - | - | - | |--u_frame_check (F:/138k_serdes/20251230/Gowin_RoraLink_8B10B_RefDesign/fpga_project/src/top.v) | 129 | 40 | 65 | - | - | - | - |