Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\apb2local.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\axi_to_ll_reg.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\frame_check.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\frame_gen.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\gowin_pll\gowin_pll.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\ll_to_axi_reg.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\local2reg.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\reset_gen.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\serdes\roralink_8b10b\roralink_8b10b.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\serdes\serdes.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\top.v F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\uart_to_bus\uart_to_bus.v |
| GowinSynthesis Constraints File | F:\138k_serdes\20251230\Gowin_RoraLink_8B10B_RefDesign\fpga_project\src\top.gsc |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:27:46 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.76s, Peak memory usage = 332.465MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.24s, Peak memory usage = 332.465MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 332.465MB Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 332.465MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.174s, Peak memory usage = 332.465MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 332.465MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 332.465MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 332.465MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.163s, Peak memory usage = 332.465MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 332.465MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 332.465MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 341.918MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.196s, Peak memory usage = 342.184MB Generate output files: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.274s, Peak memory usage = 354.230MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 4s, Peak memory usage = 354.230MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 14 |
| I/O Buf | 14 |
| IBUF | 3 |
| OBUF | 11 |
| Register | 4086 |
| DFFSE | 258 |
| DFFRE | 2383 |
| DFFPE | 9 |
| DFFCE | 1436 |
| LUT | 3250 |
| LUT2 | 288 |
| LUT3 | 1150 |
| LUT4 | 1812 |
| ALU | 250 |
| ALU | 250 |
| INV | 103 |
| INV | 103 |
| CLOCK | 1 |
| PLL | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3603(3353 LUT, 250 ALU) / 138240 | 3% |
| Register | 4086 / 139140 | 3% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 4086 / 139140 | 3% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | osc_clk_i | Base | 20.000 | 50.000 | 0.000 | 10.000 | osc_clk_i_ibuf/I | ||
| 2 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | osc_clk_i_ibuf/I | osc_clk_i | u_Gowin_PLL/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 147.471(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 13.219 |
| Data Arrival Time | 7.319 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
| To | u_local2reg/local_rdat_o_26_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 2 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/I1 |
| 2.472 | 0.454 | tINS | RR | 44 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 2.802 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/I3 |
| 3.033 | 0.231 | tINS | RR | 45 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/F |
| 3.363 | 0.330 | tNET | RR | 1 | u_local2reg/n2481_s1/I0 |
| 3.826 | 0.463 | tINS | RR | 49 | u_local2reg/n2481_s1/F |
| 4.156 | 0.330 | tNET | RR | 1 | u_local2reg/n1770_s42/I0 |
| 4.619 | 0.463 | tINS | RR | 1 | u_local2reg/n1770_s42/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1770_s39/I0 |
| 5.412 | 0.463 | tINS | RR | 1 | u_local2reg/n1770_s39/F |
| 5.742 | 0.330 | tNET | RR | 1 | u_local2reg/n1770_s36/I1 |
| 6.196 | 0.454 | tINS | RR | 1 | u_local2reg/n1770_s36/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1770_s35/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1770_s35/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_26_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_26_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_26_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.454, 51.322%; route: 2.970, 44.131%; tC2Q: 0.306, 4.547% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 2
Path Summary:| Slack | 13.267 |
| Data Arrival Time | 7.271 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
| To | u_local2reg/local_rdat_o_4_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 2 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/I1 |
| 2.472 | 0.454 | tINS | RR | 44 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 2.802 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/I3 |
| 3.033 | 0.231 | tINS | RR | 45 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/F |
| 3.363 | 0.330 | tNET | RR | 1 | u_local2reg/n2545_s1/I0 |
| 3.826 | 0.463 | tINS | RR | 28 | u_local2reg/n2545_s1/F |
| 4.156 | 0.330 | tNET | RR | 1 | u_local2reg/n1792_s45/I0 |
| 4.619 | 0.463 | tINS | RR | 1 | u_local2reg/n1792_s45/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1792_s39/I2 |
| 5.355 | 0.406 | tINS | RR | 1 | u_local2reg/n1792_s39/F |
| 5.685 | 0.330 | tNET | RR | 1 | u_local2reg/n1792_s36/I0 |
| 6.148 | 0.463 | tINS | RR | 1 | u_local2reg/n1792_s36/F |
| 6.478 | 0.330 | tNET | RR | 1 | u_local2reg/n1792_s35/I0 |
| 6.941 | 0.463 | tINS | RR | 1 | u_local2reg/n1792_s35/F |
| 7.271 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_4_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.406, 50.973%; route: 2.970, 44.448%; tC2Q: 0.306, 4.579% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 3
Path Summary:| Slack | 13.267 |
| Data Arrival Time | 7.271 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
| To | u_local2reg/local_rdat_o_5_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 2 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/I1 |
| 2.472 | 0.454 | tINS | RR | 44 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 2.802 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_4_s0/I3 |
| 3.033 | 0.231 | tINS | RR | 40 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_4_s0/F |
| 3.363 | 0.330 | tNET | RR | 1 | u_local2reg/n2769_s1/I0 |
| 3.826 | 0.463 | tINS | RR | 24 | u_local2reg/n2769_s1/F |
| 4.156 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s50/I0 |
| 4.619 | 0.463 | tINS | RR | 6 | u_local2reg/n1765_s50/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s39/I0 |
| 5.412 | 0.463 | tINS | RR | 1 | u_local2reg/n1791_s39/F |
| 5.742 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s37/I0 |
| 6.205 | 0.463 | tINS | RR | 1 | u_local2reg/n1791_s37/F |
| 6.535 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s35/I2 |
| 6.941 | 0.406 | tINS | RR | 1 | u_local2reg/n1791_s35/F |
| 7.271 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_5_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.406, 50.973%; route: 2.970, 44.448%; tC2Q: 0.306, 4.579% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 4
Path Summary:| Slack | 13.267 |
| Data Arrival Time | 7.271 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
| To | u_local2reg/local_rdat_o_10_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 2 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/I1 |
| 2.472 | 0.454 | tINS | RR | 44 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 2.802 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/I3 |
| 3.033 | 0.231 | tINS | RR | 45 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_2_s0/F |
| 3.363 | 0.330 | tNET | RR | 1 | u_local2reg/n2737_s1/I0 |
| 3.826 | 0.463 | tINS | RR | 22 | u_local2reg/n2737_s1/F |
| 4.156 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s43/I0 |
| 4.619 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s43/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s39/I0 |
| 5.412 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s39/F |
| 5.742 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s36/I2 |
| 6.148 | 0.406 | tINS | RR | 1 | u_local2reg/n1786_s36/F |
| 6.478 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s35/I0 |
| 6.941 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s35/F |
| 7.271 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_10_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.406, 50.973%; route: 2.970, 44.448%; tC2Q: 0.306, 4.579% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 5
Path Summary:| Slack | 13.267 |
| Data Arrival Time | 7.271 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0 |
| To | u_local2reg/local_rdat_o_13_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 2 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_15_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s4/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/I1 |
| 2.472 | 0.454 | tINS | RR | 44 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s1/F |
| 2.802 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_4_s0/I3 |
| 3.033 | 0.231 | tINS | RR | 40 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_4_s0/F |
| 3.363 | 0.330 | tNET | RR | 1 | u_local2reg/n2769_s1/I0 |
| 3.826 | 0.463 | tINS | RR | 24 | u_local2reg/n2769_s1/F |
| 4.156 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s50/I0 |
| 4.619 | 0.463 | tINS | RR | 6 | u_local2reg/n1765_s50/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1783_s41/I0 |
| 5.412 | 0.463 | tINS | RR | 1 | u_local2reg/n1783_s41/F |
| 5.742 | 0.330 | tNET | RR | 1 | u_local2reg/n1783_s37/I0 |
| 6.205 | 0.463 | tINS | RR | 1 | u_local2reg/n1783_s37/F |
| 6.535 | 0.330 | tNET | RR | 1 | u_local2reg/n1783_s35/I2 |
| 6.941 | 0.406 | tINS | RR | 1 | u_local2reg/n1783_s35/F |
| 7.271 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_13_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2079 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_13_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_13_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.406, 50.973%; route: 2.970, 44.448%; tC2Q: 0.306, 4.579% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |