Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v
C:\Gowin\Gowin_V1.9.11.01_x64\IDE\data\ipcores\gw_jtag.v
E:\gowin_prj\RoraLink_8b10b\Gowin_RoraLink_ 8B10B_RefDesign\fpga_project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Tue Mar 4 09:59:31 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.302s, Peak memory usage = 119.789MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 119.789MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 119.789MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 119.789MB
    Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 119.789MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 119.789MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 119.789MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 119.789MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 119.789MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 119.789MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 119.789MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 119.789MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 145.453MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 145.453MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 145.453MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 145.453MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 74
I/O Buf 74
    IBUF 73
    OBUF 1
Register 513
    DFFRE 1
    DFFPE 36
    DFFCE 476
LUT 468
    LUT2 47
    LUT3 125
    LUT4 296
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 4
    SDPX9B 4
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 493(480 LUT, 13 ALU) / 138240 <1%
Register 513 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 513 / 139140 <1%
BSRAM 4 / 340 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 sys_clk Base 10.000 100.000 0.000 5.000 sys_clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 100.000(MHz) 220.799(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.471
Data Arrival Time 4.808
Data Required Time 10.279
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.000 0.000 tINS RR 202 sys_clk_ibuf/O
0.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.636 0.306 tC2Q RR 10 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
0.966 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n555_s2/I0
1.429 0.463 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n555_s2/F
1.759 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n553_s2/I2
2.165 0.406 tINS RR 3 u_la0_top/u_ao_mem_ctrl/n553_s2/F
2.495 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n551_s2/I2
2.901 0.406 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n551_s2/F
3.231 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s3/I1
3.685 0.454 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s3/F
4.015 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s2/I0
4.478 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s2/F
4.808 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.000 0.000 tINS RR 202 sys_clk_ibuf/O
10.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.279 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%
Arrival Data Path Delay: cell: 2.192, 48.951%; route: 1.980, 44.216%; tC2Q: 0.306, 6.833%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%

Path 2

Path Summary:
Slack 5.952
Data Arrival Time 4.129
Data Required Time 10.081
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.000 0.000 tINS RR 202 sys_clk_ibuf/O
0.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.636 0.306 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.966 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/I0
1.429 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/F
1.759 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s5/I1
2.213 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n550_s5/F
2.543 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s4/I0
3.006 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n550_s4/F
3.336 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
3.799 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.129 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.000 0.000 tINS RR 202 sys_clk_ibuf/O
10.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.081 -0.249 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%
Arrival Data Path Delay: cell: 1.843, 48.513%; route: 1.650, 43.432%; tC2Q: 0.306, 8.055%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%

Path 3

Path Summary:
Slack 6.207
Data Arrival Time 4.072
Data Required Time 10.279
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.000 0.000 tINS RR 202 sys_clk_ibuf/O
0.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.636 0.306 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.966 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/I0
1.429 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/F
1.759 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s5/I1
2.213 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n550_s5/F
2.543 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s4/I0
3.006 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n550_s4/F
3.336 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n558_s1/I2
3.742 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n558_s1/F
4.072 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.000 0.000 tINS RR 202 sys_clk_ibuf/O
10.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.279 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%
Arrival Data Path Delay: cell: 1.786, 47.729%; route: 1.650, 44.094%; tC2Q: 0.306, 8.177%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%

Path 4

Path Summary:
Slack 6.207
Data Arrival Time 4.072
Data Required Time 10.279
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.000 0.000 tINS RR 202 sys_clk_ibuf/O
0.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.636 0.306 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.966 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/I0
1.429 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/F
1.759 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s5/I1
2.213 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n550_s5/F
2.543 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s4/I0
3.006 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n550_s4/F
3.336 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n556_s1/I2
3.742 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n556_s1/F
4.072 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.000 0.000 tINS RR 202 sys_clk_ibuf/O
10.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.279 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%
Arrival Data Path Delay: cell: 1.786, 47.729%; route: 1.650, 44.094%; tC2Q: 0.306, 8.177%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%

Path 5

Path Summary:
Slack 6.207
Data Arrival Time 4.072
Data Required Time 10.279
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk sys_clk[R]
Latch Clk sys_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 sys_clk_ibuf/I
0.000 0.000 tINS RR 202 sys_clk_ibuf/O
0.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.636 0.306 tC2Q RR 8 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
0.966 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/I0
1.429 0.463 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n550_s8/F
1.759 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s5/I1
2.213 0.454 tINS RR 2 u_la0_top/u_ao_mem_ctrl/n550_s5/F
2.543 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n550_s4/I0
3.006 0.463 tINS RR 10 u_la0_top/u_ao_mem_ctrl/n550_s4/F
3.336 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/n552_s1/I2
3.742 0.406 tINS RR 1 u_la0_top/u_ao_mem_ctrl/n552_s1/F
4.072 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 sys_clk
10.000 0.000 tCL RR 1 sys_clk_ibuf/I
10.000 0.000 tINS RR 202 sys_clk_ibuf/O
10.330 0.330 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.279 -0.051 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%
Arrival Data Path Delay: cell: 1.786, 47.729%; route: 1.650, 44.094%; tC2Q: 0.306, 8.177%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.330, 100.000%