#Build: Synplify Pro (R) P-2019.09G-1, Build 284R, Feb 28 2020 #install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: NOA-PC # Wed May 20 01:53:28 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_parameter.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top_define.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top.v" (library work) @W:CG1337 : gw_con_top.v(194) | Net capture_dr is not declared. @W:CG1337 : gw_con_top.v(211) | Net enable_i_delay is not declared. Verilog syntax check successful! @N:CG364 : gw_con_parameter.v(1) | Synthesizing module work_C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_parameter.v_unit in library work. Selecting top level module gw_con_top Running optimization stage 1 on gw_con_top ....... Running optimization stage 2 on gw_con_top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 88MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:53:30 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 86MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:53:30 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ao_control_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 18MB peak: 18MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:53:31 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:53:32 2020 ###########################################################] Premap Report # Wed May 20 01:53:32 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @A:MF827 : | No constraint file specified. Linked File: ao_control_scck.rpt See clock summary report "C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_control\rev_1\ao_control_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 128MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 128MB peak: 129MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 129MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB) Starting clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 221MB) Finished clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 221MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 221MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 221MB) Finished netlist restructuring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 221MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------- 0 - gw_con_top|tck_i 297.4 MHz 3.362 inferred Autoconstr_clkgroup_0 14 ======================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------- gw_con_top|tck_i 14 tck_i(port) shift_dr_capture_dr_dly[0].C - un1_tck_i.I[0](inv) ===================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 14 clock pin(s) of sequential element(s) 0 instances converted, 14 sequential instances remain driven by gated/generated clocks ======================================================= Gated/Generated Clocks ======================================================== Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_0 ENCRYPTED IO_port 14 ENCRYPTED Clock source is invalid for GCC ======================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_control\rev_1\ao_control.sap. Starting constraint checker (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 222MB peak: 222MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 222MB peak: 222MB) Finished constraint checker (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 222MB peak: 222MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 143MB peak: 224MB) Process took 0h:00m:13s realtime, 0h:00m:13s cputime # Wed May 20 01:53:46 2020 ###########################################################] Map & Optimize Report # Wed May 20 01:53:46 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 120MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 123MB peak: 128MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 136MB peak: 138MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 218MB peak: 218MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 221MB peak: 221MB) Starting factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 222MB peak: 222MB) Finished factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 222MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 223MB peak: 223MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s -1.33ns 18 / 14 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 223MB peak: 223MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 224MB peak: 224MB) Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 152MB peak: 224MB) Writing Analyst data base C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_control\rev_1\synwork\ao_control_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 224MB peak: 224MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 225MB peak: 225MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 225MB peak: 225MB) Start final timing analysis (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 224MB peak: 225MB) @W:MT420 : | Found inferred clock gw_con_top|tck_i with period 1.65ns. Please declare a user-defined clock on port tck_i. ##### START OF TIMING REPORT #####[ # Timing report written on Wed May 20 01:54:11 2020 # Top view: gw_con_top Requested Frequency: 605.2 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.118 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------- gw_con_top|tck_i 605.2 MHz 257.2 MHz 1.652 3.888 -1.118 inferred Autoconstr_clkgroup_0 System 150.0 MHz NA 6.667 NA NA system system_clkgroup ========================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------- gw_con_top|tck_i gw_con_top|tck_i | 1.652 0.243 | 1.652 0.813 | No paths - | 0.826 -1.118 =========================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: gw_con_top|tck_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------- enable_reg[1] gw_con_top|tck_i DFFNC Q enable_reg[1] 0.243 -1.118 enable_reg[0] gw_con_top|tck_i DFFNC Q enable_reg[0] 0.243 -1.097 enable_reg[2] gw_con_top|tck_i DFFNC Q enable_reg[2] 0.243 -1.010 tdi_d gw_con_top|tck_i DFFNC Q control0_c[2] 0.243 -0.562 input_shift_reg[0] gw_con_top|tck_i DFFCE Q input_shift_reg[0] 0.243 0.243 input_shift_reg[1] gw_con_top|tck_i DFFCE Q input_shift_reg[1] 0.243 0.243 input_shift_reg[2] gw_con_top|tck_i DFFCE Q input_shift_reg[2] 0.243 0.243 input_shift_reg[3] gw_con_top|tck_i DFFCE Q input_shift_reg[3] 0.243 0.243 input_shift_reg[4] gw_con_top|tck_i DFFCE Q input_shift_reg[4] 0.243 0.243 shift_dr_capture_dr_dly[0] gw_con_top|tck_i DFFC Q control0_c[4] 0.243 0.243 =============================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- input_shift_reg[0] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 input_shift_reg[1] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 input_shift_reg[2] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 input_shift_reg[3] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 input_shift_reg[4] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 module_id_reg[0] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 module_id_reg[1] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 module_id_reg[2] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 module_id_reg[3] gw_con_top|tck_i DFFCE CE enable_i_delay 0.765 -1.118 input_shift_reg[4] gw_con_top|tck_i DFFCE D input_shift_reg_ldmx[4] 0.765 -0.562 ============================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.826 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.765 - Propagation time: 1.883 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.118 Number of logic level(s): 1 Starting point: enable_reg[1] / Q Ending point: input_shift_reg[0] / CE The start point is clocked by gw_con_top|tck_i [falling] on pin CLK The end point is clocked by gw_con_top|tck_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- enable_reg[1] DFFNC Q Out 0.243 0.243 - enable_reg[1] Net - - 0.535 - 2 enable_i_delay LUT3 I1 In - 0.778 - enable_i_delay LUT3 F Out 0.570 1.348 - enable_i_delay Net - - 0.535 - 9 input_shift_reg[0] DFFCE CE In - 1.883 - ================================================================================== Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.826 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.765 - Propagation time: 1.883 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.118 Number of logic level(s): 1 Starting point: enable_reg[1] / Q Ending point: module_id_reg[0] / CE The start point is clocked by gw_con_top|tck_i [falling] on pin CLK The end point is clocked by gw_con_top|tck_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------- enable_reg[1] DFFNC Q Out 0.243 0.243 - enable_reg[1] Net - - 0.535 - 2 enable_i_delay LUT3 I1 In - 0.778 - enable_i_delay LUT3 F Out 0.570 1.348 - enable_i_delay Net - - 0.535 - 9 module_id_reg[0] DFFCE CE In - 1.883 - ================================================================================ Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 0.826 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.765 - Propagation time: 1.883 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.118 Number of logic level(s): 1 Starting point: enable_reg[1] / Q Ending point: module_id_reg[1] / CE The start point is clocked by gw_con_top|tck_i [falling] on pin CLK The end point is clocked by gw_con_top|tck_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------- enable_reg[1] DFFNC Q Out 0.243 0.243 - enable_reg[1] Net - - 0.535 - 2 enable_i_delay LUT3 I1 In - 0.778 - enable_i_delay LUT3 F Out 0.570 1.348 - enable_i_delay Net - - 0.535 - 9 module_id_reg[1] DFFCE CE In - 1.883 - ================================================================================ Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 0.826 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.765 - Propagation time: 1.883 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.118 Number of logic level(s): 1 Starting point: enable_reg[1] / Q Ending point: module_id_reg[2] / CE The start point is clocked by gw_con_top|tck_i [falling] on pin CLK The end point is clocked by gw_con_top|tck_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------- enable_reg[1] DFFNC Q Out 0.243 0.243 - enable_reg[1] Net - - 0.535 - 2 enable_i_delay LUT3 I1 In - 0.778 - enable_i_delay LUT3 F Out 0.570 1.348 - enable_i_delay Net - - 0.535 - 9 module_id_reg[2] DFFCE CE In - 1.883 - ================================================================================ Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 0.826 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.765 - Propagation time: 1.883 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.118 Number of logic level(s): 1 Starting point: enable_reg[1] / Q Ending point: module_id_reg[3] / CE The start point is clocked by gw_con_top|tck_i [falling] on pin CLK The end point is clocked by gw_con_top|tck_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------- enable_reg[1] DFFNC Q Out 0.243 0.243 - enable_reg[1] Net - - 0.535 - 2 enable_i_delay LUT3 I1 In - 0.778 - enable_i_delay LUT3 F Out 0.570 1.348 - enable_i_delay Net - - 0.535 - 9 module_id_reg[3] DFFCE CE In - 1.883 - ================================================================================ Total path delay (propagation time + setup) of 1.944 is 0.874(45.0%) logic and 1.070(55.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 225MB peak: 225MB) Finished timing report (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 225MB peak: 225MB) --------------------------------------- Resource Usage Report for gw_con_top Mapping to part: gw2a_18pbga256-8 Cell usage: DFFC 1 use DFFCE 9 uses DFFNC 4 uses GSR 1 use INV 1 use LUT2 3 uses LUT3 6 uses LUT4 5 uses I/O ports: 17 I/O primitives: 17 IBUF 8 uses OBUF 9 uses I/O Register bits: 0 Register bits not including I/Os: 14 of 15552 (0%) Total load per clock: gw_con_top|tck_i: 15 @S |Mapping Summary: Total LUTs: 14 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 73MB peak: 225MB) Process took 0h:00m:25s realtime, 0h:00m:25s cputime # Wed May 20 01:54:11 2020 ###########################################################]