Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_18
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 1 0 - 00m:04s - 5/20/2020
1:54:20 AM
(premap)Complete 6 0 0 0m:13s 0m:13s 226MB 5/20/2020
1:54:35 AM
(fpga_mapper)Complete 9 2 0 0m:31s 0m:31s 235MB 5/20/2020
1:55:07 AM
Multi-srs Generator Complete5/20/2020
1:54:21 AM

Area Summary
I/O ports (io_port) 62 Non I/O Register bits (non_io_reg) 220 (1%)
I/O Register bits (total_io_reg) 0 Ultra Rams 0
Block Rams (v_ram) 3 (46) Block Multipliers (dsp_used) 0 (24)
LUTs (total_luts) 197 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top|clk_i362.8 MHz308.4 MHz-0.486
ao_top|control[0]212.3 MHz180.5 MHz-0.831
System150.0 MHz197.8 MHz1.612

Optimizations Summary
Combined Clock Conversion 2 / 0