#Build: Synplify Pro (R) P-2019.09G-1, Build 284R, Feb 28 2020 #install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: NOA-PC # Wed May 20 01:54:16 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_define.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(104) | Net capture_length_zero is not declared. @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_top.v" (library work) Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top Running optimization stage 1 on ao_mem_ctrl_1024s_51s_10s ....... Running optimization stage 1 on ao_top ....... Running optimization stage 2 on ao_top ....... Extracted state machine for register module_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 Running optimization stage 2 on ao_mem_ctrl_1024s_51s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 94MB peak: 103MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime Process completed successfully. # Wed May 20 01:54:19 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:54:20 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ao_0_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 18MB peak: 18MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Wed May 20 01:54:20 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed May 20 01:54:21 2020 ###########################################################] Premap Report # Wed May 20 01:54:22 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A:MF827 : | No constraint file specified. Linked File: ao_0_scck.rpt See clock summary report "C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\rev_1\ao_0_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 128MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 128MB peak: 128MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 129MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 142MB) Encoding state machine module_state[5:0] (in view: work.ao_top(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0011 -> 001000 0100 -> 010000 0101 -> 100000 Starting clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 222MB peak: 222MB) Finished clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 223MB peak: 223MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 223MB peak: 223MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 223MB peak: 223MB) Finished netlist restructuring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 224MB peak: 224MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------- 0 - ao_top|control[0] 213.2 MHz 4.690 inferred Autoconstr_clkgroup_1 255 0 - ao_top|clk_i 347.5 MHz 2.878 inferred Autoconstr_clkgroup_0 73 ======================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------------------------------------- ao_top|control[0] 255 control[0](port) data_register[71:0].C - - ao_top|clk_i 73 clk_i(port) internal_reg_start_syn[1:0].C - clk_ao.I[0](keepbuf) ============================================================================================================================= ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 278 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 ENCRYPTED port 23 ENCRYPTED ClockId_0_1 ENCRYPTED IO_port 255 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\rev_1\ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 224MB peak: 224MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 224MB peak: 224MB) Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 225MB peak: 225MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 145MB peak: 226MB) Process took 0h:00m:13s realtime, 0h:00m:13s cputime # Wed May 20 01:54:35 2020 ###########################################################] Map & Optimize Report # Wed May 20 01:54:35 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 124MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 137MB peak: 139MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 219MB peak: 219MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 224MB peak: 224MB) Starting factoring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 226MB peak: 226MB) Finished factoring (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 229MB peak: 229MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 229MB peak: 229MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 230MB peak: 230MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 230MB peak: 230MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 230MB peak: 230MB) Finished preparing to map (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 230MB peak: 230MB) Finished technology mapping (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 233MB peak: 233MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:11s -2.44ns 228 / 220 2 0h:00m:11s -2.16ns 226 / 220 3 0h:00m:11s -2.16ns 226 / 220 4 0h:00m:11s -2.16ns 227 / 220 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 233MB peak: 233MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 234MB peak: 234MB) Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 161MB peak: 234MB) Writing Analyst data base C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 234MB peak: 234MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 234MB peak: 234MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 235MB peak: 235MB) Start final timing analysis (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:31s; Memory used current: 233MB peak: 235MB) @W:MT420 : | Found inferred clock ao_top|clk_i with period 2.76ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top|control[0] with period 4.71ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing report written on Wed May 20 01:55:07 2020 # Top view: ao_top Requested Frequency: 212.3 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.831 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------- ao_top|clk_i 362.8 MHz 308.4 MHz 2.757 3.243 -0.486 inferred Autoconstr_clkgroup_0 ao_top|control[0] 212.3 MHz 180.5 MHz 4.710 5.541 -0.831 inferred Autoconstr_clkgroup_1 System 150.0 MHz 197.8 MHz 6.667 5.055 1.612 system system_clkgroup =========================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------- System ao_top|clk_i | 2.757 1.612 | No paths - | No paths - | No paths - System ao_top|control[0] | 4.710 2.794 | No paths - | No paths - | No paths - ao_top|clk_i System | 2.757 1.979 | No paths - | No paths - | No paths - ao_top|clk_i ao_top|clk_i | 2.757 -0.486 | 2.757 1.918 | No paths - | 1.378 0.539 ao_top|clk_i ao_top|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top|control[0] System | 4.710 3.749 | No paths - | No paths - | No paths - ao_top|control[0] ao_top|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top|control[0] ao_top|control[0] | 4.710 -0.831 | No paths - | No paths - | No paths - ============================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[0] ao_top|clk_i DFFCE Q capture_mem_addr[0] 0.243 -0.486 u_ao_mem_ctrl.capture_mem_addr[4] ao_top|clk_i DFFCE Q capture_mem_addr[4] 0.243 -0.483 u_ao_mem_ctrl.capture_mem_addr[2] ao_top|clk_i DFFCE Q capture_mem_addr[2] 0.243 -0.462 u_ao_mem_ctrl.capture_mem_addr[1] ao_top|clk_i DFFCE Q capture_mem_addr[1] 0.243 -0.451 u_ao_mem_ctrl.capture_mem_addr[3] ao_top|clk_i DFFCE Q capture_mem_addr[3] 0.243 -0.381 u_ao_mem_ctrl.capture_mem_addr[8] ao_top|clk_i DFFCE Q capture_mem_addr[8] 0.243 -0.375 u_ao_mem_ctrl.capture_mem_addr[5] ao_top|clk_i DFFCE Q capture_mem_addr[5] 0.243 -0.375 u_ao_mem_ctrl.capture_mem_addr[6] ao_top|clk_i DFFCE Q capture_mem_addr[6] 0.243 -0.276 u_ao_mem_ctrl.capture_mem_addr[9] ao_top|clk_i DFFCE Q capture_mem_addr[9] 0.243 -0.267 u_ao_mem_ctrl.capture_mem_addr[7] ao_top|clk_i DFFCE Q capture_mem_addr[7] 0.243 -0.241 =================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[9] ao_top|clk_i DFFCE D capture_mem_addr_lm[9] 2.696 -0.486 u_ao_mem_ctrl.capture_mem_wr ao_top|clk_i DFFCE CE un1_start_reg_0 2.696 -0.483 u_ao_mem_ctrl.capture_mem_addr[8] ao_top|clk_i DFFCE D capture_mem_addr_lm[8] 2.696 -0.451 u_ao_mem_ctrl.capture_mem_addr[7] ao_top|clk_i DFFCE D capture_mem_addr_lm[7] 2.696 -0.416 u_ao_mem_ctrl.capture_mem_addr[0] ao_top|clk_i DFFCE D capture_mem_addr_lm[0] 2.696 -0.392 u_ao_mem_ctrl.capture_mem_addr[1] ao_top|clk_i DFFCE D capture_mem_addr_lm[1] 2.696 -0.392 u_ao_mem_ctrl.capture_mem_addr[2] ao_top|clk_i DFFCE D capture_mem_addr_lm[2] 2.696 -0.392 u_ao_mem_ctrl.capture_mem_addr[3] ao_top|clk_i DFFCE D capture_mem_addr_lm[3] 2.696 -0.392 u_ao_mem_ctrl.capture_mem_addr[4] ao_top|clk_i DFFCE D capture_mem_addr_lm[4] 2.696 -0.392 u_ao_mem_ctrl.capture_mem_addr[5] ao_top|clk_i DFFCE D capture_mem_addr_lm[5] 2.696 -0.392 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 3.182 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.486 Number of logic level(s): 11 Starting point: u_ao_mem_ctrl.capture_mem_addr[0] / Q Ending point: u_ao_mem_ctrl.capture_mem_addr[9] / D The start point is clocked by ao_top|clk_i [rising] on pin CLK The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[0] DFFCE Q Out 0.243 0.243 - capture_mem_addr[0] Net - - 0.535 - 6 u_ao_mem_ctrl.capture_mem_addr_cry_0[0] ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_mem_addr_cry_0[0] ALU COUT Out 0.549 1.327 - capture_mem_addr_cry[0] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU COUT Out 0.035 1.362 - capture_mem_addr_cry[1] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU COUT Out 0.035 1.397 - capture_mem_addr_cry[2] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU COUT Out 0.035 1.432 - capture_mem_addr_cry[3] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU COUT Out 0.035 1.467 - capture_mem_addr_cry[4] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU COUT Out 0.035 1.502 - capture_mem_addr_cry[5] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU COUT Out 0.035 1.537 - capture_mem_addr_cry[6] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU COUT Out 0.035 1.572 - capture_mem_addr_cry[7] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU COUT Out 0.035 1.607 - capture_mem_addr_cry[8] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_s_0[9] ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_mem_addr_s_0[9] ALU SUM Out 0.470 2.077 - capture_mem_addr_s[9] Net - - 0.535 - 1 u_ao_mem_ctrl.capture_mem_addr_lm_0[9] LUT4 I1 In - 2.612 - u_ao_mem_ctrl.capture_mem_addr_lm_0[9] LUT4 F Out 0.570 3.182 - capture_mem_addr_lm[9] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr[9] DFFCE D In - 3.182 - ======================================================================================================= Total path delay (propagation time + setup) of 3.243 is 2.173(67.0%) logic and 1.070(33.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 3.178 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.483 Number of logic level(s): 3 Starting point: u_ao_mem_ctrl.capture_mem_addr[4] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top|clk_i [rising] on pin CLK The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[4] DFFCE Q Out 0.243 0.243 - capture_mem_addr[4] Net - - 0.535 - 5 u_ao_mem_ctrl.un1_capture_mem_addr_7_1_0 LUT3 I1 In - 0.778 - u_ao_mem_ctrl.un1_capture_mem_addr_7_1_0 LUT3 F Out 0.570 1.348 - un1_capture_mem_addr_7_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_capture_mem_addr_7 LUT4 I3 In - 1.749 - u_ao_mem_ctrl.un1_capture_mem_addr_7 LUT4 F Out 0.371 2.120 - un1_capture_mem_addr_7 Net - - 0.596 - 12 u_ao_mem_ctrl.un1_start_reg_0 LUT4 I2 In - 2.716 - u_ao_mem_ctrl.un1_start_reg_0 LUT4 F Out 0.462 3.178 - un1_start_reg_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 3.178 - ======================================================================================================== Total path delay (propagation time + setup) of 3.239 is 1.707(52.7%) logic and 1.532(47.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 3.157 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.462 Number of logic level(s): 3 Starting point: u_ao_mem_ctrl.capture_mem_addr[2] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top|clk_i [rising] on pin CLK The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[2] DFFCE Q Out 0.243 0.243 - capture_mem_addr[2] Net - - 0.535 - 5 u_ao_mem_ctrl.un1_capture_mem_addr_7_1_0 LUT3 I0 In - 0.778 - u_ao_mem_ctrl.un1_capture_mem_addr_7_1_0 LUT3 F Out 0.549 1.327 - un1_capture_mem_addr_7_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_capture_mem_addr_7 LUT4 I3 In - 1.728 - u_ao_mem_ctrl.un1_capture_mem_addr_7 LUT4 F Out 0.371 2.099 - un1_capture_mem_addr_7 Net - - 0.596 - 12 u_ao_mem_ctrl.un1_start_reg_0 LUT4 I2 In - 2.695 - u_ao_mem_ctrl.un1_start_reg_0 LUT4 F Out 0.462 3.157 - un1_start_reg_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 3.157 - ======================================================================================================== Total path delay (propagation time + setup) of 3.218 is 1.686(52.4%) logic and 1.532(47.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 3.147 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.451 Number of logic level(s): 10 Starting point: u_ao_mem_ctrl.capture_mem_addr[1] / Q Ending point: u_ao_mem_ctrl.capture_mem_addr[9] / D The start point is clocked by ao_top|clk_i [rising] on pin CLK The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[1] DFFCE Q Out 0.243 0.243 - capture_mem_addr[1] Net - - 0.535 - 6 u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU COUT Out 0.549 1.327 - capture_mem_addr_cry[1] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU COUT Out 0.035 1.362 - capture_mem_addr_cry[2] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU COUT Out 0.035 1.397 - capture_mem_addr_cry[3] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU COUT Out 0.035 1.432 - capture_mem_addr_cry[4] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU COUT Out 0.035 1.467 - capture_mem_addr_cry[5] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU COUT Out 0.035 1.502 - capture_mem_addr_cry[6] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU COUT Out 0.035 1.537 - capture_mem_addr_cry[7] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU COUT Out 0.035 1.572 - capture_mem_addr_cry[8] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_s_0[9] ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_mem_addr_s_0[9] ALU SUM Out 0.470 2.042 - capture_mem_addr_s[9] Net - - 0.535 - 1 u_ao_mem_ctrl.capture_mem_addr_lm_0[9] LUT4 I1 In - 2.577 - u_ao_mem_ctrl.capture_mem_addr_lm_0[9] LUT4 F Out 0.570 3.147 - capture_mem_addr_lm[9] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr[9] DFFCE D In - 3.147 - ======================================================================================================= Total path delay (propagation time + setup) of 3.208 is 2.138(66.6%) logic and 1.070(33.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 3.147 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.451 Number of logic level(s): 10 Starting point: u_ao_mem_ctrl.capture_mem_addr[0] / Q Ending point: u_ao_mem_ctrl.capture_mem_addr[8] / D The start point is clocked by ao_top|clk_i [rising] on pin CLK The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_addr[0] DFFCE Q Out 0.243 0.243 - capture_mem_addr[0] Net - - 0.535 - 6 u_ao_mem_ctrl.capture_mem_addr_cry_0[0] ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_mem_addr_cry_0[0] ALU COUT Out 0.549 1.327 - capture_mem_addr_cry[0] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_mem_addr_cry_0[1] ALU COUT Out 0.035 1.362 - capture_mem_addr_cry[1] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_mem_addr_cry_0[2] ALU COUT Out 0.035 1.397 - capture_mem_addr_cry[2] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_mem_addr_cry_0[3] ALU COUT Out 0.035 1.432 - capture_mem_addr_cry[3] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_mem_addr_cry_0[4] ALU COUT Out 0.035 1.467 - capture_mem_addr_cry[4] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_mem_addr_cry_0[5] ALU COUT Out 0.035 1.502 - capture_mem_addr_cry[5] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_mem_addr_cry_0[6] ALU COUT Out 0.035 1.537 - capture_mem_addr_cry[6] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_mem_addr_cry_0[7] ALU COUT Out 0.035 1.572 - capture_mem_addr_cry[7] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_mem_addr_cry_0[8] ALU SUM Out 0.470 2.042 - capture_mem_addr_s[8] Net - - 0.535 - 1 u_ao_mem_ctrl.capture_mem_addr_lm_0[8] LUT4 I1 In - 2.577 - u_ao_mem_ctrl.capture_mem_addr_lm_0[8] LUT4 F Out 0.570 3.147 - capture_mem_addr_lm[8] Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_addr[8] DFFCE D In - 3.147 - ======================================================================================================= Total path delay (propagation time + setup) of 3.208 is 2.138(66.6%) logic and 1.070(33.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------ bit_count[2] ao_top|control[0] DFFCE Q bit_count[2] 0.243 -0.831 bit_count[0] ao_top|control[0] DFFCE Q bit_count[0] 0.243 -0.810 bit_count[3] ao_top|control[0] DFFCE Q bit_count[3] 0.243 -0.723 bit_count[4] ao_top|control[0] DFFCE Q bit_count[4] 0.243 -0.653 bit_count[1] ao_top|control[0] DFFCE Q bit_count[1] 0.243 -0.632 bit_count[5] ao_top|control[0] DFFCE Q bit_count[5] 0.243 -0.545 data_register[67] ao_top|control[0] DFFCE Q data_register[67] 0.243 -0.521 data_register[71] ao_top|control[0] DFFCE Q data_register[71] 0.243 -0.430 word_count[10] ao_top|control[0] DFFCE Q word_count[10] 0.243 -0.405 word_count[0] ao_top|control[0] DFFCE Q word_count[0] 0.243 -0.384 ====================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- data_out_shift_reg[0] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[1] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[2] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[3] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[4] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[5] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[6] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[7] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[8] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 data_out_shift_reg[9] ao_top|control[0] DFFCE CE un1_out_reg_shift_en 4.649 -0.831 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.710 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.649 - Propagation time: 5.480 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.831 Number of logic level(s): 4 Starting point: bit_count[2] / Q Ending point: data_out_shift_reg[0] / CE The start point is clocked by ao_top|control[0] [rising] on pin CLK The end point is clocked by ao_top|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- bit_count[2] DFFCE Q Out 0.243 0.243 - bit_count[2] Net - - 0.535 - 4 biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 I1 In - 0.778 - biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 F Out 0.570 1.348 - N_91 Net - - 0.535 - 4 out_reg_ld_en_m0 LUT4 I0 In - 1.883 - out_reg_ld_en_m0 LUT4 F Out 0.549 2.432 - out_reg_ld_en_m0 Net - - 0.535 - 2 out_reg_ld_en LUT4 I3 In - 2.967 - out_reg_ld_en LUT4 F Out 0.371 3.338 - out_reg_ld_en Net - - 0.840 - 52 un1_out_reg_shift_en LUT4 I2 In - 4.178 - un1_out_reg_shift_en LUT4 F Out 0.462 4.640 - un1_out_reg_shift_en Net - - 0.840 - 51 data_out_shift_reg[0] DFFCE CE In - 5.480 - ============================================================================================ Total path delay (propagation time + setup) of 5.541 is 2.256(40.7%) logic and 3.285(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.710 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.649 - Propagation time: 5.480 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.831 Number of logic level(s): 4 Starting point: bit_count[2] / Q Ending point: data_out_shift_reg[1] / CE The start point is clocked by ao_top|control[0] [rising] on pin CLK The end point is clocked by ao_top|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- bit_count[2] DFFCE Q Out 0.243 0.243 - bit_count[2] Net - - 0.535 - 4 biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 I1 In - 0.778 - biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 F Out 0.570 1.348 - N_91 Net - - 0.535 - 4 out_reg_ld_en_m0 LUT4 I0 In - 1.883 - out_reg_ld_en_m0 LUT4 F Out 0.549 2.432 - out_reg_ld_en_m0 Net - - 0.535 - 2 out_reg_ld_en LUT4 I3 In - 2.967 - out_reg_ld_en LUT4 F Out 0.371 3.338 - out_reg_ld_en Net - - 0.840 - 52 un1_out_reg_shift_en LUT4 I2 In - 4.178 - un1_out_reg_shift_en LUT4 F Out 0.462 4.640 - un1_out_reg_shift_en Net - - 0.840 - 51 data_out_shift_reg[1] DFFCE CE In - 5.480 - ============================================================================================ Total path delay (propagation time + setup) of 5.541 is 2.256(40.7%) logic and 3.285(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.710 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.649 - Propagation time: 5.480 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.831 Number of logic level(s): 4 Starting point: bit_count[2] / Q Ending point: data_out_shift_reg[2] / CE The start point is clocked by ao_top|control[0] [rising] on pin CLK The end point is clocked by ao_top|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- bit_count[2] DFFCE Q Out 0.243 0.243 - bit_count[2] Net - - 0.535 - 4 biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 I1 In - 0.778 - biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 F Out 0.570 1.348 - N_91 Net - - 0.535 - 4 out_reg_ld_en_m0 LUT4 I0 In - 1.883 - out_reg_ld_en_m0 LUT4 F Out 0.549 2.432 - out_reg_ld_en_m0 Net - - 0.535 - 2 out_reg_ld_en LUT4 I3 In - 2.967 - out_reg_ld_en LUT4 F Out 0.371 3.338 - out_reg_ld_en Net - - 0.840 - 52 un1_out_reg_shift_en LUT4 I2 In - 4.178 - un1_out_reg_shift_en LUT4 F Out 0.462 4.640 - un1_out_reg_shift_en Net - - 0.840 - 51 data_out_shift_reg[2] DFFCE CE In - 5.480 - ============================================================================================ Total path delay (propagation time + setup) of 5.541 is 2.256(40.7%) logic and 3.285(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.710 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.649 - Propagation time: 5.480 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.831 Number of logic level(s): 4 Starting point: bit_count[2] / Q Ending point: data_out_shift_reg[3] / CE The start point is clocked by ao_top|control[0] [rising] on pin CLK The end point is clocked by ao_top|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- bit_count[2] DFFCE Q Out 0.243 0.243 - bit_count[2] Net - - 0.535 - 4 biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 I1 In - 0.778 - biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 F Out 0.570 1.348 - N_91 Net - - 0.535 - 4 out_reg_ld_en_m0 LUT4 I0 In - 1.883 - out_reg_ld_en_m0 LUT4 F Out 0.549 2.432 - out_reg_ld_en_m0 Net - - 0.535 - 2 out_reg_ld_en LUT4 I3 In - 2.967 - out_reg_ld_en LUT4 F Out 0.371 3.338 - out_reg_ld_en Net - - 0.840 - 52 un1_out_reg_shift_en LUT4 I2 In - 4.178 - un1_out_reg_shift_en LUT4 F Out 0.462 4.640 - un1_out_reg_shift_en Net - - 0.840 - 51 data_out_shift_reg[3] DFFCE CE In - 5.480 - ============================================================================================ Total path delay (propagation time + setup) of 5.541 is 2.256(40.7%) logic and 3.285(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.710 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.649 - Propagation time: 5.480 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.831 Number of logic level(s): 4 Starting point: bit_count[2] / Q Ending point: data_out_shift_reg[4] / CE The start point is clocked by ao_top|control[0] [rising] on pin CLK The end point is clocked by ao_top|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- bit_count[2] DFFCE Q Out 0.243 0.243 - bit_count[2] Net - - 0.535 - 4 biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 I1 In - 0.778 - biu_strobe_0_sqmuxa_4_0_a2_0 LUT3 F Out 0.570 1.348 - N_91 Net - - 0.535 - 4 out_reg_ld_en_m0 LUT4 I0 In - 1.883 - out_reg_ld_en_m0 LUT4 F Out 0.549 2.432 - out_reg_ld_en_m0 Net - - 0.535 - 2 out_reg_ld_en LUT4 I3 In - 2.967 - out_reg_ld_en LUT4 F Out 0.371 3.338 - out_reg_ld_en Net - - 0.840 - 52 un1_out_reg_shift_en LUT4 I2 In - 4.178 - un1_out_reg_shift_en LUT4 F Out 0.462 4.640 - un1_out_reg_shift_en Net - - 0.840 - 51 data_out_shift_reg[4] DFFCE CE In - 5.480 - ============================================================================================ Total path delay (propagation time + setup) of 5.541 is 2.256(40.7%) logic and 3.285(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 System INV O capture_end 0.000 1.612 address_counter_cry_0_RNO[0] System INV O address_counter 0.000 2.794 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ capture_start_sel System DFFCE CE internal_reg_start_dly_2_i[0] 2.696 1.612 internal_reg_start_dly[0] System DFFC D internal_reg_start_dly_2[0] 2.696 1.612 capture_end_dly System DFFP D capture_end 2.696 2.161 address_counter[9] System DFFCE D address_counter_s[9] 4.649 2.794 address_counter[8] System DFFCE D address_counter_s[8] 4.649 2.829 address_counter[7] System DFFCE D address_counter_s[7] 4.649 2.864 address_counter[6] System DFFCE D address_counter_s[6] 4.649 2.899 address_counter[5] System DFFCE D address_counter_s[5] 4.649 2.934 address_counter[4] System DFFCE D address_counter_s[4] 4.649 2.969 address_counter[3] System DFFCE D address_counter_s[3] 4.649 3.004 ================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.757 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.696 - Propagation time: 1.084 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.612 Number of logic level(s): 1 Starting point: u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O Ending point: internal_reg_start_dly[0] / D The start point is clocked by System [rising] The end point is clocked by ao_top|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 INV O Out 0.000 0.000 - capture_end Net - - 0.535 - 4 internal_reg_start_dly_2[0] LUT3 I0 In - 0.535 - internal_reg_start_dly_2[0] LUT3 F Out 0.549 1.084 - internal_reg_start_dly_2[0] Net - - 0.000 - 1 internal_reg_start_dly[0] DFFC D In - 1.084 - =================================================================================================== Total path delay (propagation time + setup) of 1.145 is 0.610(53.3%) logic and 0.535(46.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:31s; Memory used current: 234MB peak: 235MB) Finished timing report (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:31s; Memory used current: 234MB peak: 235MB) --------------------------------------- Resource Usage Report for ao_top Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 42 uses DFFC 12 uses DFFCE 204 uses DFFNP 2 uses DFFP 2 uses GSR 1 use INV 2 uses MUX2_LUT5 3 uses MUX2_LUT6 1 use SDPX9 3 uses LUT2 30 uses LUT3 42 uses LUT4 125 uses I/O ports: 62 I/O primitives: 62 IBUF 60 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 220 of 15552 (1%) RAM/ROM usage summary Block Rams : 3 of 46 (6%) Total load per clock: ao_top|clk_i: 1 ao_top|control[0]: 201 @S |Mapping Summary: Total LUTs: 197 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:31s; Memory used current: 78MB peak: 235MB) Process took 0h:00m:31s realtime, 0h:00m:31s cputime # Wed May 20 01:55:07 2020 ###########################################################]