Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\static_macro_define.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Verision | GowinSynthesis V1.9.5.02Beta |
| Created Time | Wed May 20 19:07:11 2020 |
| Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved. |
Design Settings
| Top Level Module: | ASRC_TOP |
| Part Number: | GW2A-LV18PG256C8/I7 |
Resource
Resource Usage Summary
| I/OPORT Usage: | 253 |
| I/OBUF Usage: | 253 |
| IBUF | 128 |
| OBUF | 125 |
| REG Usage: | 1915 |
| DFFE | 4 |
| DFFPE | 21 |
| DFFCE | 1864 |
| DL | 26 |
| LUT Usage: | 2286 |
| LUT2 | 578 |
| LUT3 | 580 |
| LUT4 | 1128 |
| ALU Usage: | 683 |
| ALU | 683 |
| INV Usage: | 4 |
| INV | 4 |
| DSP Usage: | 3 |
| MULT36X36 | 3 |
| BSRAM Usage: | 8 |
| SP | 1 |
| SDPB | 4 |
| pROM | 3 |
Resource Utilization Summary
Target Device: GW2A-18-PBGA256| CFU Logics | 2973(2290 LUTs, 683 ALUs) / 20736 | 14% |
| Registers | 1915 / 16173 | 12% |
| BSRAMs | 8 / 46 | 17% |
| DSP Macros | 6 / (12*2) | 25% |
Timing
Clock Summary:
| Clock | Type | Frequency | Period | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| DEFAULT_CLK | Base | 100.0 MHz | 10.000 | 0.000 | 5.000 |
Timing Report:
| Top View: | ASRC_TOP |
| Requested Frequency: | 100.0 MHz |
| Paths Requested: | 5 |
| Constraint File(ignored): |
Performance Summary:
Worst Slack in Design: 2.420| Start Clock | Slack | Requested Frequency | Estimated Frequency | Requested Period | Estimated Period | Clock Type |
|---|---|---|---|---|---|---|
| DEFAULT_CLK | 2.420 | 100.0 MHz | 131.9 MHz | 10.000 | 7.580 | Base |
Detail Timing Paths Information
Path information for path number 1 :| Clock Skew: | 0.062 |
| Setup Relationship: | 5.000 |
| Slack(critical): | 2.236 |
| Data Arrival Time: | 3.453 |
| Data Required Time: | 5.690 |
| Number of Logic Level: | 5 |
| Starting Point: | asrc/ratio_dect/err_mag_vari_0_ins11352 |
| Ending Point: | asrc/ratio_dect/ratio_vari_25_ins13532 |
| The Start Point Is Clocked By: | DEFAULT_CLK[falling] |
| The End Point Is Clocked By: | DEFAULT_CLK[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| clk_ibuf8818 | IBUF | I | In | - | 0.000 | - |
| clk_ibuf8818 | IBUF | O | Out | 0.683 | 0.683 | - |
| clk | Net | - | - | 0.180 | - | 1904 |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | CLK | In | - | 0.863 | - |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | Q | Out | 0.232 | 1.095 | - |
| asrc_ratio_dect_err_mag_vari[0] | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/n1148_ins15362 | ALU | I1 | In | - | 1.332 | - |
| \asrc/ratio_dect/n1148_ins15362 | ALU | COUT | Out | 0.570 | 1.901 | - |
| asrc_ratio_dect_n1148_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1147_ins15363 | ALU | CIN | In | - | 1.901 | - |
| \asrc/ratio_dect/n1147_ins15363 | ALU | COUT | Out | 0.035 | 1.937 | - |
| asrc_ratio_dect_n1147_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1146_ins15364 | ALU | CIN | In | - | 1.937 | - |
| \asrc/ratio_dect/n1146_ins15364 | ALU | COUT | Out | 0.035 | 1.972 | - |
| asrc_ratio_dect_n1146_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1145_ins15365 | ALU | CIN | In | - | 1.972 | - |
| \asrc/ratio_dect/n1145_ins15365 | ALU | COUT | Out | 0.035 | 2.007 | - |
| asrc_ratio_dect_n1145_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1144_ins15366 | ALU | CIN | In | - | 2.007 | - |
| \asrc/ratio_dect/n1144_ins15366 | ALU | COUT | Out | 0.035 | 2.042 | - |
| asrc_ratio_dect_n1144_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1143_ins15367 | ALU | CIN | In | - | 2.042 | - |
| \asrc/ratio_dect/n1143_ins15367 | ALU | COUT | Out | 0.035 | 2.078 | - |
| asrc_ratio_dect_n1143_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1142_ins15368 | ALU | CIN | In | - | 2.078 | - |
| \asrc/ratio_dect/n1142_ins15368 | ALU | COUT | Out | 0.035 | 2.113 | - |
| asrc_ratio_dect_n1142_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1141_ins15369 | ALU | CIN | In | - | 2.113 | - |
| \asrc/ratio_dect/n1141_ins15369 | ALU | COUT | Out | 0.035 | 2.148 | - |
| asrc_ratio_dect_n1141_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1140_ins15370 | ALU | CIN | In | - | 2.148 | - |
| \asrc/ratio_dect/n1140_ins15370 | ALU | COUT | Out | 0.035 | 2.183 | - |
| asrc_ratio_dect_n1140_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1139_ins15371 | ALU | CIN | In | - | 2.183 | - |
| \asrc/ratio_dect/n1139_ins15371 | ALU | COUT | Out | 0.035 | 2.218 | - |
| asrc_ratio_dect_n1139_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1138_ins15372 | ALU | CIN | In | - | 2.218 | - |
| \asrc/ratio_dect/n1138_ins15372 | ALU | COUT | Out | 0.035 | 2.254 | - |
| asrc_ratio_dect_n1138_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1137_ins15373 | ALU | CIN | In | - | 2.254 | - |
| \asrc/ratio_dect/n1137_ins15373 | ALU | COUT | Out | 0.035 | 2.289 | - |
| asrc_ratio_dect_n1137_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1136_ins15374 | ALU | CIN | In | - | 2.289 | - |
| \asrc/ratio_dect/n1136_ins15374 | ALU | COUT | Out | 0.035 | 2.324 | - |
| asrc_ratio_dect_n1136_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1135_ins15375 | ALU | CIN | In | - | 2.324 | - |
| \asrc/ratio_dect/n1135_ins15375 | ALU | COUT | Out | 0.035 | 2.359 | - |
| asrc_ratio_dect_n1135_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1134_ins15376 | ALU | CIN | In | - | 2.359 | - |
| \asrc/ratio_dect/n1134_ins15376 | ALU | COUT | Out | 0.035 | 2.394 | - |
| asrc_ratio_dect_n1134_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1133_ins15377 | ALU | CIN | In | - | 2.394 | - |
| \asrc/ratio_dect/n1133_ins15377 | ALU | COUT | Out | 0.035 | 2.430 | - |
| asrc_ratio_dect_n1133_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1132_ins15378 | ALU | CIN | In | - | 2.430 | - |
| \asrc/ratio_dect/n1132_ins15378 | ALU | COUT | Out | 0.035 | 2.465 | - |
| asrc_ratio_dect_n1132_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1131_ins15379 | ALU | CIN | In | - | 2.465 | - |
| \asrc/ratio_dect/n1131_ins15379 | ALU | COUT | Out | 0.035 | 2.500 | - |
| asrc_ratio_dect_n1131_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1130_ins15380 | ALU | CIN | In | - | 2.500 | - |
| \asrc/ratio_dect/n1130_ins15380 | ALU | COUT | Out | 0.035 | 2.535 | - |
| asrc_ratio_dect_n1130_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1129_ins15381 | ALU | CIN | In | - | 2.535 | - |
| \asrc/ratio_dect/n1129_ins15381 | ALU | COUT | Out | 0.035 | 2.570 | - |
| asrc_ratio_dect_n1129_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1128_ins15382 | ALU | CIN | In | - | 2.570 | - |
| \asrc/ratio_dect/n1128_ins15382 | ALU | COUT | Out | 0.035 | 2.606 | - |
| asrc_ratio_dect_n1128_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1127_ins15383 | ALU | CIN | In | - | 2.606 | - |
| \asrc/ratio_dect/n1127_ins15383 | ALU | COUT | Out | 0.035 | 2.641 | - |
| asrc_ratio_dect_n1127_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1126_ins15384 | ALU | CIN | In | - | 2.641 | - |
| \asrc/ratio_dect/n1126_ins15384 | ALU | COUT | Out | 0.035 | 2.676 | - |
| asrc_ratio_dect_n1126_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1125_ins15385 | ALU | CIN | In | - | 2.676 | - |
| \asrc/ratio_dect/n1125_ins15385 | ALU | COUT | Out | 0.035 | 2.711 | - |
| asrc_ratio_dect_n1125_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1124_ins15386 | ALU | CIN | In | - | 2.711 | - |
| \asrc/ratio_dect/n1124_ins15386 | ALU | COUT | Out | 0.035 | 2.746 | - |
| asrc_ratio_dect_n1124_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1123_ins15387 | ALU | CIN | In | - | 2.746 | - |
| \asrc/ratio_dect/n1123_ins15387 | ALU | SUM | Out | 0.470 | 3.216 | - |
| asrc_ratio_dect_n1123 | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/ratio_vari_25_ins13532 | DL | D | In | - | 3.453 | - |
Total Path Delay: 3.453
Logic Delay: 2.799(81.1%)
Route Delay: 0.654(18.9%)
Path information for path number 2 :
| Clock Skew: | 0.124 |
| Setup Relationship: | 5.000 |
| Slack(non-critical): | 2.271 |
| Data Arrival Time: | 3.418 |
| Data Required Time: | 5.690 |
| Number of Logic Level: | 5 |
| Starting Point: | asrc/ratio_dect/err_mag_vari_0_ins11352 |
| Ending Point: | asrc/ratio_dect/ratio_vari_24_ins13533 |
| The Start Point Is Clocked By: | DEFAULT_CLK[falling] |
| The End Point Is Clocked By: | DEFAULT_CLK[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| clk_ibuf8818 | IBUF | I | In | - | 0.000 | - |
| clk_ibuf8818 | IBUF | O | Out | 0.683 | 0.683 | - |
| clk | Net | - | - | 0.180 | - | 1904 |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | CLK | In | - | 0.863 | - |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | Q | Out | 0.232 | 1.095 | - |
| asrc_ratio_dect_err_mag_vari[0] | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/n1148_ins15362 | ALU | I1 | In | - | 1.332 | - |
| \asrc/ratio_dect/n1148_ins15362 | ALU | COUT | Out | 0.570 | 1.901 | - |
| asrc_ratio_dect_n1148_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1147_ins15363 | ALU | CIN | In | - | 1.901 | - |
| \asrc/ratio_dect/n1147_ins15363 | ALU | COUT | Out | 0.035 | 1.937 | - |
| asrc_ratio_dect_n1147_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1146_ins15364 | ALU | CIN | In | - | 1.937 | - |
| \asrc/ratio_dect/n1146_ins15364 | ALU | COUT | Out | 0.035 | 1.972 | - |
| asrc_ratio_dect_n1146_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1145_ins15365 | ALU | CIN | In | - | 1.972 | - |
| \asrc/ratio_dect/n1145_ins15365 | ALU | COUT | Out | 0.035 | 2.007 | - |
| asrc_ratio_dect_n1145_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1144_ins15366 | ALU | CIN | In | - | 2.007 | - |
| \asrc/ratio_dect/n1144_ins15366 | ALU | COUT | Out | 0.035 | 2.042 | - |
| asrc_ratio_dect_n1144_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1143_ins15367 | ALU | CIN | In | - | 2.042 | - |
| \asrc/ratio_dect/n1143_ins15367 | ALU | COUT | Out | 0.035 | 2.078 | - |
| asrc_ratio_dect_n1143_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1142_ins15368 | ALU | CIN | In | - | 2.078 | - |
| \asrc/ratio_dect/n1142_ins15368 | ALU | COUT | Out | 0.035 | 2.113 | - |
| asrc_ratio_dect_n1142_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1141_ins15369 | ALU | CIN | In | - | 2.113 | - |
| \asrc/ratio_dect/n1141_ins15369 | ALU | COUT | Out | 0.035 | 2.148 | - |
| asrc_ratio_dect_n1141_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1140_ins15370 | ALU | CIN | In | - | 2.148 | - |
| \asrc/ratio_dect/n1140_ins15370 | ALU | COUT | Out | 0.035 | 2.183 | - |
| asrc_ratio_dect_n1140_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1139_ins15371 | ALU | CIN | In | - | 2.183 | - |
| \asrc/ratio_dect/n1139_ins15371 | ALU | COUT | Out | 0.035 | 2.218 | - |
| asrc_ratio_dect_n1139_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1138_ins15372 | ALU | CIN | In | - | 2.218 | - |
| \asrc/ratio_dect/n1138_ins15372 | ALU | COUT | Out | 0.035 | 2.254 | - |
| asrc_ratio_dect_n1138_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1137_ins15373 | ALU | CIN | In | - | 2.254 | - |
| \asrc/ratio_dect/n1137_ins15373 | ALU | COUT | Out | 0.035 | 2.289 | - |
| asrc_ratio_dect_n1137_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1136_ins15374 | ALU | CIN | In | - | 2.289 | - |
| \asrc/ratio_dect/n1136_ins15374 | ALU | COUT | Out | 0.035 | 2.324 | - |
| asrc_ratio_dect_n1136_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1135_ins15375 | ALU | CIN | In | - | 2.324 | - |
| \asrc/ratio_dect/n1135_ins15375 | ALU | COUT | Out | 0.035 | 2.359 | - |
| asrc_ratio_dect_n1135_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1134_ins15376 | ALU | CIN | In | - | 2.359 | - |
| \asrc/ratio_dect/n1134_ins15376 | ALU | COUT | Out | 0.035 | 2.394 | - |
| asrc_ratio_dect_n1134_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1133_ins15377 | ALU | CIN | In | - | 2.394 | - |
| \asrc/ratio_dect/n1133_ins15377 | ALU | COUT | Out | 0.035 | 2.430 | - |
| asrc_ratio_dect_n1133_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1132_ins15378 | ALU | CIN | In | - | 2.430 | - |
| \asrc/ratio_dect/n1132_ins15378 | ALU | COUT | Out | 0.035 | 2.465 | - |
| asrc_ratio_dect_n1132_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1131_ins15379 | ALU | CIN | In | - | 2.465 | - |
| \asrc/ratio_dect/n1131_ins15379 | ALU | COUT | Out | 0.035 | 2.500 | - |
| asrc_ratio_dect_n1131_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1130_ins15380 | ALU | CIN | In | - | 2.500 | - |
| \asrc/ratio_dect/n1130_ins15380 | ALU | COUT | Out | 0.035 | 2.535 | - |
| asrc_ratio_dect_n1130_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1129_ins15381 | ALU | CIN | In | - | 2.535 | - |
| \asrc/ratio_dect/n1129_ins15381 | ALU | COUT | Out | 0.035 | 2.570 | - |
| asrc_ratio_dect_n1129_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1128_ins15382 | ALU | CIN | In | - | 2.570 | - |
| \asrc/ratio_dect/n1128_ins15382 | ALU | COUT | Out | 0.035 | 2.606 | - |
| asrc_ratio_dect_n1128_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1127_ins15383 | ALU | CIN | In | - | 2.606 | - |
| \asrc/ratio_dect/n1127_ins15383 | ALU | COUT | Out | 0.035 | 2.641 | - |
| asrc_ratio_dect_n1127_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1126_ins15384 | ALU | CIN | In | - | 2.641 | - |
| \asrc/ratio_dect/n1126_ins15384 | ALU | COUT | Out | 0.035 | 2.676 | - |
| asrc_ratio_dect_n1126_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1125_ins15385 | ALU | CIN | In | - | 2.676 | - |
| \asrc/ratio_dect/n1125_ins15385 | ALU | COUT | Out | 0.035 | 2.711 | - |
| asrc_ratio_dect_n1125_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1124_ins15386 | ALU | CIN | In | - | 2.711 | - |
| \asrc/ratio_dect/n1124_ins15386 | ALU | SUM | Out | 0.470 | 3.181 | - |
| asrc_ratio_dect_n1124 | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/ratio_vari_24_ins13533 | DL | D | In | - | 3.418 | - |
Total Path Delay: 3.418
Logic Delay: 2.764(80.9%)
Route Delay: 0.654(19.1%)
Path information for path number 3 :
| Clock Skew: | 0.186 |
| Setup Relationship: | 5.000 |
| Slack(non-critical): | 2.307 |
| Data Arrival Time: | 3.383 |
| Data Required Time: | 5.690 |
| Number of Logic Level: | 5 |
| Starting Point: | asrc/ratio_dect/err_mag_vari_0_ins11352 |
| Ending Point: | asrc/ratio_dect/ratio_vari_23_ins13534 |
| The Start Point Is Clocked By: | DEFAULT_CLK[falling] |
| The End Point Is Clocked By: | DEFAULT_CLK[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| clk_ibuf8818 | IBUF | I | In | - | 0.000 | - |
| clk_ibuf8818 | IBUF | O | Out | 0.683 | 0.683 | - |
| clk | Net | - | - | 0.180 | - | 1904 |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | CLK | In | - | 0.863 | - |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | Q | Out | 0.232 | 1.095 | - |
| asrc_ratio_dect_err_mag_vari[0] | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/n1148_ins15362 | ALU | I1 | In | - | 1.332 | - |
| \asrc/ratio_dect/n1148_ins15362 | ALU | COUT | Out | 0.570 | 1.901 | - |
| asrc_ratio_dect_n1148_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1147_ins15363 | ALU | CIN | In | - | 1.901 | - |
| \asrc/ratio_dect/n1147_ins15363 | ALU | COUT | Out | 0.035 | 1.937 | - |
| asrc_ratio_dect_n1147_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1146_ins15364 | ALU | CIN | In | - | 1.937 | - |
| \asrc/ratio_dect/n1146_ins15364 | ALU | COUT | Out | 0.035 | 1.972 | - |
| asrc_ratio_dect_n1146_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1145_ins15365 | ALU | CIN | In | - | 1.972 | - |
| \asrc/ratio_dect/n1145_ins15365 | ALU | COUT | Out | 0.035 | 2.007 | - |
| asrc_ratio_dect_n1145_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1144_ins15366 | ALU | CIN | In | - | 2.007 | - |
| \asrc/ratio_dect/n1144_ins15366 | ALU | COUT | Out | 0.035 | 2.042 | - |
| asrc_ratio_dect_n1144_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1143_ins15367 | ALU | CIN | In | - | 2.042 | - |
| \asrc/ratio_dect/n1143_ins15367 | ALU | COUT | Out | 0.035 | 2.078 | - |
| asrc_ratio_dect_n1143_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1142_ins15368 | ALU | CIN | In | - | 2.078 | - |
| \asrc/ratio_dect/n1142_ins15368 | ALU | COUT | Out | 0.035 | 2.113 | - |
| asrc_ratio_dect_n1142_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1141_ins15369 | ALU | CIN | In | - | 2.113 | - |
| \asrc/ratio_dect/n1141_ins15369 | ALU | COUT | Out | 0.035 | 2.148 | - |
| asrc_ratio_dect_n1141_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1140_ins15370 | ALU | CIN | In | - | 2.148 | - |
| \asrc/ratio_dect/n1140_ins15370 | ALU | COUT | Out | 0.035 | 2.183 | - |
| asrc_ratio_dect_n1140_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1139_ins15371 | ALU | CIN | In | - | 2.183 | - |
| \asrc/ratio_dect/n1139_ins15371 | ALU | COUT | Out | 0.035 | 2.218 | - |
| asrc_ratio_dect_n1139_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1138_ins15372 | ALU | CIN | In | - | 2.218 | - |
| \asrc/ratio_dect/n1138_ins15372 | ALU | COUT | Out | 0.035 | 2.254 | - |
| asrc_ratio_dect_n1138_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1137_ins15373 | ALU | CIN | In | - | 2.254 | - |
| \asrc/ratio_dect/n1137_ins15373 | ALU | COUT | Out | 0.035 | 2.289 | - |
| asrc_ratio_dect_n1137_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1136_ins15374 | ALU | CIN | In | - | 2.289 | - |
| \asrc/ratio_dect/n1136_ins15374 | ALU | COUT | Out | 0.035 | 2.324 | - |
| asrc_ratio_dect_n1136_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1135_ins15375 | ALU | CIN | In | - | 2.324 | - |
| \asrc/ratio_dect/n1135_ins15375 | ALU | COUT | Out | 0.035 | 2.359 | - |
| asrc_ratio_dect_n1135_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1134_ins15376 | ALU | CIN | In | - | 2.359 | - |
| \asrc/ratio_dect/n1134_ins15376 | ALU | COUT | Out | 0.035 | 2.394 | - |
| asrc_ratio_dect_n1134_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1133_ins15377 | ALU | CIN | In | - | 2.394 | - |
| \asrc/ratio_dect/n1133_ins15377 | ALU | COUT | Out | 0.035 | 2.430 | - |
| asrc_ratio_dect_n1133_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1132_ins15378 | ALU | CIN | In | - | 2.430 | - |
| \asrc/ratio_dect/n1132_ins15378 | ALU | COUT | Out | 0.035 | 2.465 | - |
| asrc_ratio_dect_n1132_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1131_ins15379 | ALU | CIN | In | - | 2.465 | - |
| \asrc/ratio_dect/n1131_ins15379 | ALU | COUT | Out | 0.035 | 2.500 | - |
| asrc_ratio_dect_n1131_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1130_ins15380 | ALU | CIN | In | - | 2.500 | - |
| \asrc/ratio_dect/n1130_ins15380 | ALU | COUT | Out | 0.035 | 2.535 | - |
| asrc_ratio_dect_n1130_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1129_ins15381 | ALU | CIN | In | - | 2.535 | - |
| \asrc/ratio_dect/n1129_ins15381 | ALU | COUT | Out | 0.035 | 2.570 | - |
| asrc_ratio_dect_n1129_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1128_ins15382 | ALU | CIN | In | - | 2.570 | - |
| \asrc/ratio_dect/n1128_ins15382 | ALU | COUT | Out | 0.035 | 2.606 | - |
| asrc_ratio_dect_n1128_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1127_ins15383 | ALU | CIN | In | - | 2.606 | - |
| \asrc/ratio_dect/n1127_ins15383 | ALU | COUT | Out | 0.035 | 2.641 | - |
| asrc_ratio_dect_n1127_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1126_ins15384 | ALU | CIN | In | - | 2.641 | - |
| \asrc/ratio_dect/n1126_ins15384 | ALU | COUT | Out | 0.035 | 2.676 | - |
| asrc_ratio_dect_n1126_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1125_ins15385 | ALU | CIN | In | - | 2.676 | - |
| \asrc/ratio_dect/n1125_ins15385 | ALU | SUM | Out | 0.470 | 3.146 | - |
| asrc_ratio_dect_n1125 | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/ratio_vari_23_ins13534 | DL | D | In | - | 3.383 | - |
Total Path Delay: 3.383
Logic Delay: 2.729(80.7%)
Route Delay: 0.654(19.3%)
Path information for path number 4 :
| Clock Skew: | 0.248 |
| Setup Relationship: | 5.000 |
| Slack(non-critical): | 2.342 |
| Data Arrival Time: | 3.348 |
| Data Required Time: | 5.690 |
| Number of Logic Level: | 5 |
| Starting Point: | asrc/ratio_dect/err_mag_vari_0_ins11352 |
| Ending Point: | asrc/ratio_dect/ratio_vari_22_ins13535 |
| The Start Point Is Clocked By: | DEFAULT_CLK[falling] |
| The End Point Is Clocked By: | DEFAULT_CLK[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| clk_ibuf8818 | IBUF | I | In | - | 0.000 | - |
| clk_ibuf8818 | IBUF | O | Out | 0.683 | 0.683 | - |
| clk | Net | - | - | 0.180 | - | 1904 |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | CLK | In | - | 0.863 | - |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | Q | Out | 0.232 | 1.095 | - |
| asrc_ratio_dect_err_mag_vari[0] | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/n1148_ins15362 | ALU | I1 | In | - | 1.332 | - |
| \asrc/ratio_dect/n1148_ins15362 | ALU | COUT | Out | 0.570 | 1.901 | - |
| asrc_ratio_dect_n1148_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1147_ins15363 | ALU | CIN | In | - | 1.901 | - |
| \asrc/ratio_dect/n1147_ins15363 | ALU | COUT | Out | 0.035 | 1.937 | - |
| asrc_ratio_dect_n1147_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1146_ins15364 | ALU | CIN | In | - | 1.937 | - |
| \asrc/ratio_dect/n1146_ins15364 | ALU | COUT | Out | 0.035 | 1.972 | - |
| asrc_ratio_dect_n1146_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1145_ins15365 | ALU | CIN | In | - | 1.972 | - |
| \asrc/ratio_dect/n1145_ins15365 | ALU | COUT | Out | 0.035 | 2.007 | - |
| asrc_ratio_dect_n1145_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1144_ins15366 | ALU | CIN | In | - | 2.007 | - |
| \asrc/ratio_dect/n1144_ins15366 | ALU | COUT | Out | 0.035 | 2.042 | - |
| asrc_ratio_dect_n1144_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1143_ins15367 | ALU | CIN | In | - | 2.042 | - |
| \asrc/ratio_dect/n1143_ins15367 | ALU | COUT | Out | 0.035 | 2.078 | - |
| asrc_ratio_dect_n1143_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1142_ins15368 | ALU | CIN | In | - | 2.078 | - |
| \asrc/ratio_dect/n1142_ins15368 | ALU | COUT | Out | 0.035 | 2.113 | - |
| asrc_ratio_dect_n1142_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1141_ins15369 | ALU | CIN | In | - | 2.113 | - |
| \asrc/ratio_dect/n1141_ins15369 | ALU | COUT | Out | 0.035 | 2.148 | - |
| asrc_ratio_dect_n1141_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1140_ins15370 | ALU | CIN | In | - | 2.148 | - |
| \asrc/ratio_dect/n1140_ins15370 | ALU | COUT | Out | 0.035 | 2.183 | - |
| asrc_ratio_dect_n1140_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1139_ins15371 | ALU | CIN | In | - | 2.183 | - |
| \asrc/ratio_dect/n1139_ins15371 | ALU | COUT | Out | 0.035 | 2.218 | - |
| asrc_ratio_dect_n1139_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1138_ins15372 | ALU | CIN | In | - | 2.218 | - |
| \asrc/ratio_dect/n1138_ins15372 | ALU | COUT | Out | 0.035 | 2.254 | - |
| asrc_ratio_dect_n1138_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1137_ins15373 | ALU | CIN | In | - | 2.254 | - |
| \asrc/ratio_dect/n1137_ins15373 | ALU | COUT | Out | 0.035 | 2.289 | - |
| asrc_ratio_dect_n1137_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1136_ins15374 | ALU | CIN | In | - | 2.289 | - |
| \asrc/ratio_dect/n1136_ins15374 | ALU | COUT | Out | 0.035 | 2.324 | - |
| asrc_ratio_dect_n1136_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1135_ins15375 | ALU | CIN | In | - | 2.324 | - |
| \asrc/ratio_dect/n1135_ins15375 | ALU | COUT | Out | 0.035 | 2.359 | - |
| asrc_ratio_dect_n1135_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1134_ins15376 | ALU | CIN | In | - | 2.359 | - |
| \asrc/ratio_dect/n1134_ins15376 | ALU | COUT | Out | 0.035 | 2.394 | - |
| asrc_ratio_dect_n1134_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1133_ins15377 | ALU | CIN | In | - | 2.394 | - |
| \asrc/ratio_dect/n1133_ins15377 | ALU | COUT | Out | 0.035 | 2.430 | - |
| asrc_ratio_dect_n1133_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1132_ins15378 | ALU | CIN | In | - | 2.430 | - |
| \asrc/ratio_dect/n1132_ins15378 | ALU | COUT | Out | 0.035 | 2.465 | - |
| asrc_ratio_dect_n1132_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1131_ins15379 | ALU | CIN | In | - | 2.465 | - |
| \asrc/ratio_dect/n1131_ins15379 | ALU | COUT | Out | 0.035 | 2.500 | - |
| asrc_ratio_dect_n1131_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1130_ins15380 | ALU | CIN | In | - | 2.500 | - |
| \asrc/ratio_dect/n1130_ins15380 | ALU | COUT | Out | 0.035 | 2.535 | - |
| asrc_ratio_dect_n1130_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1129_ins15381 | ALU | CIN | In | - | 2.535 | - |
| \asrc/ratio_dect/n1129_ins15381 | ALU | COUT | Out | 0.035 | 2.570 | - |
| asrc_ratio_dect_n1129_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1128_ins15382 | ALU | CIN | In | - | 2.570 | - |
| \asrc/ratio_dect/n1128_ins15382 | ALU | COUT | Out | 0.035 | 2.606 | - |
| asrc_ratio_dect_n1128_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1127_ins15383 | ALU | CIN | In | - | 2.606 | - |
| \asrc/ratio_dect/n1127_ins15383 | ALU | COUT | Out | 0.035 | 2.641 | - |
| asrc_ratio_dect_n1127_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1126_ins15384 | ALU | CIN | In | - | 2.641 | - |
| \asrc/ratio_dect/n1126_ins15384 | ALU | SUM | Out | 0.470 | 3.111 | - |
| asrc_ratio_dect_n1126 | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/ratio_vari_22_ins13535 | DL | D | In | - | 3.348 | - |
Total Path Delay: 3.348
Logic Delay: 2.694(80.5%)
Route Delay: 0.654(19.5%)
Path information for path number 5 :
| Clock Skew: | 0.310 |
| Setup Relationship: | 5.000 |
| Slack(non-critical): | 2.377 |
| Data Arrival Time: | 3.313 |
| Data Required Time: | 5.690 |
| Number of Logic Level: | 4 |
| Starting Point: | asrc/ratio_dect/err_mag_vari_0_ins11352 |
| Ending Point: | asrc/ratio_dect/ratio_vari_21_ins13536 |
| The Start Point Is Clocked By: | DEFAULT_CLK[falling] |
| The End Point Is Clocked By: | DEFAULT_CLK[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| clk_ibuf8818 | IBUF | I | In | - | 0.000 | - |
| clk_ibuf8818 | IBUF | O | Out | 0.683 | 0.683 | - |
| clk | Net | - | - | 0.180 | - | 1904 |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | CLK | In | - | 0.863 | - |
| \asrc/ratio_dect/err_mag_vari_0_ins11352 | DFFCE | Q | Out | 0.232 | 1.095 | - |
| asrc_ratio_dect_err_mag_vari[0] | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/n1148_ins15362 | ALU | I1 | In | - | 1.332 | - |
| \asrc/ratio_dect/n1148_ins15362 | ALU | COUT | Out | 0.570 | 1.901 | - |
| asrc_ratio_dect_n1148_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1147_ins15363 | ALU | CIN | In | - | 1.901 | - |
| \asrc/ratio_dect/n1147_ins15363 | ALU | COUT | Out | 0.035 | 1.937 | - |
| asrc_ratio_dect_n1147_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1146_ins15364 | ALU | CIN | In | - | 1.937 | - |
| \asrc/ratio_dect/n1146_ins15364 | ALU | COUT | Out | 0.035 | 1.972 | - |
| asrc_ratio_dect_n1146_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1145_ins15365 | ALU | CIN | In | - | 1.972 | - |
| \asrc/ratio_dect/n1145_ins15365 | ALU | COUT | Out | 0.035 | 2.007 | - |
| asrc_ratio_dect_n1145_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1144_ins15366 | ALU | CIN | In | - | 2.007 | - |
| \asrc/ratio_dect/n1144_ins15366 | ALU | COUT | Out | 0.035 | 2.042 | - |
| asrc_ratio_dect_n1144_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1143_ins15367 | ALU | CIN | In | - | 2.042 | - |
| \asrc/ratio_dect/n1143_ins15367 | ALU | COUT | Out | 0.035 | 2.078 | - |
| asrc_ratio_dect_n1143_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1142_ins15368 | ALU | CIN | In | - | 2.078 | - |
| \asrc/ratio_dect/n1142_ins15368 | ALU | COUT | Out | 0.035 | 2.113 | - |
| asrc_ratio_dect_n1142_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1141_ins15369 | ALU | CIN | In | - | 2.113 | - |
| \asrc/ratio_dect/n1141_ins15369 | ALU | COUT | Out | 0.035 | 2.148 | - |
| asrc_ratio_dect_n1141_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1140_ins15370 | ALU | CIN | In | - | 2.148 | - |
| \asrc/ratio_dect/n1140_ins15370 | ALU | COUT | Out | 0.035 | 2.183 | - |
| asrc_ratio_dect_n1140_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1139_ins15371 | ALU | CIN | In | - | 2.183 | - |
| \asrc/ratio_dect/n1139_ins15371 | ALU | COUT | Out | 0.035 | 2.218 | - |
| asrc_ratio_dect_n1139_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1138_ins15372 | ALU | CIN | In | - | 2.218 | - |
| \asrc/ratio_dect/n1138_ins15372 | ALU | COUT | Out | 0.035 | 2.254 | - |
| asrc_ratio_dect_n1138_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1137_ins15373 | ALU | CIN | In | - | 2.254 | - |
| \asrc/ratio_dect/n1137_ins15373 | ALU | COUT | Out | 0.035 | 2.289 | - |
| asrc_ratio_dect_n1137_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1136_ins15374 | ALU | CIN | In | - | 2.289 | - |
| \asrc/ratio_dect/n1136_ins15374 | ALU | COUT | Out | 0.035 | 2.324 | - |
| asrc_ratio_dect_n1136_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1135_ins15375 | ALU | CIN | In | - | 2.324 | - |
| \asrc/ratio_dect/n1135_ins15375 | ALU | COUT | Out | 0.035 | 2.359 | - |
| asrc_ratio_dect_n1135_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1134_ins15376 | ALU | CIN | In | - | 2.359 | - |
| \asrc/ratio_dect/n1134_ins15376 | ALU | COUT | Out | 0.035 | 2.394 | - |
| asrc_ratio_dect_n1134_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1133_ins15377 | ALU | CIN | In | - | 2.394 | - |
| \asrc/ratio_dect/n1133_ins15377 | ALU | COUT | Out | 0.035 | 2.430 | - |
| asrc_ratio_dect_n1133_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1132_ins15378 | ALU | CIN | In | - | 2.430 | - |
| \asrc/ratio_dect/n1132_ins15378 | ALU | COUT | Out | 0.035 | 2.465 | - |
| asrc_ratio_dect_n1132_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1131_ins15379 | ALU | CIN | In | - | 2.465 | - |
| \asrc/ratio_dect/n1131_ins15379 | ALU | COUT | Out | 0.035 | 2.500 | - |
| asrc_ratio_dect_n1131_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1130_ins15380 | ALU | CIN | In | - | 2.500 | - |
| \asrc/ratio_dect/n1130_ins15380 | ALU | COUT | Out | 0.035 | 2.535 | - |
| asrc_ratio_dect_n1130_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1129_ins15381 | ALU | CIN | In | - | 2.535 | - |
| \asrc/ratio_dect/n1129_ins15381 | ALU | COUT | Out | 0.035 | 2.570 | - |
| asrc_ratio_dect_n1129_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1128_ins15382 | ALU | CIN | In | - | 2.570 | - |
| \asrc/ratio_dect/n1128_ins15382 | ALU | COUT | Out | 0.035 | 2.606 | - |
| asrc_ratio_dect_n1128_4_COUT | Net | - | - | 0.000 | - | 1 |
| \asrc/ratio_dect/n1127_ins15383 | ALU | CIN | In | - | 2.606 | - |
| \asrc/ratio_dect/n1127_ins15383 | ALU | SUM | Out | 0.470 | 3.076 | - |
| asrc_ratio_dect_n1127 | Net | - | - | 0.237 | - | 1 |
| \asrc/ratio_dect/ratio_vari_21_ins13536 | DL | D | In | - | 3.313 | - |
Total Path Delay: 3.313
Logic Delay: 2.659(80.3%)
Route Delay: 0.654(19.7%)
Message
Info (EXT0100) : Run analyzation & elaborationInfo (EXT1482) : Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v'
Info (EXT1328) : Analyzing included file 'C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\temp\ASRC\define.vh'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:1618)
Info (EXT2320) : Back to file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:1618)
Info (EXT1328) : Analyzing included file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\static_macro_define.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:1)
Info (EXT2320) : Back to file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:1618)
Info (EXT1482) : Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v'
Info (EXT1328) : Analyzing included file 'C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\temp\ASRC\define.vh'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v:1)
Info (EXT2320) : Back to file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v:1)
Info (EXT1328) : Analyzing included file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\static_macro_define.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v:2)
Info (EXT2320) : Back to file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v:2)
Info (EXT1482) : Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\static_macro_define.v'
Info (EXT1018) : Compiling module 'ASRC_TOP'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc_wrap.v:4)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1330) : Actual bit length ** differs from formal bit length ** for port '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT1018) : Compiling module '**'(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT1209) : Expression size ** truncated to fit in target size **(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Warning (EXT3053) : Input port '**' remains unconnected for this instance(C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\ASRC\data\asrc.v:0)
Info (EXT0101) : Current top module is "ASRC_TOP"
Info (CVT0001) : Run conversion
Info (DIO0001) : Run device independent optimization
Info (DIO0006) : Register and gate optimizing before inferencing
Info (DSP0001) : DSP inferencing
Info (RAM0001) : RAM inferencing
Info (ATO0001) : Adder tree reduction
Info (ATO0002) : Rebuild ALU instances from adder tree nodes
Info (DIO0001) : Run device independent optimization
Info (DIO0007) : Register and gate optimizing before mapping
Info (MAP0001) : Run tech-mapping
Info (MAP0003) : Run logic optimization
Info (DIO0001) : Run device independent optimization
Info (SYN0009) : Write post-map netlist to file: C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\temp\ASRC\asrc.vg
Summary
| Total Warnings: | 12 |
| Total Informations: | 37 |
Synthesis completed successfully!
Process took 0h:1m:38s realtime, 0h:1m:36s cputime
Memory peak: 59.3MB