#Build: Synplify Pro (R) P-2019.09G-1, Build 284R, Feb 28 2020 #install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: NOA-PC # Mon May 18 22:53:00 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys HDL Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Verilog Compiler, Version comp2019q3p1, Build 317R, Built Apr 1 2020 10:50:36 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v" (library work) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\test_top.v" (library work) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\data_prom\data_prom.v" (library work) @I::"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v" (library work) Verilog syntax check successful! File C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v changed - recompiling Selecting top level module gw2a18 @N:CG364 : gw2a.v(2405) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... @N:CG364 : gw2a.v(113) | Synthesizing module LUT4 in library work. Running optimization stage 1 on LUT4 ....... @N:CG364 : gw2a.v(107) | Synthesizing module LUT3 in library work. Running optimization stage 1 on LUT3 ....... @N:CG364 : gw2a.v(360) | Synthesizing module INV in library work. Running optimization stage 1 on INV ....... @N:CG364 : gw2a.v(222) | Synthesizing module DFFCE in library work. Running optimization stage 1 on DFFCE ....... @N:CG364 : gw2a.v(27) | Synthesizing module MUX2_LUT5 in library work. Running optimization stage 1 on MUX2_LUT5 ....... @N:CG364 : gw2a.v(101) | Synthesizing module LUT2 in library work. Running optimization stage 1 on LUT2 ....... @N:CG364 : gw2a.v(288) | Synthesizing module DL in library work. Running optimization stage 1 on DL ....... @N:CG364 : gw2a.v(210) | Synthesizing module DFFPE in library work. Running optimization stage 1 on DFFPE ....... @N:CG364 : gw2a.v(216) | Synthesizing module DFFC in library work. Running optimization stage 1 on DFFC ....... @N:CG364 : gw2a.v(204) | Synthesizing module DFFP in library work. Running optimization stage 1 on DFFP ....... @N:CG364 : gw2a.v(143) | Synthesizing module ALU in library work. Running optimization stage 1 on ALU ....... @N:CG364 : gw2a.v(33) | Synthesizing module MUX2_LUT6 in library work. Running optimization stage 1 on MUX2_LUT6 ....... @N:CG364 : gw2a.v(174) | Synthesizing module DFFE in library work. Running optimization stage 1 on DFFE ....... @N:CG364 : gw2a.v(1150) | Synthesizing module SDP in library work. Running optimization stage 1 on SDP ....... @N:CG364 : gw2a.v(2397) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : gw2a.v(2401) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : asrc.v(21) | Synthesizing module \~average_filter.ASRC_TOP__26s_16s_1s in library work. Running optimization stage 1 on \~average_filter.ASRC_TOP__26s_16s_1s ....... @N:CG364 : asrc.v(2503) | Synthesizing module \~ratio_detection.ASRC_TOP__Z1 in library work. Running optimization stage 1 on \~ratio_detection.ASRC_TOP__Z1 ....... @N:CG364 : asrc.v(11924) | Synthesizing module \~frac_divider.ASRC_TOP__27s_27s_52s in library work. @W:CG360 : asrc.v(12192) | Removing wire N_216, as there is no assignment to it. Running optimization stage 1 on \~frac_divider.ASRC_TOP__27s_27s_52s ....... @N:CG364 : asrc.v(16208) | Synthesizing module \~shared_divider.ASRC_TOP__26s_24s_4194304s in library work. Running optimization stage 1 on \~shared_divider.ASRC_TOP__26s_24s_4194304s ....... @W:CL168 : asrc.v(18570) | Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : asrc.v(18567) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : gw2a.v(813) | Synthesizing module SDPB in library work. Running optimization stage 1 on SDPB ....... @N:CG364 : asrc.v(18575) | Synthesizing module \~MEM_SDPB.ASRC_TOP_ in library work. Running optimization stage 1 on \~MEM_SDPB.ASRC_TOP_ ....... @N:CG364 : asrc.v(18655) | Synthesizing module \~input_storage.ASRC_TOP__16_24s_512s_2s_1 in library work. Running optimization stage 1 on \~input_storage.ASRC_TOP__16_24s_512s_2s_1 ....... @N:CG364 : asrc.v(20499) | Synthesizing module \~MEM_SDPB.ASRC_TOP__0 in library work. Running optimization stage 1 on \~MEM_SDPB.ASRC_TOP__0 ....... @N:CG364 : asrc.v(20579) | Synthesizing module \~input_storage.ASRC_TOP__16_24s_512s_2s_0 in library work. @W:CG360 : asrc.v(20737) | Removing wire N_27, as there is no assignment to it. @W:CG360 : asrc.v(20738) | Removing wire N_26, as there is no assignment to it. @W:CG360 : asrc.v(20739) | Removing wire N_25, as there is no assignment to it. @W:CG360 : asrc.v(20740) | Removing wire N_24, as there is no assignment to it. @W:CG360 : asrc.v(20741) | Removing wire N_23, as there is no assignment to it. @W:CG360 : asrc.v(20742) | Removing wire N_22, as there is no assignment to it. @W:CG360 : asrc.v(20743) | Removing wire N_21, as there is no assignment to it. @W:CG360 : asrc.v(20744) | Removing wire N_20, as there is no assignment to it. @W:CG360 : asrc.v(20745) | Removing wire N_19, as there is no assignment to it. @W:CG360 : asrc.v(20746) | Removing wire N_18, as there is no assignment to it. @W:CG360 : asrc.v(20747) | Removing wire N_17, as there is no assignment to it. @W:CG360 : asrc.v(20748) | Removing wire N_16, as there is no assignment to it. @W:CG360 : asrc.v(20749) | Removing wire N_15, as there is no assignment to it. Running optimization stage 1 on \~input_storage.ASRC_TOP__16_24s_512s_2s_0 ....... @N:CG364 : gw2a.v(2194) | Synthesizing module MULT36X36 in library work. Running optimization stage 1 on MULT36X36 ....... @N:CG364 : gw2a.v(1473) | Synthesizing module pROM in library work. Running optimization stage 1 on pROM ....... @N:CG364 : asrc.v(21636) | Synthesizing module \~Coeff_pROM.ASRC_TOP_ in library work. Running optimization stage 1 on \~Coeff_pROM.ASRC_TOP_ ....... @W:CL168 : asrc.v(21888) | Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : asrc.v(21893) | Synthesizing module \~phase_interpolator.ASRC_TOP__35s_26s_24s_2048s_25s_2042893_2796203_8s_Z2 in library work. @W:CG360 : asrc.v(22880) | Removing wire N_678, as there is no assignment to it. Running optimization stage 1 on \~phase_interpolator.ASRC_TOP__35s_26s_24s_2048s_25s_2042893_2796203_8s_Z2 ....... @N:CG364 : asrc.v(36725) | Synthesizing module \~fir_filter.ASRC_TOP__35s_26s_24s_4s_2s in library work. Running optimization stage 1 on \~fir_filter.ASRC_TOP__35s_26s_24s_4s_2s ....... @N:CG364 : asrc.v(46126) | Synthesizing module \~asrc.ASRC_TOP__26s_24s_35s_16 in library work. Running optimization stage 1 on \~asrc.ASRC_TOP__26s_24s_35s_16 ....... @W:CL318 : asrc.v(46159) | *Output clkin_reg has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL168 : asrc.v(47350) | Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : asrc.v(47347) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : asrc.v(47355) | Synthesizing module ASRC_TOP in library work. Running optimization stage 1 on ASRC_TOP ....... @W:CL168 : asrc.v(47467) | Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : data_prom.v(8) | Synthesizing module Data_pROM in library work. @W:CS263 : data_prom.v(22) | Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 16. Adjust either the definition or the instantiation of this port. @W:CS263 : data_prom.v(95) | Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on Data_pROM ....... @N:CG364 : test_top.v(15) | Synthesizing module test_top in library work. Running optimization stage 1 on test_top ....... @N:CG364 : gw2a18.v(16) | Synthesizing module gw2a18 in library work. @W:CG360 : gw2a18.v(27) | Removing wire JTAG_TDO, as there is no assignment to it. @W:CG360 : gw2a18.v(28) | Removing wire JTAG_TMS, as there is no assignment to it. @W:CG360 : gw2a18.v(31) | Removing wire SPI_CS, as there is no assignment to it. @W:CG360 : gw2a18.v(33) | Removing wire SPI_MISO, as there is no assignment to it. Running optimization stage 1 on gw2a18 ....... @W:CL318 : gw2a18.v(27) | *Output JTAG_TDO has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : gw2a18.v(28) | *Output JTAG_TMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : gw2a18.v(31) | *Output SPI_CS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : gw2a18.v(33) | *Output SPI_MISO has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Running optimization stage 2 on gw2a18 ....... @W:CL246 : gw2a18.v(22) | Input port bits 4 to 2 of KEY[4:1] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : gw2a18.v(23) | Input port bits 4 to 2 of SW[4:1] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : gw2a18.v(18) | Input EXT_CLK is unused. @N:CL159 : gw2a18.v(19) | Input RST_N is unused. @N:CL159 : gw2a18.v(21) | Input LED is unused. @N:CL159 : gw2a18.v(26) | Input JTAG_TDI is unused. @N:CL159 : gw2a18.v(29) | Input JTAG_TCK is unused. @N:CL159 : gw2a18.v(32) | Input SPI_CLK is unused. @N:CL159 : gw2a18.v(34) | Input SPI_MOSI is unused. @W:CL158 : gw2a18.v(36) | Inout J11 is unused @W:CL158 : gw2a18.v(37) | Inout J10 is unused Running optimization stage 2 on test_top ....... Running optimization stage 2 on Data_pROM ....... Running optimization stage 2 on ASRC_TOP ....... Running optimization stage 2 on \~asrc.ASRC_TOP__26s_24s_35s_16 ....... Running optimization stage 2 on \~fir_filter.ASRC_TOP__35s_26s_24s_4s_2s ....... Running optimization stage 2 on \~phase_interpolator.ASRC_TOP__35s_26s_24s_2048s_25s_2042893_2796203_8s_Z2 ....... Running optimization stage 2 on \~Coeff_pROM.ASRC_TOP_ ....... Running optimization stage 2 on pROM ....... Running optimization stage 2 on MULT36X36 ....... Running optimization stage 2 on \~input_storage.ASRC_TOP__16_24s_512s_2s_0 ....... Running optimization stage 2 on \~MEM_SDPB.ASRC_TOP__0 ....... Running optimization stage 2 on \~input_storage.ASRC_TOP__16_24s_512s_2s_1 ....... Running optimization stage 2 on \~MEM_SDPB.ASRC_TOP_ ....... Running optimization stage 2 on SDPB ....... Running optimization stage 2 on \~shared_divider.ASRC_TOP__26s_24s_4194304s ....... Running optimization stage 2 on \~frac_divider.ASRC_TOP__27s_27s_52s ....... Running optimization stage 2 on \~ratio_detection.ASRC_TOP__Z1 ....... Running optimization stage 2 on \~average_filter.ASRC_TOP__26s_16s_1s ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on SDP ....... Running optimization stage 2 on DFFE ....... Running optimization stage 2 on MUX2_LUT6 ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on DL ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on GSR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:08s; Memory used current: 127MB peak: 128MB) Process took 0h:00m:07s realtime, 0h:00m:08s cputime Process completed successfully. # Mon May 18 22:53:08 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode @N:NF107 : gw2a18.v(16) | Selected library: work cell: gw2a18 view verilog as top level @N:NF107 : gw2a18.v(16) | Selected library: work cell: gw2a18 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 95MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:02s cputime Process completed successfully. # Mon May 18 22:53:09 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: ASRC_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:10s; Memory used current: 18MB peak: 18MB) Process took 0h:00m:09s realtime, 0h:00m:10s cputime Process completed successfully. # Mon May 18 22:53:10 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2019q3p1, Build 286R, Built Feb 28 2020 09:59:15 @N: : | Running in 64-bit mode File C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\synthesize\rev_1\synwork\ASRC_comp.srs changed - recompiling @N:NF107 : gw2a18.v(16) | Selected library: work cell: gw2a18 view verilog as top level @N:NF107 : gw2a18.v(16) | Selected library: work cell: gw2a18 view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 96MB peak: 96MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon May 18 22:53:12 2020 ###########################################################] # Mon May 18 22:53:12 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A:MF827 : | No constraint file specified. Linked File: ASRC_scck.rpt See clock summary report "C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\synthesize\rev_1\ASRC_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 137MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 137MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 138MB peak: 138MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 151MB) @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @N:MO111 : asrc.v(2578) | Tristate driver clkin_reg_1 (in view: work.\\\~ratio_detection\.ASRC_TOP__Z1\ (verilog)) on net clkin_reg_1 (in view: work.\\\~ratio_detection\.ASRC_TOP__Z1\ (verilog)) has its enable tied to GND. @N:MO111 : asrc.v(46159) | Tristate driver clkin_reg_1 (in view: work.\\\~asrc\.ASRC_TOP__26s_24s_35s_16\ (verilog)) on net clkin_reg_1 (in view: work.\\\~asrc\.ASRC_TOP__26s_24s_35s_16\ (verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(27) | Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(28) | Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(31) | Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(33) | Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND. Starting clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:09s; Memory used current: 233MB peak: 233MB) Finished clock optimization phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB) Finished netlist restructuring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:10s; Memory used current: 234MB peak: 234MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------- 0 - System 150.0 MHz 6.667 system system_clkgroup 0 0 - gw2a18|SYM_CLK 62.8 MHz 15.920 inferred Autoconstr_clkgroup_0 1901 0 - gw2a18|SW[1] 150.0 MHz 6.667 inferred Autoconstr_clkgroup_1 801 ===================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------- System 0 - - - - gw2a18|SYM_CLK 1901 SYM_CLK(port) test_top.clk_in.C - - gw2a18|SW[1] 801 SW[1](port) test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[6\].G test_top.clk_in.E test_top.cnt_cycle_clkin_4[4:0].SEL(mux) ===================================================================================================================================================================== @W:MT529 : asrc.v(1874) | Found inferred clock gw2a18|SYM_CLK which controls 1901 sequential elements including test_top.asrc.asrc.ratio_dect.ave_filter.data_reg_CR26_data_reg_CR26_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W:MT529 : asrc.v(1874) | Found inferred clock gw2a18|SW[1] which controls 801 sequential elements including test_top.asrc.asrc.ratio_dect.ave_filter.data_reg_CR26_data_reg_CR26_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 1927 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================================= Non-Gated/Non-Generated Clocks ============================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------------------- ClockId_0_0 SYM_CLK port 1901 test_top.mem_addr[9:0] ClockId_0_1 SW[1] port 26 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[22\] ========================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:MO111 : gw2a18.v(33) | Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(31) | Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(28) | Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(27) | Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:BN225 : | Writing default property annotation file C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\synthesize\rev_1\ASRC.sap. Starting constraint checker (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:18s; Memory used current: 234MB peak: 234MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:18s; Memory used current: 234MB peak: 234MB) Finished constraint checker (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:18s; Memory used current: 235MB peak: 235MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:19s; Memory used current: 156MB peak: 237MB) Process took 0h:00m:16s realtime, 0h:00m:19s cputime # Mon May 18 22:53:29 2020 ###########################################################] # Mon May 18 22:53:29 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: P-2019.09G-1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: NOA-PC Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1564R, Built Mar 4 2020 10:56:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 121MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 121MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 128MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 135MB peak: 137MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 227MB peak: 227MB) @N:MO111 : gw2a18.v(33) | Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(31) | Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(28) | Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : gw2a18.v(27) | Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[18] (in view: work.gw2a18(verilog)) on net J3[18] (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[17] (in view: work.gw2a18(verilog)) on net J3[17] (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[16] (in view: work.gw2a18(verilog)) on net J3[16] (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[15] (in view: work.gw2a18(verilog)) on net J3[15] (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[14] (in view: work.gw2a18(verilog)) on net J3[14] (in view: work.gw2a18(verilog)) has its enable tied to GND. @N:MO111 : | Tristate driver J3_t[13] (in view: work.gw2a18(verilog)) on net J3[13] (in view: work.gw2a18(verilog)) has its enable tied to GND. @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port Available hyper_sources - for debug and ip models None Found @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 265MB peak: 265MB) Starting factoring (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 237MB peak: 266MB) Finished factoring (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 238MB peak: 266MB) @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 239MB peak: 266MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 239MB peak: 266MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:21s; Memory used current: 239MB peak: 266MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:21s; Memory used current: 239MB peak: 266MB) Finished preparing to map (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:24s; Memory used current: 239MB peak: 266MB) @N:BN362 : asrc.v(8016) | Removing sequential instance test_top.asrc.asrc.ratio_dect.valid_cnt_clk_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. @W:BN114 : asrc.v(3759) | Removing instance test_top.asrc.asrc.ratio_dect.valid_cnt_clk_0_sqmuxa_cZ (in view: work.gw2a18(verilog)) of black box view:GOWIN.LUT4(PRIM) because it does not drive other instances. @N:BN362 : asrc.v(8008) | Removing sequential instance test_top.asrc.asrc.ratio_dect.valid_cnt_clkin_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. Finished technology mapping (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:26s; Memory used current: 240MB peak: 266MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:28s -3.82ns 2281 / 37 2 0h:00m:28s -3.82ns 2281 / 37 3 0h:00m:30s -3.82ns 2281 / 37 4 0h:00m:31s -3.82ns 2281 / 37 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:32s; Memory used current: 240MB peak: 266MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @N:BN362 : asrc.v(8848) | Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst3_0 (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. @N:BN362 : asrc.v(8840) | Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst2_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. @N:BN362 : asrc.v(8832) | Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst1_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. @N:BN362 : asrc.v(8048) | Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances. @W:BN114 : asrc.v(4126) | Removing instance test_top.asrc.asrc.ratio_dect.N_630_i_cZ (in view: work.gw2a18(verilog)) of black box view:GOWIN.LUT4(PRIM) because it does not drive other instances. @W:BN709 : gw2a18.v(38) | Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port @W:BN709 : gw2a18.v(39) | Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port Finished restoring hierarchy (Real Time elapsed 0h:00m:42s; CPU Time elapsed 0h:00m:37s; Memory used current: 241MB peak: 266MB) Start Writing Netlists (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:39s; Memory used current: 156MB peak: 266MB) Writing Analyst data base C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\synthesize\rev_1\synwork\ASRC_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:52s; CPU Time elapsed 0h:00m:46s; Memory used current: 241MB peak: 266MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:01m:05s; CPU Time elapsed 0h:00m:59s; Memory used current: 242MB peak: 266MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:01m:06s; CPU Time elapsed 0h:01m:00s; Memory used current: 242MB peak: 266MB) Start final timing analysis (Real Time elapsed 0h:01m:11s; CPU Time elapsed 0h:01m:05s; Memory used current: 236MB peak: 266MB) @W:MT420 : | Found inferred clock gw2a18|SYM_CLK with period 9.28ns. Please declare a user-defined clock on port SYM_CLK. @W:MT420 : | Found inferred clock gw2a18|SW[1] with period 6.67ns. Please declare a user-defined clock on port SW[1]. ##### START OF TIMING REPORT #####[ # Timing report written on Mon May 18 22:54:41 2020 # Top view: gw2a18 Requested Frequency: 107.7 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.639 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------ gw2a18|SW[1] 150.0 MHz NA 6.667 NA NA inferred Autoconstr_clkgroup_1 gw2a18|SYM_CLK 107.7 MHz 91.5 MHz 9.285 10.923 -1.639 inferred Autoconstr_clkgroup_0 System 150.0 MHz 403.9 MHz 6.667 2.476 4.191 system system_clkgroup ======================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------- System gw2a18|SYM_CLK | 9.285 5.461 | No paths - | No paths - | No paths - System gw2a18|SW[1] | No paths - | No paths - | 6.667 4.191 | No paths - gw2a18|SYM_CLK System | 9.285 6.262 | No paths - | No paths - | No paths - gw2a18|SYM_CLK gw2a18|SYM_CLK | 9.285 -1.639 | No paths - | No paths - | No paths - gw2a18|SYM_CLK gw2a18|SW[1] | No paths - | No paths - | Diff grp - | No paths - gw2a18|SW[1] gw2a18|SYM_CLK | Diff grp - | No paths - | No paths - | No paths - ======================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: gw2a18|SYM_CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] gw2a18|SYM_CLK DFFC Q write_addr[0] 0.243 -1.639 test_top.asrc.asrc.input_storage1.\\read_addr_Z\[0\] gw2a18|SYM_CLK DFFC Q read_addr[0] 0.243 -1.617 test_top.asrc.asrc.input_storage1.\\write_addr_Z\[1\] gw2a18|SYM_CLK DFFC Q write_addr[1] 0.243 -1.603 test_top.asrc.asrc.input_storage1.\\read_addr_Z\[1\] gw2a18|SYM_CLK DFFC Q read_addr[1] 0.243 -1.583 test_top.asrc.asrc.input_storage0.\\write_addr_Z\[0\] gw2a18|SYM_CLK DFFC Q write_addr[0] 0.243 -1.571 test_top.asrc.asrc.input_storage1.\\write_addr_Z\[2\] gw2a18|SYM_CLK DFFC Q write_addr[2] 0.243 -1.569 test_top.asrc.asrc.input_storage0.\\read_addr_Z\[0\] gw2a18|SYM_CLK DFFC Q read_addr[0] 0.243 -1.550 test_top.asrc.asrc.input_storage1.\\read_addr_Z\[2\] gw2a18|SYM_CLK DFFC Q read_addr[2] 0.243 -1.548 test_top.asrc.asrc.input_storage0.\\write_addr_Z\[1\] gw2a18|SYM_CLK DFFC Q write_addr[1] 0.243 -1.536 test_top.asrc.asrc.input_storage1.\\write_addr_Z\[3\] gw2a18|SYM_CLK DFFC Q write_addr[3] 0.243 -1.534 ================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] gw2a18|SYM_CLK DFFCE D mult_acc0_5[34] 9.224 -1.639 test_top.asrc.asrc.fir_filter.\\mult_acc1_Z\[34\] gw2a18|SYM_CLK DFFCE D mult_acc1_5[34] 9.224 -1.639 test_top.asrc.asrc.fir_filter.\\mult_acc2_Z\[34\] gw2a18|SYM_CLK DFFCE D mult_acc2_5[34] 9.224 -1.639 test_top.asrc.asrc.fir_filter.\\mult_acc3_Z\[34\] gw2a18|SYM_CLK DFFCE D mult_acc3_5[34] 9.224 -1.639 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] gw2a18|SYM_CLK MULT36X36 B[30] mult_b[30] 4.944 -1.639 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] gw2a18|SYM_CLK MULT36X36 B[31] mult_b[31] 4.944 -1.639 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] gw2a18|SYM_CLK MULT36X36 B[32] mult_b[32] 4.944 -1.639 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] gw2a18|SYM_CLK MULT36X36 B[33] mult_b[33] 4.944 -1.639 test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[33\] gw2a18|SYM_CLK DFFCE D mult_acc0_5[33] 9.224 -1.603 test_top.asrc.asrc.fir_filter.\\mult_acc1_Z\[33\] gw2a18|SYM_CLK DFFCE D mult_acc1_5[33] 9.224 -1.603 ==================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 9.285 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.224 - Propagation time: 10.862 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.639 Number of logic level(s): 50 Starting point: test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] / Q Ending point: test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] / D The start point is clocked by gw2a18|SYM_CLK [rising] on pin CLK The end point is clocked by gw2a18|SYM_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] DFFC Q Out 0.243 0.243 - write_addr[0] Net - - 0.535 - 7 test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU I1 In - 0.778 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU COUT Out 0.570 1.348 - un2_out_data_cry_0_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU CIN In - 1.348 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU COUT Out 0.035 1.383 - un2_out_data_cry_1_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU CIN In - 1.383 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU COUT Out 0.035 1.418 - un2_out_data_cry_2_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU CIN In - 1.418 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU COUT Out 0.035 1.453 - un2_out_data_cry_3_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU CIN In - 1.453 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU COUT Out 0.035 1.488 - un2_out_data_cry_4_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU CIN In - 1.488 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU COUT Out 0.035 1.523 - un2_out_data_cry_5_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU CIN In - 1.523 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU COUT Out 0.035 1.558 - un2_out_data_cry_6_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU CIN In - 1.558 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU COUT Out 0.035 1.593 - un2_out_data_cry_7_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU CIN In - 1.593 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU COUT Out 0.035 1.628 - un2_out_data_cry_8_0_COUT_0 Net - - 0.961 - 1 test_top.asrc.asrc.input_storage1.out_data_1 LUT4 I2 In - 2.589 - test_top.asrc.asrc.input_storage1.out_data_1 LUT4 F Out 0.462 3.051 - out_data_1_0 Net - - 0.657 - 23 test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 I3 In - 3.708 - test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 F Out 0.371 4.079 - mult_b_a0_3[30] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[30\] LUT4 I2 In - 4.614 - test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[30\] LUT4 F Out 0.462 5.076 - mult_b_8_1[30] Net - - 0.401 - 1 test_top.asrc.asrc.fir_filter.\\mult_b_8\[30\] LUT4 I1 In - 5.477 - test_top.asrc.asrc.fir_filter.\\mult_b_8\[30\] LUT4 F Out 0.570 6.047 - mult_b[30] Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 B[30] In - 6.582 - test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 DOUT[36] Out 0.466 7.048 - mult_out[36] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU I1 In - 7.583 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU COUT Out 0.570 8.153 - un2_mult_acc0_cry_0_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU CIN In - 8.153 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU COUT Out 0.035 8.188 - un2_mult_acc0_cry_1_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU CIN In - 8.188 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU COUT Out 0.035 8.223 - un2_mult_acc0_cry_2_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU CIN In - 8.223 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU COUT Out 0.035 8.258 - un2_mult_acc0_cry_3_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU CIN In - 8.258 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU COUT Out 0.035 8.293 - un2_mult_acc0_cry_4_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU CIN In - 8.293 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU COUT Out 0.035 8.328 - un2_mult_acc0_cry_5_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU CIN In - 8.328 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU COUT Out 0.035 8.363 - un2_mult_acc0_cry_6_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU CIN In - 8.363 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU COUT Out 0.035 8.398 - un2_mult_acc0_cry_7_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU CIN In - 8.398 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU COUT Out 0.035 8.433 - un2_mult_acc0_cry_8_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU CIN In - 8.433 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU COUT Out 0.035 8.468 - un2_mult_acc0_cry_9_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU CIN In - 8.468 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU COUT Out 0.035 8.503 - un2_mult_acc0_cry_10_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU CIN In - 8.503 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU COUT Out 0.035 8.538 - un2_mult_acc0_cry_11_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU CIN In - 8.538 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU COUT Out 0.035 8.573 - un2_mult_acc0_cry_12_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU CIN In - 8.573 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU COUT Out 0.035 8.608 - un2_mult_acc0_cry_13_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU CIN In - 8.608 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU COUT Out 0.035 8.643 - un2_mult_acc0_cry_14_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU CIN In - 8.643 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU COUT Out 0.035 8.678 - un2_mult_acc0_cry_15_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU CIN In - 8.678 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU COUT Out 0.035 8.713 - un2_mult_acc0_cry_16_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU CIN In - 8.713 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU COUT Out 0.035 8.748 - un2_mult_acc0_cry_17_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU CIN In - 8.748 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU COUT Out 0.035 8.783 - un2_mult_acc0_cry_18_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU CIN In - 8.783 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU COUT Out 0.035 8.818 - un2_mult_acc0_cry_19_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU CIN In - 8.818 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU COUT Out 0.035 8.853 - un2_mult_acc0_cry_20_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU CIN In - 8.853 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU COUT Out 0.035 8.888 - un2_mult_acc0_cry_21_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU CIN In - 8.888 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU COUT Out 0.035 8.923 - un2_mult_acc0_cry_22_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU CIN In - 8.923 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU COUT Out 0.035 8.958 - un2_mult_acc0_cry_23_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU CIN In - 8.958 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU COUT Out 0.035 8.993 - un2_mult_acc0_cry_24_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU CIN In - 8.993 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU COUT Out 0.035 9.028 - un2_mult_acc0_cry_25_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU CIN In - 9.028 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU COUT Out 0.035 9.063 - un2_mult_acc0_cry_26_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU CIN In - 9.063 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU COUT Out 0.035 9.098 - un2_mult_acc0_cry_27_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU CIN In - 9.098 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU COUT Out 0.035 9.133 - un2_mult_acc0_cry_28_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU CIN In - 9.133 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU COUT Out 0.035 9.168 - un2_mult_acc0_cry_29_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU CIN In - 9.168 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU COUT Out 0.035 9.203 - un2_mult_acc0_cry_30_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU CIN In - 9.203 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU COUT Out 0.035 9.238 - un2_mult_acc0_cry_31_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU CIN In - 9.238 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU COUT Out 0.035 9.273 - un2_mult_acc0_cry_32_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU CIN In - 9.273 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU COUT Out 0.035 9.308 - un2_mult_acc0_cry_33_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU CIN In - 9.308 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU SUM Out 0.470 9.778 - un2_mult_acc0_s_34_0_SUM Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 I0 In - 10.313 - test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 F Out 0.549 10.862 - mult_acc0_5[34] Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] DFFCE D In - 10.862 - ===================================================================================================================================== Total path delay (propagation time + setup) of 10.923 is 6.229(57.0%) logic and 4.694(43.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 9.285 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.224 - Propagation time: 10.862 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.639 Number of logic level(s): 50 Starting point: test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] / Q Ending point: test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] / D The start point is clocked by gw2a18|SYM_CLK [rising] on pin CLK The end point is clocked by gw2a18|SYM_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] DFFC Q Out 0.243 0.243 - write_addr[0] Net - - 0.535 - 7 test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU I1 In - 0.778 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU COUT Out 0.570 1.348 - un2_out_data_cry_0_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU CIN In - 1.348 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU COUT Out 0.035 1.383 - un2_out_data_cry_1_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU CIN In - 1.383 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU COUT Out 0.035 1.418 - un2_out_data_cry_2_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU CIN In - 1.418 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU COUT Out 0.035 1.453 - un2_out_data_cry_3_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU CIN In - 1.453 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU COUT Out 0.035 1.488 - un2_out_data_cry_4_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU CIN In - 1.488 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU COUT Out 0.035 1.523 - un2_out_data_cry_5_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU CIN In - 1.523 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU COUT Out 0.035 1.558 - un2_out_data_cry_6_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU CIN In - 1.558 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU COUT Out 0.035 1.593 - un2_out_data_cry_7_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU CIN In - 1.593 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU COUT Out 0.035 1.628 - un2_out_data_cry_8_0_COUT_0 Net - - 0.961 - 1 test_top.asrc.asrc.input_storage1.out_data_1 LUT4 I2 In - 2.589 - test_top.asrc.asrc.input_storage1.out_data_1 LUT4 F Out 0.462 3.051 - out_data_1_0 Net - - 0.657 - 23 test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 I3 In - 3.708 - test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 F Out 0.371 4.079 - mult_b_a0_3[30] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[32\] LUT4 I2 In - 4.614 - test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[32\] LUT4 F Out 0.462 5.076 - mult_b_8_1[32] Net - - 0.401 - 1 test_top.asrc.asrc.fir_filter.\\mult_b_8\[32\] LUT4 I1 In - 5.477 - test_top.asrc.asrc.fir_filter.\\mult_b_8\[32\] LUT4 F Out 0.570 6.047 - mult_b[32] Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 B[32] In - 6.582 - test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 DOUT[36] Out 0.466 7.048 - mult_out[36] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU I1 In - 7.583 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU COUT Out 0.570 8.153 - un2_mult_acc0_cry_0_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU CIN In - 8.153 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU COUT Out 0.035 8.188 - un2_mult_acc0_cry_1_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU CIN In - 8.188 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU COUT Out 0.035 8.223 - un2_mult_acc0_cry_2_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU CIN In - 8.223 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU COUT Out 0.035 8.258 - un2_mult_acc0_cry_3_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU CIN In - 8.258 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU COUT Out 0.035 8.293 - un2_mult_acc0_cry_4_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU CIN In - 8.293 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU COUT Out 0.035 8.328 - un2_mult_acc0_cry_5_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU CIN In - 8.328 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU COUT Out 0.035 8.363 - un2_mult_acc0_cry_6_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU CIN In - 8.363 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU COUT Out 0.035 8.398 - un2_mult_acc0_cry_7_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU CIN In - 8.398 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU COUT Out 0.035 8.433 - un2_mult_acc0_cry_8_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU CIN In - 8.433 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU COUT Out 0.035 8.468 - un2_mult_acc0_cry_9_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU CIN In - 8.468 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU COUT Out 0.035 8.503 - un2_mult_acc0_cry_10_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU CIN In - 8.503 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU COUT Out 0.035 8.538 - un2_mult_acc0_cry_11_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU CIN In - 8.538 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU COUT Out 0.035 8.573 - un2_mult_acc0_cry_12_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU CIN In - 8.573 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU COUT Out 0.035 8.608 - un2_mult_acc0_cry_13_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU CIN In - 8.608 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU COUT Out 0.035 8.643 - un2_mult_acc0_cry_14_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU CIN In - 8.643 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU COUT Out 0.035 8.678 - un2_mult_acc0_cry_15_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU CIN In - 8.678 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU COUT Out 0.035 8.713 - un2_mult_acc0_cry_16_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU CIN In - 8.713 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU COUT Out 0.035 8.748 - un2_mult_acc0_cry_17_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU CIN In - 8.748 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU COUT Out 0.035 8.783 - un2_mult_acc0_cry_18_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU CIN In - 8.783 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU COUT Out 0.035 8.818 - un2_mult_acc0_cry_19_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU CIN In - 8.818 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU COUT Out 0.035 8.853 - un2_mult_acc0_cry_20_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU CIN In - 8.853 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU COUT Out 0.035 8.888 - un2_mult_acc0_cry_21_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU CIN In - 8.888 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU COUT Out 0.035 8.923 - un2_mult_acc0_cry_22_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU CIN In - 8.923 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU COUT Out 0.035 8.958 - un2_mult_acc0_cry_23_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU CIN In - 8.958 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU COUT Out 0.035 8.993 - un2_mult_acc0_cry_24_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU CIN In - 8.993 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU COUT Out 0.035 9.028 - un2_mult_acc0_cry_25_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU CIN In - 9.028 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU COUT Out 0.035 9.063 - un2_mult_acc0_cry_26_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU CIN In - 9.063 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU COUT Out 0.035 9.098 - un2_mult_acc0_cry_27_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU CIN In - 9.098 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU COUT Out 0.035 9.133 - un2_mult_acc0_cry_28_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU CIN In - 9.133 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU COUT Out 0.035 9.168 - un2_mult_acc0_cry_29_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU CIN In - 9.168 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU COUT Out 0.035 9.203 - un2_mult_acc0_cry_30_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU CIN In - 9.203 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU COUT Out 0.035 9.238 - un2_mult_acc0_cry_31_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU CIN In - 9.238 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU COUT Out 0.035 9.273 - un2_mult_acc0_cry_32_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU CIN In - 9.273 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU COUT Out 0.035 9.308 - un2_mult_acc0_cry_33_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU CIN In - 9.308 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU SUM Out 0.470 9.778 - un2_mult_acc0_s_34_0_SUM Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 I0 In - 10.313 - test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 F Out 0.549 10.862 - mult_acc0_5[34] Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] DFFCE D In - 10.862 - ===================================================================================================================================== Total path delay (propagation time + setup) of 10.923 is 6.229(57.0%) logic and 4.694(43.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 9.285 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.224 - Propagation time: 10.862 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.639 Number of logic level(s): 50 Starting point: test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] / Q Ending point: test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] / D The start point is clocked by gw2a18|SYM_CLK [rising] on pin CLK The end point is clocked by gw2a18|SYM_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] DFFC Q Out 0.243 0.243 - write_addr[0] Net - - 0.535 - 7 test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU I1 In - 0.778 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU COUT Out 0.570 1.348 - un2_out_data_cry_0_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU CIN In - 1.348 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU COUT Out 0.035 1.383 - un2_out_data_cry_1_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU CIN In - 1.383 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU COUT Out 0.035 1.418 - un2_out_data_cry_2_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU CIN In - 1.418 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU COUT Out 0.035 1.453 - un2_out_data_cry_3_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU CIN In - 1.453 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU COUT Out 0.035 1.488 - un2_out_data_cry_4_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU CIN In - 1.488 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU COUT Out 0.035 1.523 - un2_out_data_cry_5_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU CIN In - 1.523 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU COUT Out 0.035 1.558 - un2_out_data_cry_6_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU CIN In - 1.558 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU COUT Out 0.035 1.593 - un2_out_data_cry_7_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU CIN In - 1.593 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU COUT Out 0.035 1.628 - un2_out_data_cry_8_0_COUT_0 Net - - 0.961 - 1 test_top.asrc.asrc.input_storage1.out_data_1 LUT4 I2 In - 2.589 - test_top.asrc.asrc.input_storage1.out_data_1 LUT4 F Out 0.462 3.051 - out_data_1_0 Net - - 0.657 - 23 test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 I3 In - 3.708 - test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 F Out 0.371 4.079 - mult_b_a0_3[30] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[31\] LUT4 I2 In - 4.614 - test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[31\] LUT4 F Out 0.462 5.076 - mult_b_8_1[31] Net - - 0.401 - 1 test_top.asrc.asrc.fir_filter.\\mult_b_8\[31\] LUT4 I1 In - 5.477 - test_top.asrc.asrc.fir_filter.\\mult_b_8\[31\] LUT4 F Out 0.570 6.047 - mult_b[31] Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 B[31] In - 6.582 - test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 DOUT[36] Out 0.466 7.048 - mult_out[36] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU I1 In - 7.583 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU COUT Out 0.570 8.153 - un2_mult_acc0_cry_0_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU CIN In - 8.153 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU COUT Out 0.035 8.188 - un2_mult_acc0_cry_1_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU CIN In - 8.188 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU COUT Out 0.035 8.223 - un2_mult_acc0_cry_2_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU CIN In - 8.223 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU COUT Out 0.035 8.258 - un2_mult_acc0_cry_3_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU CIN In - 8.258 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU COUT Out 0.035 8.293 - un2_mult_acc0_cry_4_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU CIN In - 8.293 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU COUT Out 0.035 8.328 - un2_mult_acc0_cry_5_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU CIN In - 8.328 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU COUT Out 0.035 8.363 - un2_mult_acc0_cry_6_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU CIN In - 8.363 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU COUT Out 0.035 8.398 - un2_mult_acc0_cry_7_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU CIN In - 8.398 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU COUT Out 0.035 8.433 - un2_mult_acc0_cry_8_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU CIN In - 8.433 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU COUT Out 0.035 8.468 - un2_mult_acc0_cry_9_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU CIN In - 8.468 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU COUT Out 0.035 8.503 - un2_mult_acc0_cry_10_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU CIN In - 8.503 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU COUT Out 0.035 8.538 - un2_mult_acc0_cry_11_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU CIN In - 8.538 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU COUT Out 0.035 8.573 - un2_mult_acc0_cry_12_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU CIN In - 8.573 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU COUT Out 0.035 8.608 - un2_mult_acc0_cry_13_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU CIN In - 8.608 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU COUT Out 0.035 8.643 - un2_mult_acc0_cry_14_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU CIN In - 8.643 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU COUT Out 0.035 8.678 - un2_mult_acc0_cry_15_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU CIN In - 8.678 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU COUT Out 0.035 8.713 - un2_mult_acc0_cry_16_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU CIN In - 8.713 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU COUT Out 0.035 8.748 - un2_mult_acc0_cry_17_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU CIN In - 8.748 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU COUT Out 0.035 8.783 - un2_mult_acc0_cry_18_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU CIN In - 8.783 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU COUT Out 0.035 8.818 - un2_mult_acc0_cry_19_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU CIN In - 8.818 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU COUT Out 0.035 8.853 - un2_mult_acc0_cry_20_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU CIN In - 8.853 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU COUT Out 0.035 8.888 - un2_mult_acc0_cry_21_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU CIN In - 8.888 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU COUT Out 0.035 8.923 - un2_mult_acc0_cry_22_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU CIN In - 8.923 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU COUT Out 0.035 8.958 - un2_mult_acc0_cry_23_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU CIN In - 8.958 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU COUT Out 0.035 8.993 - un2_mult_acc0_cry_24_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU CIN In - 8.993 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU COUT Out 0.035 9.028 - un2_mult_acc0_cry_25_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU CIN In - 9.028 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU COUT Out 0.035 9.063 - un2_mult_acc0_cry_26_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU CIN In - 9.063 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU COUT Out 0.035 9.098 - un2_mult_acc0_cry_27_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU CIN In - 9.098 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU COUT Out 0.035 9.133 - un2_mult_acc0_cry_28_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU CIN In - 9.133 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU COUT Out 0.035 9.168 - un2_mult_acc0_cry_29_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU CIN In - 9.168 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU COUT Out 0.035 9.203 - un2_mult_acc0_cry_30_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU CIN In - 9.203 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU COUT Out 0.035 9.238 - un2_mult_acc0_cry_31_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU CIN In - 9.238 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU COUT Out 0.035 9.273 - un2_mult_acc0_cry_32_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU CIN In - 9.273 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU COUT Out 0.035 9.308 - un2_mult_acc0_cry_33_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU CIN In - 9.308 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU SUM Out 0.470 9.778 - un2_mult_acc0_s_34_0_SUM Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 I0 In - 10.313 - test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 F Out 0.549 10.862 - mult_acc0_5[34] Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] DFFCE D In - 10.862 - ===================================================================================================================================== Total path delay (propagation time + setup) of 10.923 is 6.229(57.0%) logic and 4.694(43.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 9.285 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.224 - Propagation time: 10.862 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.639 Number of logic level(s): 50 Starting point: test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] / Q Ending point: test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] / D The start point is clocked by gw2a18|SYM_CLK [rising] on pin CLK The end point is clocked by gw2a18|SYM_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] DFFC Q Out 0.243 0.243 - write_addr[0] Net - - 0.535 - 7 test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU I1 In - 0.778 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU COUT Out 0.570 1.348 - un2_out_data_cry_0_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU CIN In - 1.348 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU COUT Out 0.035 1.383 - un2_out_data_cry_1_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU CIN In - 1.383 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU COUT Out 0.035 1.418 - un2_out_data_cry_2_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU CIN In - 1.418 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU COUT Out 0.035 1.453 - un2_out_data_cry_3_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU CIN In - 1.453 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU COUT Out 0.035 1.488 - un2_out_data_cry_4_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU CIN In - 1.488 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU COUT Out 0.035 1.523 - un2_out_data_cry_5_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU CIN In - 1.523 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU COUT Out 0.035 1.558 - un2_out_data_cry_6_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU CIN In - 1.558 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU COUT Out 0.035 1.593 - un2_out_data_cry_7_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU CIN In - 1.593 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU COUT Out 0.035 1.628 - un2_out_data_cry_8_0_COUT_0 Net - - 0.961 - 1 test_top.asrc.asrc.input_storage1.out_data_1 LUT4 I2 In - 2.589 - test_top.asrc.asrc.input_storage1.out_data_1 LUT4 F Out 0.462 3.051 - out_data_1_0 Net - - 0.657 - 23 test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 I3 In - 3.708 - test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 F Out 0.371 4.079 - mult_b_a0_3[30] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[33\] LUT4 I2 In - 4.614 - test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[33\] LUT4 F Out 0.462 5.076 - mult_b_8_1[33] Net - - 0.401 - 1 test_top.asrc.asrc.fir_filter.\\mult_b_8\[33\] LUT4 I1 In - 5.477 - test_top.asrc.asrc.fir_filter.\\mult_b_8\[33\] LUT4 F Out 0.570 6.047 - mult_b[33] Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 B[33] In - 6.582 - test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 DOUT[36] Out 0.466 7.048 - mult_out[36] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU I1 In - 7.583 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_0_0 ALU COUT Out 0.570 8.153 - un2_mult_acc0_cry_0_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU CIN In - 8.153 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_1_0 ALU COUT Out 0.035 8.188 - un2_mult_acc0_cry_1_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU CIN In - 8.188 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_2_0 ALU COUT Out 0.035 8.223 - un2_mult_acc0_cry_2_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU CIN In - 8.223 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_3_0 ALU COUT Out 0.035 8.258 - un2_mult_acc0_cry_3_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU CIN In - 8.258 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_4_0 ALU COUT Out 0.035 8.293 - un2_mult_acc0_cry_4_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU CIN In - 8.293 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_5_0 ALU COUT Out 0.035 8.328 - un2_mult_acc0_cry_5_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU CIN In - 8.328 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_6_0 ALU COUT Out 0.035 8.363 - un2_mult_acc0_cry_6_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU CIN In - 8.363 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_7_0 ALU COUT Out 0.035 8.398 - un2_mult_acc0_cry_7_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU CIN In - 8.398 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_8_0 ALU COUT Out 0.035 8.433 - un2_mult_acc0_cry_8_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU CIN In - 8.433 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_9_0 ALU COUT Out 0.035 8.468 - un2_mult_acc0_cry_9_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU CIN In - 8.468 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_10_0 ALU COUT Out 0.035 8.503 - un2_mult_acc0_cry_10_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU CIN In - 8.503 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_11_0 ALU COUT Out 0.035 8.538 - un2_mult_acc0_cry_11_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU CIN In - 8.538 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_12_0 ALU COUT Out 0.035 8.573 - un2_mult_acc0_cry_12_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU CIN In - 8.573 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_13_0 ALU COUT Out 0.035 8.608 - un2_mult_acc0_cry_13_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU CIN In - 8.608 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_14_0 ALU COUT Out 0.035 8.643 - un2_mult_acc0_cry_14_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU CIN In - 8.643 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_15_0 ALU COUT Out 0.035 8.678 - un2_mult_acc0_cry_15_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU CIN In - 8.678 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_16_0 ALU COUT Out 0.035 8.713 - un2_mult_acc0_cry_16_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU CIN In - 8.713 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_17_0 ALU COUT Out 0.035 8.748 - un2_mult_acc0_cry_17_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU CIN In - 8.748 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_18_0 ALU COUT Out 0.035 8.783 - un2_mult_acc0_cry_18_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU CIN In - 8.783 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_19_0 ALU COUT Out 0.035 8.818 - un2_mult_acc0_cry_19_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU CIN In - 8.818 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_20_0 ALU COUT Out 0.035 8.853 - un2_mult_acc0_cry_20_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU CIN In - 8.853 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_21_0 ALU COUT Out 0.035 8.888 - un2_mult_acc0_cry_21_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU CIN In - 8.888 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_22_0 ALU COUT Out 0.035 8.923 - un2_mult_acc0_cry_22_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU CIN In - 8.923 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_23_0 ALU COUT Out 0.035 8.958 - un2_mult_acc0_cry_23_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU CIN In - 8.958 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_24_0 ALU COUT Out 0.035 8.993 - un2_mult_acc0_cry_24_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU CIN In - 8.993 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_25_0 ALU COUT Out 0.035 9.028 - un2_mult_acc0_cry_25_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU CIN In - 9.028 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_26_0 ALU COUT Out 0.035 9.063 - un2_mult_acc0_cry_26_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU CIN In - 9.063 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_27_0 ALU COUT Out 0.035 9.098 - un2_mult_acc0_cry_27_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU CIN In - 9.098 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_28_0 ALU COUT Out 0.035 9.133 - un2_mult_acc0_cry_28_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU CIN In - 9.133 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_29_0 ALU COUT Out 0.035 9.168 - un2_mult_acc0_cry_29_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU CIN In - 9.168 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_30_0 ALU COUT Out 0.035 9.203 - un2_mult_acc0_cry_30_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU CIN In - 9.203 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_31_0 ALU COUT Out 0.035 9.238 - un2_mult_acc0_cry_31_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU CIN In - 9.238 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_32_0 ALU COUT Out 0.035 9.273 - un2_mult_acc0_cry_32_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU CIN In - 9.273 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_cry_33_0 ALU COUT Out 0.035 9.308 - un2_mult_acc0_cry_33_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU CIN In - 9.308 - test_top.asrc.asrc.fir_filter.un2_mult_acc0_s_34_0 ALU SUM Out 0.470 9.778 - un2_mult_acc0_s_34_0_SUM Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 I0 In - 10.313 - test_top.asrc.asrc.fir_filter.\\mult_acc0_5_cZ\[34\] LUT2 F Out 0.549 10.862 - mult_acc0_5[34] Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc0_Z\[34\] DFFCE D In - 10.862 - ===================================================================================================================================== Total path delay (propagation time + setup) of 10.923 is 6.229(57.0%) logic and 4.694(43.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 9.285 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.224 - Propagation time: 10.862 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.639 Number of logic level(s): 50 Starting point: test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] / Q Ending point: test_top.asrc.asrc.fir_filter.\\mult_acc1_Z\[34\] / D The start point is clocked by gw2a18|SYM_CLK [rising] on pin CLK The end point is clocked by gw2a18|SYM_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.input_storage1.\\write_addr_Z\[0\] DFFC Q Out 0.243 0.243 - write_addr[0] Net - - 0.535 - 7 test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU I1 In - 0.778 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_0_0 ALU COUT Out 0.570 1.348 - un2_out_data_cry_0_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU CIN In - 1.348 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_1_0 ALU COUT Out 0.035 1.383 - un2_out_data_cry_1_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU CIN In - 1.383 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_2_0 ALU COUT Out 0.035 1.418 - un2_out_data_cry_2_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU CIN In - 1.418 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_3_0 ALU COUT Out 0.035 1.453 - un2_out_data_cry_3_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU CIN In - 1.453 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_4_0 ALU COUT Out 0.035 1.488 - un2_out_data_cry_4_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU CIN In - 1.488 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_5_0 ALU COUT Out 0.035 1.523 - un2_out_data_cry_5_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU CIN In - 1.523 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_6_0 ALU COUT Out 0.035 1.558 - un2_out_data_cry_6_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU CIN In - 1.558 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_7_0 ALU COUT Out 0.035 1.593 - un2_out_data_cry_7_0_COUT_0 Net - - 0.000 - 1 test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU CIN In - 1.593 - test_top.asrc.asrc.input_storage1.un2_out_data_cry_8_0 ALU COUT Out 0.035 1.628 - un2_out_data_cry_8_0_COUT_0 Net - - 0.961 - 1 test_top.asrc.asrc.input_storage1.out_data_1 LUT4 I2 In - 2.589 - test_top.asrc.asrc.input_storage1.out_data_1 LUT4 F Out 0.462 3.051 - out_data_1_0 Net - - 0.657 - 23 test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 I3 In - 3.708 - test_top.asrc.asrc.fir_filter.\\mult_b_a0_3_cZ\[30\] LUT4 F Out 0.371 4.079 - mult_b_a0_3[30] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[30\] LUT4 I2 In - 4.614 - test_top.asrc.asrc.fir_filter.\\mult_b_8_1_cZ\[30\] LUT4 F Out 0.462 5.076 - mult_b_8_1[30] Net - - 0.401 - 1 test_top.asrc.asrc.fir_filter.\\mult_b_8\[30\] LUT4 I1 In - 5.477 - test_top.asrc.asrc.fir_filter.\\mult_b_8\[30\] LUT4 F Out 0.570 6.047 - mult_b[30] Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 B[30] In - 6.582 - test_top.asrc.asrc.fir_filter.\\mult_out_2_mulonly_0\[69\:0\] MULT36X36 DOUT[36] Out 0.466 7.048 - mult_out[36] Net - - 0.535 - 4 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_0_0 ALU I1 In - 7.583 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_0_0 ALU COUT Out 0.570 8.153 - un2_mult_acc1_cry_0_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_1_0 ALU CIN In - 8.153 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_1_0 ALU COUT Out 0.035 8.188 - un2_mult_acc1_cry_1_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_2_0 ALU CIN In - 8.188 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_2_0 ALU COUT Out 0.035 8.223 - un2_mult_acc1_cry_2_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_3_0 ALU CIN In - 8.223 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_3_0 ALU COUT Out 0.035 8.258 - un2_mult_acc1_cry_3_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_4_0 ALU CIN In - 8.258 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_4_0 ALU COUT Out 0.035 8.293 - un2_mult_acc1_cry_4_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_5_0 ALU CIN In - 8.293 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_5_0 ALU COUT Out 0.035 8.328 - un2_mult_acc1_cry_5_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_6_0 ALU CIN In - 8.328 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_6_0 ALU COUT Out 0.035 8.363 - un2_mult_acc1_cry_6_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_7_0 ALU CIN In - 8.363 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_7_0 ALU COUT Out 0.035 8.398 - un2_mult_acc1_cry_7_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_8_0 ALU CIN In - 8.398 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_8_0 ALU COUT Out 0.035 8.433 - un2_mult_acc1_cry_8_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_9_0 ALU CIN In - 8.433 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_9_0 ALU COUT Out 0.035 8.468 - un2_mult_acc1_cry_9_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_10_0 ALU CIN In - 8.468 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_10_0 ALU COUT Out 0.035 8.503 - un2_mult_acc1_cry_10_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_11_0 ALU CIN In - 8.503 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_11_0 ALU COUT Out 0.035 8.538 - un2_mult_acc1_cry_11_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_12_0 ALU CIN In - 8.538 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_12_0 ALU COUT Out 0.035 8.573 - un2_mult_acc1_cry_12_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_13_0 ALU CIN In - 8.573 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_13_0 ALU COUT Out 0.035 8.608 - un2_mult_acc1_cry_13_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_14_0 ALU CIN In - 8.608 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_14_0 ALU COUT Out 0.035 8.643 - un2_mult_acc1_cry_14_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_15_0 ALU CIN In - 8.643 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_15_0 ALU COUT Out 0.035 8.678 - un2_mult_acc1_cry_15_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_16_0 ALU CIN In - 8.678 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_16_0 ALU COUT Out 0.035 8.713 - un2_mult_acc1_cry_16_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_17_0 ALU CIN In - 8.713 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_17_0 ALU COUT Out 0.035 8.748 - un2_mult_acc1_cry_17_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_18_0 ALU CIN In - 8.748 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_18_0 ALU COUT Out 0.035 8.783 - un2_mult_acc1_cry_18_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_19_0 ALU CIN In - 8.783 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_19_0 ALU COUT Out 0.035 8.818 - un2_mult_acc1_cry_19_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_20_0 ALU CIN In - 8.818 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_20_0 ALU COUT Out 0.035 8.853 - un2_mult_acc1_cry_20_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_21_0 ALU CIN In - 8.853 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_21_0 ALU COUT Out 0.035 8.888 - un2_mult_acc1_cry_21_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_22_0 ALU CIN In - 8.888 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_22_0 ALU COUT Out 0.035 8.923 - un2_mult_acc1_cry_22_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_23_0 ALU CIN In - 8.923 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_23_0 ALU COUT Out 0.035 8.958 - un2_mult_acc1_cry_23_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_24_0 ALU CIN In - 8.958 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_24_0 ALU COUT Out 0.035 8.993 - un2_mult_acc1_cry_24_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_25_0 ALU CIN In - 8.993 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_25_0 ALU COUT Out 0.035 9.028 - un2_mult_acc1_cry_25_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_26_0 ALU CIN In - 9.028 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_26_0 ALU COUT Out 0.035 9.063 - un2_mult_acc1_cry_26_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_27_0 ALU CIN In - 9.063 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_27_0 ALU COUT Out 0.035 9.098 - un2_mult_acc1_cry_27_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_28_0 ALU CIN In - 9.098 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_28_0 ALU COUT Out 0.035 9.133 - un2_mult_acc1_cry_28_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_29_0 ALU CIN In - 9.133 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_29_0 ALU COUT Out 0.035 9.168 - un2_mult_acc1_cry_29_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_30_0 ALU CIN In - 9.168 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_30_0 ALU COUT Out 0.035 9.203 - un2_mult_acc1_cry_30_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_31_0 ALU CIN In - 9.203 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_31_0 ALU COUT Out 0.035 9.238 - un2_mult_acc1_cry_31_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_32_0 ALU CIN In - 9.238 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_32_0 ALU COUT Out 0.035 9.273 - un2_mult_acc1_cry_32_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_33_0 ALU CIN In - 9.273 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_cry_33_0 ALU COUT Out 0.035 9.308 - un2_mult_acc1_cry_33_0_COUT Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.un2_mult_acc1_s_34_0 ALU CIN In - 9.308 - test_top.asrc.asrc.fir_filter.un2_mult_acc1_s_34_0 ALU SUM Out 0.470 9.778 - un2_mult_acc1_s_34_0_SUM Net - - 0.535 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc1_5_cZ\[34\] LUT2 I0 In - 10.313 - test_top.asrc.asrc.fir_filter.\\mult_acc1_5_cZ\[34\] LUT2 F Out 0.549 10.862 - mult_acc1_5[34] Net - - 0.000 - 1 test_top.asrc.asrc.fir_filter.\\mult_acc1_Z\[34\] DFFCE D In - 10.862 - ===================================================================================================================================== Total path delay (propagation time + setup) of 10.923 is 6.229(57.0%) logic and 4.694(43.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.ratio_dect.err_sign_d_fast_RNICHR7 System INV O err_sign_d_i 0.000 4.191 test_top.asrc.asrc.shared_divider.div.sum_cry_0_0_RNO System INV O operation_i 0.000 6.204 test_top.asrc.asrc.ratio_dect.un3_err_mag_abs_cry_8_0_RNO_cZ System INV O un3_err_mag_abs_cry_8_0_RNO_cZ 0.000 6.617 test_top.asrc.asrc.input_storage0.\\fifo_level_RNI4PA1\[8\] System INV O fifo_level_i[8] 0.000 6.638 test_top.asrc.asrc.ratio_dect.un3_err_mag_abs_cry_8_0_RNO_0_cZ System INV O un3_err_mag_abs_cry_8_0_RNO_0_cZ 0.000 6.816 test_top.asrc.asrc.ratio_dect.un1_ratio_ave_reg_cry_12_0_RNO_0_cZ System INV O un1_ratio_ave_reg_cry_12_0_RNO_0_cZ 0.000 6.893 test_top.asrc.asrc.ratio_dect.ave_filter.\\data_reg_CF3_RNO_cZ\[0\] System INV O data_reg_CF3_RNO[0] 0.000 8.689 test_top.asrc.asrc.ratio_dect.ave_filter.\\data_reg_CF3_ret_RNO\[1\] System INV O tmp1_i[1] 0.000 8.689 test_top.asrc.asrc.phase_interpolator.\\neg_delta_min_1_RNO\[2\] System INV O Z\\neg_delta_min_1_RNO\[2\] 0.000 8.689 test_top.asrc.asrc.phase_interpolator.\\neg_delta_min_1_RNO\[22\] System INV O Z\\neg_delta_min_1_RNO\[22\] 0.000 8.689 ================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[25\] System DL D ratio_vari_4[25] 6.606 4.191 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[24\] System DL D ratio_vari_4[24] 6.606 4.226 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[23\] System DL D ratio_vari_4[23] 6.606 4.261 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[22\] System DL D ratio_vari_4[22] 6.606 4.296 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[21\] System DL D ratio_vari_4[21] 6.606 4.331 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[20\] System DL D ratio_vari_4[20] 6.606 4.366 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[19\] System DL D ratio_vari_4[19] 6.606 4.401 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[18\] System DL D ratio_vari_4[18] 6.606 4.436 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[17\] System DL D ratio_vari_4[17] 6.606 4.471 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[16\] System DL D ratio_vari_4[16] 6.606 4.506 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.667 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.606 - Propagation time: 2.415 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 4.191 Number of logic level(s): 26 Starting point: test_top.asrc.asrc.ratio_dect.err_sign_d_fast_RNICHR7 / O Ending point: test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[25\] / D The start point is clocked by System [rising] The end point is clocked by gw2a18|SW[1] [falling] on pin G Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------- test_top.asrc.asrc.ratio_dect.err_sign_d_fast_RNICHR7 INV O Out 0.000 0.000 - err_sign_d_i Net - - 0.535 - 3 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_0_0 ALU CIN In - 0.535 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_0_0 ALU COUT Out 0.035 0.570 - ratio_vari_4_cry_0 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_1_0 ALU CIN In - 0.570 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_1_0 ALU COUT Out 0.035 0.605 - ratio_vari_4_cry_1 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_2_0 ALU CIN In - 0.605 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_2_0 ALU COUT Out 0.035 0.640 - ratio_vari_4_cry_2 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_3_0 ALU CIN In - 0.640 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_3_0 ALU COUT Out 0.035 0.675 - ratio_vari_4_cry_3 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_4_0 ALU CIN In - 0.675 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_4_0 ALU COUT Out 0.035 0.710 - ratio_vari_4_cry_4 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_5_0 ALU CIN In - 0.710 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_5_0 ALU COUT Out 0.035 0.745 - ratio_vari_4_cry_5 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_6_0 ALU CIN In - 0.745 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_6_0 ALU COUT Out 0.035 0.780 - ratio_vari_4_cry_6 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_7_0 ALU CIN In - 0.780 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_7_0 ALU COUT Out 0.035 0.815 - ratio_vari_4_cry_7 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_8_0 ALU CIN In - 0.815 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_8_0 ALU COUT Out 0.035 0.850 - ratio_vari_4_cry_8 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_9_0 ALU CIN In - 0.850 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_9_0 ALU COUT Out 0.035 0.885 - ratio_vari_4_cry_9 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_10_0 ALU CIN In - 0.885 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_10_0 ALU COUT Out 0.035 0.920 - ratio_vari_4_cry_10 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_11_0 ALU CIN In - 0.920 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_11_0 ALU COUT Out 0.035 0.955 - ratio_vari_4_cry_11 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_12_0 ALU CIN In - 0.955 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_12_0 ALU COUT Out 0.035 0.990 - ratio_vari_4_cry_12 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_13_0 ALU CIN In - 0.990 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_13_0 ALU COUT Out 0.035 1.025 - ratio_vari_4_cry_13 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_14_0 ALU CIN In - 1.025 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_14_0 ALU COUT Out 0.035 1.060 - ratio_vari_4_cry_14 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_15_0 ALU CIN In - 1.060 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_15_0 ALU COUT Out 0.035 1.095 - ratio_vari_4_cry_15 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_16_0 ALU CIN In - 1.095 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_16_0 ALU COUT Out 0.035 1.130 - ratio_vari_4_cry_16 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_17_0 ALU CIN In - 1.130 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_17_0 ALU COUT Out 0.035 1.165 - ratio_vari_4_cry_17 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_18_0 ALU CIN In - 1.165 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_18_0 ALU COUT Out 0.035 1.200 - ratio_vari_4_cry_18 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_19_0 ALU CIN In - 1.200 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_19_0 ALU COUT Out 0.035 1.235 - ratio_vari_4_cry_19 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_20_0 ALU CIN In - 1.235 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_20_0 ALU COUT Out 0.035 1.270 - ratio_vari_4_cry_20 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_21_0 ALU CIN In - 1.270 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_21_0 ALU COUT Out 0.035 1.305 - ratio_vari_4_cry_21 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_22_0 ALU CIN In - 1.305 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_22_0 ALU COUT Out 0.035 1.340 - ratio_vari_4_cry_22 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_23_0 ALU CIN In - 1.340 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_23_0 ALU COUT Out 0.035 1.375 - ratio_vari_4_cry_23 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_24_0 ALU CIN In - 1.375 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_cry_24_0 ALU COUT Out 0.035 1.410 - ratio_vari_4_cry_24 Net - - 0.000 - 1 test_top.asrc.asrc.ratio_dect.ratio_vari_4_s_25_0 ALU CIN In - 1.410 - test_top.asrc.asrc.ratio_dect.ratio_vari_4_s_25_0 ALU SUM Out 0.470 1.880 - ratio_vari_4[25] Net - - 0.535 - 1 test_top.asrc.asrc.ratio_dect.\\ratio_vari_Z\[25\] DL D In - 2.415 - ==================================================================================================================== Total path delay (propagation time + setup) of 2.476 is 1.406(56.8%) logic and 1.070(43.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:01m:16s; CPU Time elapsed 0h:01m:12s; Memory used current: 239MB peak: 266MB) Finished timing report (Real Time elapsed 0h:01m:16s; CPU Time elapsed 0h:01m:12s; Memory used current: 239MB peak: 266MB) --------------------------------------- Resource Usage Report for gw2a18 Mapping to part: gw2a_18pbga256-8 Cell usage: ALU 1015 uses DFFC 105 uses DFFCE 1701 uses DFFE 8 uses DFFP 31 uses DFFPE 32 uses DL 26 uses GSR 1 use INV 13 uses MUX2_LUT5 25 uses MUX2_LUT6 1 use SDP 1 use SDPB 4 uses pROM 5 uses LUT1 3 uses LUT2 566 uses LUT3 779 uses LUT4 893 uses MULT36X36 3 uses I/O ports: 99 I/O primitives: 47 IBUF 3 uses OBUF 26 uses TBUF 18 uses I/O Register bits: 0 Register bits not including I/Os: 1877 of 15552 (12%) RAM/ROM usage summary Block Rams : 10 of 46 (21%) Block Multipliers: 6 of 24 (25%) Total load per clock: gw2a18|SYM_CLK: 1895 gw2a18|SW[1]: 635 @S |Mapping Summary: Total LUTs: 2241 (10%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:01m:17s; CPU Time elapsed 0h:01m:12s; Memory used current: 82MB peak: 266MB) Process took 0h:01m:17s realtime, 0h:01m:13s cputime # Mon May 18 22:54:47 2020 ###########################################################]