@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: MT529 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":1874:6:1874:36|Found inferred clock gw2a18|SYM_CLK which controls 1901 sequential elements including test_top.asrc.asrc.ratio_dect.ave_filter.data_reg_CR26_data_reg_CR26_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":1874:6:1874:36|Found inferred clock gw2a18|SW[1] which controls 801 sequential elements including test_top.asrc.asrc.ratio_dect.ave_filter.data_reg_CR26_data_reg_CR26_0_0. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
