@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":2578:13:2578:21|Tristate driver clkin_reg_1 (in view: work.\\\~ratio_detection\.ASRC_TOP__Z1\ (verilog)) on net clkin_reg_1 (in view: work.\\\~ratio_detection\.ASRC_TOP__Z1\ (verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":46159:13:46159:21|Tristate driver clkin_reg_1 (in view: work.\\\~asrc\.ASRC_TOP__26s_24s_35s_16\ (verilog)) on net clkin_reg_1 (in view: work.\\\~asrc\.ASRC_TOP__26s_24s_35s_16\ (verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":27:11:27:18|Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":28:11:28:18|Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":31:11:31:16|Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":33:11:33:18|Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":33:11:33:18|Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":31:11:31:16|Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":28:11:28:18|Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":27:11:27:18|Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: BN225 |Writing default property annotation file C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\synthesize\rev_1\ASRC.sap.
