@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: BN114 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":3759:7:3759:31|Removing instance test_top.asrc.asrc.ratio_dect.valid_cnt_clk_0_sqmuxa_cZ (in view: work.gw2a18(verilog)) of black box view:GOWIN.LUT4(PRIM) because it does not drive other instances.
@W: BN114 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":4126:7:4126:16|Removing instance test_top.asrc.asrc.ratio_dect.N_630_i_cZ (in view: work.gw2a18(verilog)) of black box view:GOWIN.LUT4(PRIM) because it does not drive other instances.
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":38:14:38:15|Converting bidirection inout port J4[28:5] to output port. Because it's a pure output port
@W: BN709 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":39:14:39:15|Converting bidirection inout port J3[18:3] to output port. Because it's a pure output port
@W: MT420 |Found inferred clock gw2a18|SYM_CLK with period 9.28ns. Please declare a user-defined clock on port SYM_CLK.
@W: MT420 |Found inferred clock gw2a18|SW[1] with period 6.67ns. Please declare a user-defined clock on port SW[1].
