@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":33:11:33:18|Tristate driver SPI_MISO (in view: work.gw2a18(verilog)) on net SPI_MISO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":31:11:31:16|Tristate driver SPI_CS (in view: work.gw2a18(verilog)) on net SPI_CS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":28:11:28:18|Tristate driver JTAG_TMS (in view: work.gw2a18(verilog)) on net JTAG_TMS (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":27:11:27:18|Tristate driver JTAG_TDO (in view: work.gw2a18(verilog)) on net JTAG_TDO (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[18] (in view: work.gw2a18(verilog)) on net J3[18] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[17] (in view: work.gw2a18(verilog)) on net J3[17] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[16] (in view: work.gw2a18(verilog)) on net J3[16] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[15] (in view: work.gw2a18(verilog)) on net J3[15] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[14] (in view: work.gw2a18(verilog)) on net J3[14] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver J3_t[13] (in view: work.gw2a18(verilog)) on net J3[13] (in view: work.gw2a18(verilog)) has its enable tied to GND.
@N: MT206 |Auto Constrain mode is enabled
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8016:8:8016:22|Removing sequential instance test_top.asrc.asrc.ratio_dect.valid_cnt_clk_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8008:8:8008:24|Removing sequential instance test_top.asrc.asrc.ratio_dect.valid_cnt_clkin_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8848:8:8848:18|Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst3_0 (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8840:8:8840:18|Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst2_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8832:8:8832:18|Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst1_Z (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\asrc\asrc.v":8048:8:8048:15|Removing sequential instance test_top.asrc.asrc.ratio_dect.buff_rst (in view: work.gw2a18(verilog)) of type view:GOWIN.DFFCE(PRIM) because it does not drive other instances.
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
