@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":12192:5:12192:9|Removing wire N_216, as there is no assignment to it.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":18570:6:18570:11|Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":18567:6:18567:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20737:5:20737:8|Removing wire N_27, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20738:5:20738:8|Removing wire N_26, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20739:5:20739:8|Removing wire N_25, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20740:5:20740:8|Removing wire N_24, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20741:5:20741:8|Removing wire N_23, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20742:5:20742:8|Removing wire N_22, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20743:5:20743:8|Removing wire N_21, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20744:5:20744:8|Removing wire N_20, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20745:5:20745:8|Removing wire N_19, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20746:5:20746:8|Removing wire N_18, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20747:5:20747:8|Removing wire N_17, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20748:5:20748:8|Removing wire N_16, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20749:5:20749:8|Removing wire N_15, as there is no assignment to it.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":21888:6:21888:11|Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":22880:5:22880:9|Removing wire N_678, as there is no assignment to it.
@W: CL318 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":46159:13:46159:21|*Output clkin_reg has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":47350:6:47350:11|Removing instance VCC_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":47347:6:47347:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":47467:6:47467:11|Removing instance GND_cZ because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CS263 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\data_prom\data_prom.v":22:8:22:18|Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 16. Adjust either the definition or the instantiation of this port.
@W: CS263 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\data_prom\data_prom.v":95:8:95:19|Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":27:11:27:18|Removing wire JTAG_TDO, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":28:11:28:18|Removing wire JTAG_TMS, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":31:11:31:16|Removing wire SPI_CS, as there is no assignment to it.
@W: CG360 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":33:11:33:18|Removing wire SPI_MISO, as there is no assignment to it.
@W: CL318 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":27:11:27:18|*Output JTAG_TDO has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":28:11:28:18|*Output JTAG_TMS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":31:11:31:16|*Output SPI_CS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":33:11:33:18|*Output SPI_MISO has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL246 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":22:13:22:15|Input port bits 4 to 2 of KEY[4:1] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":23:13:23:14|Input port bits 4 to 2 of SW[4:1] are unused. Assign logic for all port bits or change the input port size.
@W: CL158 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":36:14:36:16|Inout J11 is unused
@W: CL158 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":37:14:37:16|Inout J10 is unused

