@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":2405:7:2405:9|Synthesizing module GSR in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":113:7:113:10|Synthesizing module LUT4 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":107:7:107:10|Synthesizing module LUT3 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":360:7:360:9|Synthesizing module INV in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":222:7:222:11|Synthesizing module DFFCE in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":27:7:27:15|Synthesizing module MUX2_LUT5 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":101:7:101:10|Synthesizing module LUT2 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":288:7:288:8|Synthesizing module DL in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":210:7:210:11|Synthesizing module DFFPE in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":216:7:216:10|Synthesizing module DFFC in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":204:7:204:10|Synthesizing module DFFP in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":143:7:143:9|Synthesizing module ALU in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":33:7:33:15|Synthesizing module MUX2_LUT6 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":174:7:174:10|Synthesizing module DFFE in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":1150:7:1150:9|Synthesizing module SDP in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":2397:7:2397:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":2401:7:2401:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":21:7:21:43|Synthesizing module \~average_filter.ASRC_TOP__26s_16s_1s  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":2503:7:2503:36|Synthesizing module \~ratio_detection.ASRC_TOP__Z1  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":11924:7:11924:42|Synthesizing module \~frac_divider.ASRC_TOP__27s_27s_52s  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":16208:7:16208:49|Synthesizing module \~shared_divider.ASRC_TOP__26s_24s_4194304s  in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":813:7:813:10|Synthesizing module SDPB in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":18575:7:18575:26|Synthesizing module \~MEM_SDPB.ASRC_TOP_  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":18655:7:18655:48|Synthesizing module \~input_storage.ASRC_TOP__16_24s_512s_2s_1  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20499:7:20499:28|Synthesizing module \~MEM_SDPB.ASRC_TOP__0  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":20579:7:20579:48|Synthesizing module \~input_storage.ASRC_TOP__16_24s_512s_2s_0  in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":2194:7:2194:15|Synthesizing module MULT36X36 in library work.
@N: CG364 :"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v":1473:7:1473:10|Synthesizing module pROM in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":21636:7:21636:28|Synthesizing module \~Coeff_pROM.ASRC_TOP_  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":21893:7:21893:80|Synthesizing module \~phase_interpolator.ASRC_TOP__35s_26s_24s_2048s_25s_2042893_2796203_8s_Z2  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":36725:7:36725:46|Synthesizing module \~fir_filter.ASRC_TOP__35s_26s_24s_4s_2s  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":46126:7:46126:37|Synthesizing module \~asrc.ASRC_TOP__26s_24s_35s_16  in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\asrc\asrc.v":47355:7:47355:14|Synthesizing module ASRC_TOP in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\data_prom\data_prom.v":8:7:8:15|Synthesizing module Data_pROM in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\test_top.v":15:7:15:14|Synthesizing module test_top in library work.
@N: CG364 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":16:7:16:12|Synthesizing module gw2a18 in library work.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":18:8:18:14|Input EXT_CLK is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":19:9:19:13|Input RST_N is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":21:13:21:15|Input LED is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":26:11:26:18|Input JTAG_TDI is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":29:11:29:18|Input JTAG_TCK is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":32:11:32:17|Input SPI_CLK is unused.
@N: CL159 :"C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.v":34:11:34:18|Input SPI_MOSI is unused.
@N|Running in 64-bit mode
@N: NF107 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":16:7:16:12|Selected library: work cell: gw2a18 view verilog as top level
@N: NF107 :"c:\users\noa\desktop\myworkplace\program\fpga\asrc\refdesign\asrc\src\gw2a18.v":16:7:16:12|Selected library: work cell: gw2a18 view verilog as top level

