Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\impl\gwsynthesis\ASRC.vg
Physical Constraints File	C:\Users\Noa\Desktop\MyWorkplace\Program\FPGA\ASRC\RefDesign\ASRC\src\gw2a18.cst
Timing Constraint File	---
GOWIN version	V1.9.5.02Beta
Part Number	GW2A-LV18PG256C8/I7
Created Time	Wed May 20 19:11:46 2020
Legal Announcement	Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C
Hold Delay Model	Fast 1.05V 0C
Numbers of Paths Analyzed	7453
Numbers of Endpoints Analyzed	6324
Numbers of Falling Endpoints	26
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
DEFAULT_CLK	Base	10.000	100.000	0.000	5.000

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	DEFAULT_CLK	100.000(MHz)	120.099(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
DEFAULT_CLK	Setup	0.000	0
DEFAULT_CLK	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.172	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_2_ins12297/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.789
2	1.172	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_6_ins12293/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.789
3	1.172	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_0_ins12299/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.789
4	1.289	test_top/asrc/asrc/ratio_dect/n1733_ins24049/I0	test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.671
5	1.329	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/WRE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.632
6	1.393	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_4_ins12295/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.568
7	1.393	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_5_ins12294/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.568
8	1.393	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_1_ins12298/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.568
9	1.453	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.456
10	1.532	test_top/n222_ins5740/I3	test_top/mem_addr_8_ins5489/D	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.429
11	1.539	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_7_ins12292/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.421
12	1.543	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_3_ins12296/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.418
13	1.576	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage0/read_addr_8_ins12291/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.384
14	1.581	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2	test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.380
15	1.581	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.380
16	1.581	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.380
17	1.581	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.380
18	1.610	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage1/read_addr_3_ins12354/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.351
19	1.610	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage1/read_addr_4_ins12353/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.351
20	1.610	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2	test_top/asrc/asrc/input_storage1/read_addr_2_ins12355/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.351
21	1.657	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.304
22	1.674	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/Q	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/A_17	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	7.870
23	1.686	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins24239/I2	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.275
24	1.728	test_top/asrc/asrc/phase_interpolator/n797_ins21892/I0	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.233
25	1.728	test_top/asrc/asrc/phase_interpolator/n797_ins21892/I0	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854/CE	DEFAULT_CLK:[F]	DEFAULT_CLK:[R]	5.000	-1.196	4.233

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.228	test_top/asrc/asrc/ratio_dect/ave_filter/preload_ins11481/Q	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/DI0	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.477
2	0.306	test_top/Data_pROM/prom_inst_0/DO13	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI5	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.555
3	0.307	test_top/Data_pROM/prom_inst_0/DO11	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI3	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.556
4	0.307	test_top/asrc/asrc/fir_filter/take_out2_ins13431/Q	test_top/asrc/asrc/fir_filter/take_out3_ins13432/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
5	0.307	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_r_ins12488/Q	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
6	0.307	test_top/asrc/asrc/input_storage0/valid_reg_0_ins12310/Q	test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
7	0.307	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/Q	test_top/asrc/asrc/fir_filter/fir_init_ins13220/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
8	0.307	test_top/asrc/asrc/ratio_dect/buff_rst1_ins11473/Q	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
9	0.307	test_top/asrc/asrc/ratio_dect/clkout_rising_d_1_ins11411/Q	test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.318
10	0.310	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/Q	test_top/asrc/asrc/phase_interpolator/take_h3_ins12487/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.321
11	0.310	test_top/asrc/asrc/phase_interpolator/take_h1_ins12485/Q	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.321
12	0.310	test_top/asrc/asrc/phase_interpolator/incr_addr_r_0_ins12458/Q	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.321
13	0.310	test_top/asrc/asrc/phase_interpolator/first_sample_calc_ins12414/Q	test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.321
14	0.312	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/Q	test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.323
15	0.314	test_top/asrc/asrc/fir_filter/move_ptr_flag_ins13218/Q	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.325
16	0.314	test_top/asrc/asrc/ratio_dect/clkin_reg_4_ins11126/Q	test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.325
17	0.314	test_top/asrc/asrc/ratio_dect/clkout_reg_1_ins11199/Q	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.325
18	0.317	test_top/asrc/asrc/fir_filter/take_acc2_ins13262/Q	test_top/asrc/asrc/fir_filter/take_acc3_ins13263/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.328
19	0.318	test_top/asrc/asrc/ratio_dect/period_clkout_22_ins11203/Q	test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.329
20	0.327	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/Q	test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197/D	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.338
21	0.332	test_top/Data_pROM/prom_inst_1/DO3	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI11	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.581
22	0.332	test_top/Data_pROM/prom_inst_1/DO2	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI10	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.581
23	0.334	test_top/Data_pROM/prom_inst_0/DO15	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI7	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.583
24	0.348	test_top/Data_pROM/prom_inst_1/DO6	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI14	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.597
25	0.353	test_top/asrc/asrc/ratio_dect/ave_filter/in_data_r_3_ins11504/Q	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/DI23	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	0.602

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
2	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_7_ins13177/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
3	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_10_ins13174/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
4	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_5_ins13179/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
5	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_16_ins13168/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
6	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_18_ins13166/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
7	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_8_ins13176/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
8	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
9	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
10	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
11	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
12	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_21_ins13163/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
13	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
14	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
15	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
16	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
17	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_20_ins13164/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
18	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
19	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
20	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/h2_17_ins12544/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
21	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/h2_19_ins12542/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
22	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
23	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_9_ins13175/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
24	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data3_6_ins13178/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939
25	6.826	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data2_21_ins13139/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	10.000	0.000	2.939

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.649	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/n582_ins15596/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
2	1.649	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/n2246_ins15595/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
3	1.649	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/RESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
4	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531/PRESET	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
5	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/data0_23_ins13530/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
6	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_valid_ins13529/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
7	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_0_ins13456/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
8	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_1_ins13455/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
9	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_2_ins13454/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
10	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_4_ins13452/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
11	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_5_ins13451/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
12	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_3_ins13453/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
13	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_6_ins13450/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
14	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_7_ins13449/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
15	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_8_ins13448/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
16	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_9_ins13447/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
17	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_10_ins13446/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
18	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_11_ins13445/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
19	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_12_ins13444/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
20	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_13_ins13443/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
21	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_14_ins13442/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
22	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_16_ins13440/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
23	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_17_ins13439/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
24	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_18_ins13438/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880
25	1.869	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q	test_top/asrc/asrc/fir_filter/out_data0_19_ins13437/CLEAR	DEFAULT_CLK:[R]	DEFAULT_CLK:[R]	0.000	0.000	1.880

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/mem_addr_8_ins5489
2	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/mem_addr_6_ins5491
3	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/mem_addr_2_ins5495
4	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/cnt_cycle_clkin_6_ins5503
5	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/cnt_cycle_clkout_3_ins5520
6	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/asrc/out_ratio_d_22_ins11447
7	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/asrc/asrc/ratio_dect/period_clkin_sync_14_ins11166
8	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/asrc/asrc/ratio_dect/ratio_ave_reg_13_ins11308
9	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/asrc/asrc/shared_divider/divisor_22_ins12007
10	3.662	4.662	1.000	Low Pulse Width	DEFAULT_CLK	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.172
Data Arrival Time	10.476
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_2_ins12297
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.476	2.183	tNET	RR	1	R35C42[0][B]	test_top/asrc/asrc/input_storage0/read_addr_2_ins12297/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C42[0][B]	test_top/asrc/asrc/input_storage0/read_addr_2_ins12297/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_2_ins12297
11.648	-0.035	tSu		1	R35C42[0][B]	test_top/asrc/asrc/input_storage0/read_addr_2_ins12297

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 11.464%; route: 2.183, 45.586%; tC2Q: 2.057, 42.950%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	1.172
Data Arrival Time	10.476
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_6_ins12293
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.476	2.183	tNET	RR	1	R35C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_6_ins12293/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_6_ins12293/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_6_ins12293
11.648	-0.035	tSu		1	R35C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_6_ins12293

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 11.464%; route: 2.183, 45.586%; tC2Q: 2.057, 42.950%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	1.172
Data Arrival Time	10.476
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_0_ins12299
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.476	2.183	tNET	RR	1	R35C42[0][A]	test_top/asrc/asrc/input_storage0/read_addr_0_ins12299/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C42[0][A]	test_top/asrc/asrc/input_storage0/read_addr_0_ins12299/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_0_ins12299
11.648	-0.035	tSu		1	R35C42[0][A]	test_top/asrc/asrc/input_storage0/read_addr_0_ins12299

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 11.464%; route: 2.183, 45.586%; tC2Q: 2.057, 42.950%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	1.289
Data Arrival Time	10.359
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/n1733_ins24049
To	test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R17C21[3][B]	test_top/asrc/asrc/ratio_dect/n1733_ins24049/I0
8.197	0.453	tINS	FF	34	R17C21[3][B]	test_top/asrc/asrc/ratio_dect/n1733_ins24049/F
9.566	1.369	tNET	FF	1	R24C21[3][B]	test_top/asrc/asrc/ratio_dect/valid_ratio_ins21874/I2
9.893	0.327	tINS	FR	1	R24C21[3][B]	test_top/asrc/asrc/ratio_dect/valid_ratio_ins21874/F
10.359	0.466	tNET	RR	1	R24C19[1][B]	test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R24C19[1][B]	test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470
11.648	-0.035	tSu		1	R24C19[1][B]	test_top/asrc/asrc/ratio_dect/valid_ratio_ins11470

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.780, 16.698%; route: 1.834, 39.272%; tC2Q: 2.057, 44.031%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	1.329
Data Arrival Time	10.319
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2
8.261	0.517	tINS	FF	38	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/F
10.319	2.058	tNET	FF	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/WRE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
11.648	-0.035	tSu		1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.517, 11.162%; route: 2.058, 44.432%; tC2Q: 2.057, 44.406%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	1.393
Data Arrival Time	10.256
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_4_ins12295
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.256	1.962	tNET	RR	1	R38C39[0][A]	test_top/asrc/asrc/input_storage0/read_addr_4_ins12295/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R38C39[0][A]	test_top/asrc/asrc/input_storage0/read_addr_4_ins12295/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_4_ins12295
11.648	-0.035	tSu		1	R38C39[0][A]	test_top/asrc/asrc/input_storage0/read_addr_4_ins12295

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.018%; route: 1.962, 42.956%; tC2Q: 2.057, 45.026%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	1.393
Data Arrival Time	10.256
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_5_ins12294
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.256	1.962	tNET	RR	1	R38C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_5_ins12294/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R38C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_5_ins12294/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_5_ins12294
11.648	-0.035	tSu		1	R38C41[0][B]	test_top/asrc/asrc/input_storage0/read_addr_5_ins12294

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.018%; route: 1.962, 42.956%; tC2Q: 2.057, 45.026%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	1.393
Data Arrival Time	10.256
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_1_ins12298
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.256	1.962	tNET	RR	1	R38C41[0][A]	test_top/asrc/asrc/input_storage0/read_addr_1_ins12298/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R38C41[0][A]	test_top/asrc/asrc/input_storage0/read_addr_1_ins12298/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_1_ins12298
11.648	-0.035	tSu		1	R38C41[0][A]	test_top/asrc/asrc/input_storage0/read_addr_1_ins12298

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.018%; route: 1.962, 42.956%; tC2Q: 2.057, 45.026%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	1.453
Data Arrival Time	10.143
Data Required Time	11.596
From	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2
8.293	0.549	tINS	FR	38	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/F
10.143	1.850	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
11.596	-0.087	tSu		1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.321%; route: 1.850, 41.521%; tC2Q: 2.057, 46.158%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	1.532
Data Arrival Time	10.117
Data Required Time	11.648
From	test_top/n222_ins5740
To	test_top/mem_addr_8_ins5489
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.753	2.066	tNET	FF	1	R39C33[2][B]	test_top/n222_ins5740/I3
8.124	0.371	tINS	FF	5	R39C33[2][B]	test_top/n222_ins5740/F
8.386	0.262	tNET	FF	1	R39C35[2][B]	test_top/n217_ins5738/I2
8.903	0.517	tINS	FF	3	R39C35[2][B]	test_top/n217_ins5738/F
9.568	0.665	tNET	FF	1	R40C32[0][B]	test_top/n217_ins5698/I2
10.117	0.549	tINS	FR	1	R40C32[0][B]	test_top/n217_ins5698/F
10.117	0.000	tNET	RR	1	R40C32[0][B]	test_top/mem_addr_8_ins5489/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R40C32[0][B]	test_top/mem_addr_8_ins5489/CLK
11.683	-0.200	tUnc				test_top/mem_addr_8_ins5489
11.648	-0.035	tSu		1	R40C32[0][B]	test_top/mem_addr_8_ins5489

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.437, 32.444%; route: 0.926, 20.914%; tC2Q: 2.066, 46.642%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	1.539
Data Arrival Time	10.109
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_7_ins12292
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.109	1.816	tNET	RR	1	R35C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_7_ins12292/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_7_ins12292/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_7_ins12292
11.648	-0.035	tSu		1	R35C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_7_ins12292

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.417%; route: 1.816, 41.065%; tC2Q: 2.057, 46.518%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	1.543
Data Arrival Time	10.105
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_3_ins12296
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.105	1.812	tNET	RR	1	R36C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_3_ins12296/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R36C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_3_ins12296/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_3_ins12296
11.648	-0.035	tSu		1	R36C38[0][A]	test_top/asrc/asrc/input_storage0/read_addr_3_ins12296

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.427%; route: 1.812, 41.016%; tC2Q: 2.057, 46.557%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	1.576
Data Arrival Time	10.072
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage0/read_addr_8_ins12291
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.072	1.779	tNET	RR	1	R38C40[0][A]	test_top/asrc/asrc/input_storage0/read_addr_8_ins12291/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R38C40[0][A]	test_top/asrc/asrc/input_storage0/read_addr_8_ins12291/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage0/read_addr_8_ins12291
11.648	-0.035	tSu		1	R38C40[0][A]	test_top/asrc/asrc/input_storage0/read_addr_8_ins12291

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.522%; route: 1.779, 40.566%; tC2Q: 2.057, 46.912%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	1.581
Data Arrival Time	10.067
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862
To	test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2
8.293	0.549	tINS	FR	70	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/F
10.067	1.774	tNET	RR	1	R26C30[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R26C30[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949
11.648	-0.035	tSu		1	R26C30[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out2_buf_34_ins12949

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.534%; route: 1.774, 40.507%; tC2Q: 2.057, 46.959%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	1.581
Data Arrival Time	10.067
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862
To	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2
8.293	0.549	tINS	FR	70	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/F
10.067	1.774	tNET	RR	1	R26C30[0][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R26C30[0][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913
11.648	-0.035	tSu		1	R26C30[0][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_0_ins12913

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.534%; route: 1.774, 40.507%; tC2Q: 2.057, 46.959%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	1.581
Data Arrival Time	10.067
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862
To	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2
8.293	0.549	tINS	FR	70	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/F
10.067	1.774	tNET	RR	1	R26C30[1][A]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R26C30[1][A]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912
11.648	-0.035	tSu		1	R26C30[1][A]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_1_ins12912

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.534%; route: 1.774, 40.507%; tC2Q: 2.057, 46.959%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	1.581
Data Arrival Time	10.067
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862
To	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/I2
8.293	0.549	tINS	FR	70	R29C34[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_34_ins21862/F
10.067	1.774	tNET	RR	1	R26C30[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R26C30[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911
11.648	-0.035	tSu		1	R26C30[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out2_buf_2_ins12911

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.534%; route: 1.774, 40.507%; tC2Q: 2.057, 46.959%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	1.610
Data Arrival Time	10.038
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage1/read_addr_3_ins12354
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.038	1.745	tNET	RR	1	R35C33[2][B]	test_top/asrc/asrc/input_storage1/read_addr_3_ins12354/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C33[2][B]	test_top/asrc/asrc/input_storage1/read_addr_3_ins12354/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage1/read_addr_3_ins12354
11.648	-0.035	tSu		1	R35C33[2][B]	test_top/asrc/asrc/input_storage1/read_addr_3_ins12354

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.618%; route: 1.745, 40.108%; tC2Q: 2.057, 47.273%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	1.610
Data Arrival Time	10.038
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage1/read_addr_4_ins12353
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.038	1.745	tNET	RR	1	R35C33[2][A]	test_top/asrc/asrc/input_storage1/read_addr_4_ins12353/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C33[2][A]	test_top/asrc/asrc/input_storage1/read_addr_4_ins12353/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage1/read_addr_4_ins12353
11.648	-0.035	tSu		1	R35C33[2][A]	test_top/asrc/asrc/input_storage1/read_addr_4_ins12353

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.618%; route: 1.745, 40.108%; tC2Q: 2.057, 47.273%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	1.610
Data Arrival Time	10.038
Data Required Time	11.648
From	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867
To	test_top/asrc/asrc/input_storage1/read_addr_2_ins12355
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/I2
8.293	0.549	tINS	FR	53	R25C35[1][B]	test_top/asrc/asrc/input_storage0/read_addr_8_ins21867/F
10.038	1.745	tNET	RR	1	R35C33[0][A]	test_top/asrc/asrc/input_storage1/read_addr_2_ins12355/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C33[0][A]	test_top/asrc/asrc/input_storage1/read_addr_2_ins12355/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/input_storage1/read_addr_2_ins12355
11.648	-0.035	tSu		1	R35C33[0][A]	test_top/asrc/asrc/input_storage1/read_addr_2_ins12355

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.549, 12.618%; route: 1.745, 40.108%; tC2Q: 2.057, 47.273%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	1.657
Data Arrival Time	9.991
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/I2
8.261	0.517	tINS	FF	38	R25C23[1][B]	test_top/asrc/asrc/ratio_dect/ave_filter/ave_sum_30_ins21899/F
8.977	0.715	tNET	FF	1	R18C23[0][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins21915/I2
9.526	0.549	tINS	FR	1	R18C23[0][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins21915/F
9.991	0.466	tNET	RR	1	R20C23[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R20C23[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711
11.648	-0.035	tSu		1	R20C23[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15711

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 1.066, 24.768%; route: 1.181, 27.443%; tC2Q: 2.057, 47.789%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	1.674
Data Arrival Time	9.754
Data Required Time	11.427
From	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457
To	test_top/asrc/asrc/phase_interpolator/n2033_ins15594
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R25C36[2][B]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/CLK
2.115	0.232	tC2Q	RF	123	R25C36[2][B]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/Q
3.361	1.246	tNET	FF	1	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/mult_sel_1_ins22389/I2
3.916	0.555	tINS	FF	90	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/mult_sel_1_ins22389/F
5.746	1.830	tNET	FF	1	R25C31[3][A]	test_top/asrc/asrc/phase_interpolator/mult1_b_8_ins23355/I1
6.117	0.371	tINS	FF	51	R25C31[3][A]	test_top/asrc/asrc/phase_interpolator/mult1_b_8_ins23355/F
8.025	1.908	tNET	FF	1	R26C34[3][B]	test_top/asrc/asrc/phase_interpolator/mult1_a_17_ins22586/I0
8.580	0.555	tINS	FF	1	R26C34[3][B]	test_top/asrc/asrc/phase_interpolator/mult1_a_17_ins22586/F
9.754	1.174	tNET	FF	1	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/A_17

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/n2033_ins15594
11.427	-0.256	tSu		1	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 1.481, 18.817%; route: 6.157, 78.235%; tC2Q: 0.232, 2.948%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	1.686
Data Arrival Time	9.962
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins24239
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.744	2.057	tNET	FF	1	R18C23[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins24239/I2
8.115	0.371	tINS	FF	6	R18C23[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins24239/F
8.552	0.436	tNET	FF	1	R17C21[3][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins23997/I0
9.101	0.549	tINS	FR	1	R17C21[3][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins23997/F
9.962	0.861	tNET	RR	1	R17C21[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R17C21[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707
11.648	-0.035	tSu		1	R17C21[2][A]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15707

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.920, 21.522%; route: 1.298, 30.363%; tC2Q: 2.057, 48.115%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	1.728
Data Arrival Time	9.920
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/n797_ins21892
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.753	2.066	tNET	FF	1	R24C31[3][A]	test_top/asrc/asrc/phase_interpolator/n797_ins21892/I0
8.080	0.327	tINS	FR	94	R24C31[3][A]	test_top/asrc/asrc/phase_interpolator/n797_ins21892/F
9.920	1.840	tNET	RR	1	R33C36[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C36[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928
11.648	-0.035	tSu		1	R33C36[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_20_ins12928

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.327, 7.725%; route: 1.840, 43.471%; tC2Q: 2.066, 48.803%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	1.728
Data Arrival Time	9.920
Data Required Time	11.648
From	test_top/asrc/asrc/phase_interpolator/n797_ins21892
To	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854
Launch Clk	DEFAULT_CLK:[F]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					DEFAULT_CLK
5.000	0.000	tCL	FF	1	IOL38[B]	SW_d_1_ibuf5429/I
5.688	0.688	tINS	FF	743	IOL38[B]	SW_d_1_ibuf5429/O
7.753	2.066	tNET	FF	1	R24C31[3][A]	test_top/asrc/asrc/phase_interpolator/n797_ins21892/I0
8.080	0.327	tINS	FR	94	R24C31[3][A]	test_top/asrc/asrc/phase_interpolator/n797_ins21892/F
9.920	1.840	tNET	RR	1	R33C36[0][A]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C36[0][A]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854
11.648	-0.035	tSu		1	R33C36[0][A]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_24_ins12854

Path Statistics:

Clock Skew	1.196
Setup Relationship	5.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.688, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.327, 7.725%; route: 1.840, 43.471%; tC2Q: 2.066, 48.803%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.228
Data Arrival Time	2.054
Data Required Time	1.826
From	test_top/asrc/asrc/ratio_dect/ave_filter/preload_ins11481
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R18C21[1][A]	test_top/asrc/asrc/ratio_dect/ave_filter/preload_ins11481/CLK
1.779	0.202	tC2Q	RR	36	R18C21[1][A]	test_top/asrc/asrc/ratio_dect/ave_filter/preload_ins11481/Q
2.054	0.275	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/DI0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
1.826	0.249	tHld		1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	0.306
Data Arrival Time	2.132
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_0
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	16	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/DO13
2.132	0.248	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI5

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.248, 44.651%; tC2Q: 0.307, 55.349%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	0.307
Data Arrival Time	2.133
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_0
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	16	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/DO11
2.133	0.249	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI3

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 44.773%; tC2Q: 0.307, 55.227%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/fir_filter/take_out2_ins13431
To	test_top/asrc/asrc/fir_filter/take_out3_ins13432
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R29C22[2][A]	test_top/asrc/asrc/fir_filter/take_out2_ins13431/CLK
1.778	0.201	tC2Q	RF	1	R29C22[2][A]	test_top/asrc/asrc/fir_filter/take_out2_ins13431/Q
1.895	0.117	tNET	FF	1	R29C22[0][B]	test_top/asrc/asrc/fir_filter/take_out3_ins13432/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R29C22[0][B]	test_top/asrc/asrc/fir_filter/take_out3_ins13432/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/take_out3_ins13432
1.588	0.011	tHld		1	R29C22[0][B]	test_top/asrc/asrc/fir_filter/take_out3_ins13432

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_r_ins12488
To	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C37[2][B]	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_r_ins12488/CLK
1.778	0.201	tC2Q	RF	1	R24C37[2][B]	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_r_ins12488/Q
1.895	0.117	tNET	FF	1	R24C37[0][A]	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C37[0][A]	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489
1.588	0.011	tHld		1	R24C37[0][A]	test_top/asrc/asrc/phase_interpolator/coeff_center_posi_ins12489

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/input_storage0/valid_reg_0_ins12310
To	test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C39[1][A]	test_top/asrc/asrc/input_storage0/valid_reg_0_ins12310/CLK
1.778	0.201	tC2Q	RF	1	R40C39[1][A]	test_top/asrc/asrc/input_storage0/valid_reg_0_ins12310/Q
1.895	0.117	tNET	FF	1	R40C39[0][A]	test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C39[0][A]	test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309
1.588	0.011	tHld		1	R40C39[0][A]	test_top/asrc/asrc/input_storage0/valid_reg_1_ins12309

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219
To	test_top/asrc/asrc/fir_filter/fir_init_ins13220
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C28[0][A]	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/CLK
1.778	0.201	tC2Q	RF	1	R24C28[0][A]	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/Q
1.895	0.117	tNET	FF	1	R24C28[1][B]	test_top/asrc/asrc/fir_filter/fir_init_ins13220/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C28[1][B]	test_top/asrc/asrc/fir_filter/fir_init_ins13220/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/fir_init_ins13220
1.588	0.011	tHld		1	R24C28[1][B]	test_top/asrc/asrc/fir_filter/fir_init_ins13220

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst1_ins11473
To	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[2][B]	test_top/asrc/asrc/ratio_dect/buff_rst1_ins11473/CLK
1.778	0.201	tC2Q	RF	1	R27C15[2][B]	test_top/asrc/asrc/ratio_dect/buff_rst1_ins11473/Q
1.895	0.117	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[2][A]	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474
1.588	0.011	tHld		1	R27C15[2][A]	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	0.307
Data Arrival Time	1.895
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/clkout_rising_d_1_ins11411
To	test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R25C18[0][B]	test_top/asrc/asrc/ratio_dect/clkout_rising_d_1_ins11411/CLK
1.778	0.201	tC2Q	RF	1	R25C18[0][B]	test_top/asrc/asrc/ratio_dect/clkout_rising_d_1_ins11411/Q
1.895	0.117	tNET	FF	1	R25C18[0][A]	test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R25C18[0][A]	test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410
1.588	0.011	tHld		1	R25C18[0][A]	test_top/asrc/asrc/ratio_dect/clkout_rising_d_2_ins11410

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	0.310
Data Arrival Time	1.899
Data Required Time	1.588
From	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486
To	test_top/asrc/asrc/phase_interpolator/take_h3_ins12487
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/CLK
1.778	0.201	tC2Q	RF	2	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/Q
1.899	0.120	tNET	FF	1	R34C38[1][A]	test_top/asrc/asrc/phase_interpolator/take_h3_ins12487/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R34C38[1][A]	test_top/asrc/asrc/phase_interpolator/take_h3_ins12487/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/take_h3_ins12487
1.588	0.011	tHld		1	R34C38[1][A]	test_top/asrc/asrc/phase_interpolator/take_h3_ins12487

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	0.310
Data Arrival Time	1.899
Data Required Time	1.588
From	test_top/asrc/asrc/phase_interpolator/take_h1_ins12485
To	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R34C38[2][B]	test_top/asrc/asrc/phase_interpolator/take_h1_ins12485/CLK
1.778	0.201	tC2Q	RF	2	R34C38[2][B]	test_top/asrc/asrc/phase_interpolator/take_h1_ins12485/Q
1.899	0.120	tNET	FF	1	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/take_h2_ins12486
1.588	0.011	tHld		1	R34C38[1][B]	test_top/asrc/asrc/phase_interpolator/take_h2_ins12486

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	0.310
Data Arrival Time	1.899
Data Required Time	1.588
From	test_top/asrc/asrc/phase_interpolator/incr_addr_r_0_ins12458
To	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R25C36[2][A]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_0_ins12458/CLK
1.778	0.201	tC2Q	RF	2	R25C36[2][A]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_0_ins12458/Q
1.899	0.120	tNET	FF	1	R25C36[2][B]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R25C36[2][B]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457
1.588	0.011	tHld		1	R25C36[2][B]	test_top/asrc/asrc/phase_interpolator/incr_addr_r_1_ins12457

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	0.310
Data Arrival Time	1.899
Data Required Time	1.588
From	test_top/asrc/asrc/phase_interpolator/first_sample_calc_ins12414
To	test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C29[0][B]	test_top/asrc/asrc/phase_interpolator/first_sample_calc_ins12414/CLK
1.778	0.201	tC2Q	RF	4	R27C29[0][B]	test_top/asrc/asrc/phase_interpolator/first_sample_calc_ins12414/Q
1.899	0.120	tNET	FF	1	R27C29[0][A]	test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C29[0][A]	test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416
1.588	0.011	tHld		1	R27C29[0][A]	test_top/asrc/asrc/phase_interpolator/first_sample_calc_d_0_ins12416

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	0.312
Data Arrival Time	1.900
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474
To	test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[2][A]	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/CLK
1.778	0.201	tC2Q	RF	1	R27C15[2][A]	test_top/asrc/asrc/ratio_dect/buff_rst2_ins11474/Q
1.900	0.122	tNET	FF	1	R27C14[0][A]	test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C14[0][A]	test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475
1.588	0.011	tHld		1	R27C14[0][A]	test_top/asrc/asrc/ratio_dect/buff_rst3_ins11475

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	0.314
Data Arrival Time	1.902
Data Required Time	1.588
From	test_top/asrc/asrc/fir_filter/move_ptr_flag_ins13218
To	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C28[0][B]	test_top/asrc/asrc/fir_filter/move_ptr_flag_ins13218/CLK
1.778	0.201	tC2Q	RF	2	R24C28[0][B]	test_top/asrc/asrc/fir_filter/move_ptr_flag_ins13218/Q
1.902	0.124	tNET	FF	1	R24C28[0][A]	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R24C28[0][A]	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/fir_init_r_ins13219
1.588	0.011	tHld		1	R24C28[0][A]	test_top/asrc/asrc/fir_filter/fir_init_r_ins13219

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	0.314
Data Arrival Time	1.902
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/clkin_reg_4_ins11126
To	test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R23C26[0][B]	test_top/asrc/asrc/ratio_dect/clkin_reg_4_ins11126/CLK
1.778	0.201	tC2Q	RF	2	R23C26[0][B]	test_top/asrc/asrc/ratio_dect/clkin_reg_4_ins11126/Q
1.902	0.124	tNET	FF	1	R23C26[0][A]	test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R23C26[0][A]	test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477
1.588	0.011	tHld		1	R23C26[0][A]	test_top/asrc/asrc/ratio_dect/clkin_reg_5_ins11477

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	0.314
Data Arrival Time	1.902
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/clkout_reg_1_ins11199
To	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R16C21[1][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_1_ins11199/CLK
1.778	0.201	tC2Q	RF	2	R16C21[1][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_1_ins11199/Q
1.902	0.124	tNET	FF	1	R16C21[0][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R16C21[0][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198
1.588	0.011	tHld		1	R16C21[0][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	0.317
Data Arrival Time	1.905
Data Required Time	1.588
From	test_top/asrc/asrc/fir_filter/take_acc2_ins13262
To	test_top/asrc/asrc/fir_filter/take_acc3_ins13263
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C21[0][B]	test_top/asrc/asrc/fir_filter/take_acc2_ins13262/CLK
1.778	0.201	tC2Q	RF	3	R39C21[0][B]	test_top/asrc/asrc/fir_filter/take_acc2_ins13262/Q
1.905	0.127	tNET	FF	1	R39C21[0][A]	test_top/asrc/asrc/fir_filter/take_acc3_ins13263/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C21[0][A]	test_top/asrc/asrc/fir_filter/take_acc3_ins13263/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/take_acc3_ins13263
1.588	0.011	tHld		1	R39C21[0][A]	test_top/asrc/asrc/fir_filter/take_acc3_ins13263

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.127, 38.710%; tC2Q: 0.201, 61.290%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	0.318
Data Arrival Time	1.907
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/period_clkout_22_ins11203
To	test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R16C25[2][B]	test_top/asrc/asrc/ratio_dect/period_clkout_22_ins11203/CLK
1.778	0.201	tC2Q	RF	3	R16C25[2][B]	test_top/asrc/asrc/ratio_dect/period_clkout_22_ins11203/Q
1.907	0.128	tNET	FF	1	R17C25[0][A]	test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R17C25[0][A]	test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228
1.588	0.011	tHld		1	R17C25[0][A]	test_top/asrc/asrc/ratio_dect/period_clkout_sync_22_ins11228

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 38.990%; tC2Q: 0.201, 61.010%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	0.327
Data Arrival Time	1.915
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198
To	test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R16C21[0][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/CLK
1.778	0.201	tC2Q	RF	7	R16C21[0][A]	test_top/asrc/asrc/ratio_dect/clkout_reg_2_ins11198/Q
1.915	0.137	tNET	FF	1	R16C21[0][B]	test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R16C21[0][B]	test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197
1.588	0.011	tHld		1	R16C21[0][B]	test_top/asrc/asrc/ratio_dect/clkout_reg_3_ins11197

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 40.494%; tC2Q: 0.201, 59.506%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	0.332
Data Arrival Time	2.158
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_1
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	8	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/DO3
2.158	0.274	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI11

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 47.133%; tC2Q: 0.307, 52.867%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	0.332
Data Arrival Time	2.158
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_1
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	8	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/DO2
2.158	0.274	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI10

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 47.133%; tC2Q: 0.307, 52.867%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	0.334
Data Arrival Time	2.161
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_0
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	16	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[10]	test_top/Data_pROM/prom_inst_0/DO15
2.161	0.276	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI7

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.276, 47.354%; tC2Q: 0.307, 52.646%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	0.348
Data Arrival Time	2.175
Data Required Time	1.826
From	test_top/Data_pROM/prom_inst_1
To	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	8	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/CLK
1.884	0.307	tC2Q	RR	6	BSRAM_R46[9]	test_top/Data_pROM/prom_inst_1/DO6
2.175	0.290	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/DI14

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1/CLKA
1.577	0.000	tUnc				test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1
1.826	0.249	tHld		1	BSRAM_R46[12]	test_top/asrc/asrc/input_storage0/fifo/sdpb_inst_1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.290, 48.584%; tC2Q: 0.307, 51.416%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	0.353
Data Arrival Time	2.179
Data Required Time	1.826
From	test_top/asrc/asrc/ratio_dect/ave_filter/in_data_r_3_ins11504
To	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R20C24[1][A]	test_top/asrc/asrc/ratio_dect/ave_filter/in_data_r_3_ins11504/CLK
1.779	0.202	tC2Q	RR	2	R20C24[1][A]	test_top/asrc/asrc/ratio_dect/ave_filter/in_data_r_3_ins11504/Q
2.179	0.400	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/DI23

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760
1.826	0.249	tHld		1	BSRAM_R10[6]	test_top/asrc/asrc/ratio_dect/ave_filter/data_reg[0]_26_ins15760

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 66.427%; tC2Q: 0.202, 33.573%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C25[1][B]	test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C25[1][B]	test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211
11.648	-0.035	tSu		1	R34C25[1][B]	test_top/asrc/asrc/fir_filter/first_sample_posi_6_ins13211

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path2

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_7_ins13177
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[1][A]	test_top/asrc/asrc/fir_filter/data3_7_ins13177/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[1][A]	test_top/asrc/asrc/fir_filter/data3_7_ins13177/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_7_ins13177
11.648	-0.035	tSu		1	R35C37[1][A]	test_top/asrc/asrc/fir_filter/data3_7_ins13177

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path3

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_10_ins13174
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[2][B]	test_top/asrc/asrc/fir_filter/data3_10_ins13174/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[2][B]	test_top/asrc/asrc/fir_filter/data3_10_ins13174/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_10_ins13174
11.648	-0.035	tSu		1	R35C37[2][B]	test_top/asrc/asrc/fir_filter/data3_10_ins13174

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path4

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_5_ins13179
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[0][A]	test_top/asrc/asrc/fir_filter/data3_5_ins13179/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[0][A]	test_top/asrc/asrc/fir_filter/data3_5_ins13179/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_5_ins13179
11.648	-0.035	tSu		1	R35C37[0][A]	test_top/asrc/asrc/fir_filter/data3_5_ins13179

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path5

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_16_ins13168
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C29[0][A]	test_top/asrc/asrc/fir_filter/data3_16_ins13168/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C29[0][A]	test_top/asrc/asrc/fir_filter/data3_16_ins13168/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_16_ins13168
11.648	-0.035	tSu		1	R35C29[0][A]	test_top/asrc/asrc/fir_filter/data3_16_ins13168

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path6

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_18_ins13166
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C29[1][A]	test_top/asrc/asrc/fir_filter/data3_18_ins13166/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C29[1][A]	test_top/asrc/asrc/fir_filter/data3_18_ins13166/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_18_ins13166
11.648	-0.035	tSu		1	R35C29[1][A]	test_top/asrc/asrc/fir_filter/data3_18_ins13166

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path7

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_8_ins13176
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[1][B]	test_top/asrc/asrc/fir_filter/data3_8_ins13176/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[1][B]	test_top/asrc/asrc/fir_filter/data3_8_ins13176/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_8_ins13176
11.648	-0.035	tSu		1	R35C37[1][B]	test_top/asrc/asrc/fir_filter/data3_8_ins13176

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path8

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941
11.648	-0.035	tSu		1	R34C37[2][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_7_ins12941

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path9

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939
11.648	-0.035	tSu		1	R34C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_9_ins12939

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path10

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[0][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[0][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929
11.648	-0.035	tSu		1	R34C37[0][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_19_ins12929

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path11

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927
11.648	-0.035	tSu		1	R34C37[0][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_21_ins12927

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path12

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_21_ins13163
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C29[2][B]	test_top/asrc/asrc/fir_filter/data3_21_ins13163/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C29[2][B]	test_top/asrc/asrc/fir_filter/data3_21_ins13163/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_21_ins13163
11.648	-0.035	tSu		1	R35C29[2][B]	test_top/asrc/asrc/fir_filter/data3_21_ins13163

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path13

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944
11.648	-0.035	tSu		1	R34C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_4_ins12944

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path14

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942
11.648	-0.035	tSu		1	R33C37[1][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_6_ins12942

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path15

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C33[0][B]	test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C33[0][B]	test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714
11.648	-0.035	tSu		1	R33C33[0][B]	test_top/asrc/asrc/phase_interpolator/h0_one_third_7_ins12714

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path16

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C33[0][A]	test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C33[0][A]	test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716
11.648	-0.035	tSu		1	R33C33[0][A]	test_top/asrc/asrc/phase_interpolator/h0_one_third_5_ins12716

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path17

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_20_ins13164
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C29[2][A]	test_top/asrc/asrc/fir_filter/data3_20_ins13164/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C29[2][A]	test_top/asrc/asrc/fir_filter/data3_20_ins13164/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_20_ins13164
11.648	-0.035	tSu		1	R35C29[2][A]	test_top/asrc/asrc/fir_filter/data3_20_ins13164

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path18

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850
11.648	-0.035	tSu		1	R33C37[1][B]	test_top/asrc/asrc/phase_interpolator/mult1_out1_buf_28_ins12850

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path19

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R34C37[2][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R34C37[2][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945
11.648	-0.035	tSu		1	R34C37[2][A]	test_top/asrc/asrc/phase_interpolator/mult2_out1_buf_3_ins12945

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path20

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/h2_17_ins12544
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C33[2][A]	test_top/asrc/asrc/phase_interpolator/h2_17_ins12544/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C33[2][A]	test_top/asrc/asrc/phase_interpolator/h2_17_ins12544/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/h2_17_ins12544
11.648	-0.035	tSu		1	R33C33[2][A]	test_top/asrc/asrc/phase_interpolator/h2_17_ins12544

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path21

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/h2_19_ins12542
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C33[2][B]	test_top/asrc/asrc/phase_interpolator/h2_19_ins12542/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C33[2][B]	test_top/asrc/asrc/phase_interpolator/h2_19_ins12542/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/h2_19_ins12542
11.648	-0.035	tSu		1	R33C33[2][B]	test_top/asrc/asrc/phase_interpolator/h2_19_ins12542

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path22

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R33C33[1][A]	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R33C33[1][A]	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/phase_interpolator/h1_8_ins12529
11.648	-0.035	tSu		1	R33C33[1][A]	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path23

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_9_ins13175
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[2][A]	test_top/asrc/asrc/fir_filter/data3_9_ins13175/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[2][A]	test_top/asrc/asrc/fir_filter/data3_9_ins13175/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_9_ins13175
11.648	-0.035	tSu		1	R35C37[2][A]	test_top/asrc/asrc/fir_filter/data3_9_ins13175

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path24

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data3_6_ins13178
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C37[0][B]	test_top/asrc/asrc/fir_filter/data3_6_ins13178/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C37[0][B]	test_top/asrc/asrc/fir_filter/data3_6_ins13178/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data3_6_ins13178
11.648	-0.035	tSu		1	R35C37[0][B]	test_top/asrc/asrc/fir_filter/data3_6_ins13178

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Path25

Path Summary:

Slack	6.826
Data Arrival Time	4.822
Data Required Time	11.648
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data2_21_ins13139
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.683	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.883	1.201	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
2.115	0.232	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
2.276	0.161	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.793	0.517	tINS	FF	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
4.822	2.029	tNET	FF	1	R35C29[1][B]	test_top/asrc/asrc/fir_filter/data2_21_ins13139/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					DEFAULT_CLK
10.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
10.682	0.683	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
11.883	1.201	tNET	RR	1	R35C29[1][B]	test_top/asrc/asrc/fir_filter/data2_21_ins13139/CLK
11.683	-0.200	tUnc				test_top/asrc/asrc/fir_filter/data2_21_ins13139
11.648	-0.035	tSu		1	R35C29[1][B]	test_top/asrc/asrc/fir_filter/data2_21_ins13139

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%
Arrival Data Path Delay	cell: 0.517, 17.591%; route: 2.190, 74.516%; tC2Q: 0.232, 7.894%
Required Clock Path Delay	cell: 0.683, 36.242%; route: 1.201, 63.758%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.649
Data Arrival Time	3.457
Data Required Time	1.808
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/n582_ins15596
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	72	DSP_R37[1]	test_top/asrc/asrc/fir_filter/n582_ins15596/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	DSP_R37[1]	test_top/asrc/asrc/fir_filter/n582_ins15596/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/n582_ins15596
1.808	0.231	tHld		1	DSP_R37[1]	test_top/asrc/asrc/fir_filter/n582_ins15596

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path2

Path Summary:

Slack	1.649
Data Arrival Time	3.457
Data Required Time	1.808
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/n2246_ins15595
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	72	DSP_R37[4]	test_top/asrc/asrc/phase_interpolator/n2246_ins15595/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	DSP_R37[4]	test_top/asrc/asrc/phase_interpolator/n2246_ins15595/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/n2246_ins15595
1.808	0.231	tHld		1	DSP_R37[4]	test_top/asrc/asrc/phase_interpolator/n2246_ins15595

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path3

Path Summary:

Slack	1.649
Data Arrival Time	3.457
Data Required Time	1.808
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/phase_interpolator/n2033_ins15594
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	72	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/phase_interpolator/n2033_ins15594
1.808	0.231	tHld		1	DSP_R37[3]	test_top/asrc/asrc/phase_interpolator/n2033_ins15594

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path4

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C22[0][A]	test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C22[0][A]	test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531
1.588	0.011	tHld		1	R40C22[0][A]	test_top/asrc/asrc/fir_filter/mult_b_sel_2_ins13531

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path5

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/data0_23_ins13530
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R38C37[0][A]	test_top/asrc/asrc/fir_filter/data0_23_ins13530/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R38C37[0][A]	test_top/asrc/asrc/fir_filter/data0_23_ins13530/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/data0_23_ins13530
1.588	0.011	tHld		1	R38C37[0][A]	test_top/asrc/asrc/fir_filter/data0_23_ins13530

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path6

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_valid_ins13529
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R29C22[1][A]	test_top/asrc/asrc/fir_filter/out_valid_ins13529/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R29C22[1][A]	test_top/asrc/asrc/fir_filter/out_valid_ins13529/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_valid_ins13529
1.588	0.011	tHld		1	R29C22[1][A]	test_top/asrc/asrc/fir_filter/out_valid_ins13529

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path7

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_0_ins13456
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C23[1][A]	test_top/asrc/asrc/fir_filter/out_data0_0_ins13456/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C23[1][A]	test_top/asrc/asrc/fir_filter/out_data0_0_ins13456/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_0_ins13456
1.588	0.011	tHld		1	R39C23[1][A]	test_top/asrc/asrc/fir_filter/out_data0_0_ins13456

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path8

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_1_ins13455
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C23[1][B]	test_top/asrc/asrc/fir_filter/out_data0_1_ins13455/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C23[1][B]	test_top/asrc/asrc/fir_filter/out_data0_1_ins13455/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_1_ins13455
1.588	0.011	tHld		1	R39C23[1][B]	test_top/asrc/asrc/fir_filter/out_data0_1_ins13455

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path9

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_2_ins13454
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C23[2][A]	test_top/asrc/asrc/fir_filter/out_data0_2_ins13454/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C23[2][A]	test_top/asrc/asrc/fir_filter/out_data0_2_ins13454/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_2_ins13454
1.588	0.011	tHld		1	R39C23[2][A]	test_top/asrc/asrc/fir_filter/out_data0_2_ins13454

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path10

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_4_ins13452
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R36C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_4_ins13452/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R36C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_4_ins13452/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_4_ins13452
1.588	0.011	tHld		1	R36C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_4_ins13452

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path11

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_5_ins13451
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_5_ins13451/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_5_ins13451/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_5_ins13451
1.588	0.011	tHld		1	R40C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_5_ins13451

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path12

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_3_ins13453
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C23[2][B]	test_top/asrc/asrc/fir_filter/out_data0_3_ins13453/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C23[2][B]	test_top/asrc/asrc/fir_filter/out_data0_3_ins13453/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_3_ins13453
1.588	0.011	tHld		1	R39C23[2][B]	test_top/asrc/asrc/fir_filter/out_data0_3_ins13453

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path13

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_6_ins13450
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_6_ins13450/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_6_ins13450/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_6_ins13450
1.588	0.011	tHld		1	R40C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_6_ins13450

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path14

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_7_ins13449
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_7_ins13449/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_7_ins13449/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_7_ins13449
1.588	0.011	tHld		1	R40C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_7_ins13449

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path15

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_8_ins13448
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_8_ins13448/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_8_ins13448/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_8_ins13448
1.588	0.011	tHld		1	R40C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_8_ins13448

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path16

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_9_ins13447
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_9_ins13447/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_9_ins13447/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_9_ins13447
1.588	0.011	tHld		1	R40C24[2][A]	test_top/asrc/asrc/fir_filter/out_data0_9_ins13447

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path17

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_10_ins13446
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R40C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_10_ins13446/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R40C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_10_ins13446/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_10_ins13446
1.588	0.011	tHld		1	R40C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_10_ins13446

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path18

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_11_ins13445
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_11_ins13445/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_11_ins13445/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_11_ins13445
1.588	0.011	tHld		1	R39C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_11_ins13445

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path19

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_12_ins13444
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_12_ins13444/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_12_ins13444/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_12_ins13444
1.588	0.011	tHld		1	R39C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_12_ins13444

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path20

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_13_ins13443
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_13_ins13443/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_13_ins13443/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_13_ins13443
1.588	0.011	tHld		1	R39C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_13_ins13443

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path21

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_14_ins13442
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_14_ins13442/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_14_ins13442/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_14_ins13442
1.588	0.011	tHld		1	R39C24[1][B]	test_top/asrc/asrc/fir_filter/out_data0_14_ins13442

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path22

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_16_ins13440
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R39C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_16_ins13440/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R39C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_16_ins13440/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_16_ins13440
1.588	0.011	tHld		1	R39C24[2][B]	test_top/asrc/asrc/fir_filter/out_data0_16_ins13440

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path23

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_17_ins13439
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R38C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_17_ins13439/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R38C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_17_ins13439/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_17_ins13439
1.588	0.011	tHld		1	R38C24[0][A]	test_top/asrc/asrc/fir_filter/out_data0_17_ins13439

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path24

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_18_ins13438
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R38C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_18_ins13438/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R38C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_18_ins13438/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_18_ins13438
1.588	0.011	tHld		1	R38C24[0][B]	test_top/asrc/asrc/fir_filter/out_data0_18_ins13438

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Path25

Path Summary:

Slack	1.869
Data Arrival Time	3.457
Data Required Time	1.588
From	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472
To	test_top/asrc/asrc/fir_filter/out_data0_19_ins13437
Launch Clk	DEFAULT_CLK:[R]
Latch Clk	DEFAULT_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/CLK
1.778	0.201	tC2Q	RF	2	R27C15[1][A]	test_top/asrc/asrc/ratio_dect/buff_rst_ins11472/Q
1.902	0.124	tNET	FF	1	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/I1
2.286	0.384	tINS	FR	1012	R27C15[2][A]	test_top/asrc/asrc/input_storage0/n57_ins22307/F
3.457	1.171	tNET	RR	1	R38C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_19_ins13437/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					DEFAULT_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf5427/I
0.675	0.675	tINS	RR	1996	IOT27[A]	SYM_CLK_ibuf5427/O
1.577	0.902	tNET	RR	1	R38C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_19_ins13437/CLK
1.577	0.000	tUnc				test_top/asrc/asrc/fir_filter/out_data0_19_ins13437
1.588	0.011	tHld		1	R38C24[1][A]	test_top/asrc/asrc/fir_filter/out_data0_19_ins13437

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%
Arrival Data Path Delay	cell: 0.384, 20.428%; route: 1.295, 68.879%; tC2Q: 0.201, 10.693%
Required Clock Path Delay	cell: 0.675, 42.823%; route: 0.902, 57.177%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/mem_addr_8_ins5489

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/mem_addr_8_ins5489/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/mem_addr_8_ins5489/CLK

MPW2

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/mem_addr_6_ins5491

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/mem_addr_6_ins5491/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/mem_addr_6_ins5491/CLK

MPW3

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/mem_addr_2_ins5495

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/mem_addr_2_ins5495/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/mem_addr_2_ins5495/CLK

MPW4

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/cnt_cycle_clkin_6_ins5503

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/cnt_cycle_clkin_6_ins5503/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/cnt_cycle_clkin_6_ins5503/CLK

MPW5

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/cnt_cycle_clkout_3_ins5520

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/cnt_cycle_clkout_3_ins5520/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/cnt_cycle_clkout_3_ins5520/CLK

MPW6

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/asrc/out_ratio_d_22_ins11447

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/asrc/out_ratio_d_22_ins11447/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/asrc/out_ratio_d_22_ins11447/CLK

MPW7

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/asrc/asrc/ratio_dect/period_clkin_sync_14_ins11166

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/asrc/asrc/ratio_dect/period_clkin_sync_14_ins11166/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/asrc/asrc/ratio_dect/period_clkin_sync_14_ins11166/CLK

MPW8

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/asrc/asrc/ratio_dect/ratio_ave_reg_13_ins11308

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/asrc/asrc/ratio_dect/ratio_ave_reg_13_ins11308/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/asrc/asrc/ratio_dect/ratio_ave_reg_13_ins11308/CLK

MPW9

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/asrc/asrc/shared_divider/divisor_22_ins12007

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/asrc/asrc/shared_divider/divisor_22_ins12007/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/asrc/asrc/shared_divider/divisor_22_ins12007/CLK

MPW10

MPW Summary:

Slack:	3.662
Actual Width:	4.662
Required Width:	1.000
Type:	Low Pulse Width
Clock:	DEFAULT_CLK
Objects:	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			DEFAULT_CLK
5.000	0.000	tCL	FF	SYM_CLK_ibuf5427/I
5.688	0.688	tINS	FF	SYM_CLK_ibuf5427/O
6.916	1.228	tNET	FF	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			DEFAULT_CLK
10.000	0.000	tCL	RR	SYM_CLK_ibuf5427/I
10.675	0.675	tINS	RR	SYM_CLK_ibuf5427/O
11.577	0.902	tNET	RR	test_top/asrc/asrc/phase_interpolator/h1_8_ins12529/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1996	SYM_CLK_3	1.674	1.228
1012	n57	6.826	2.029
743	SW_d[1]	1.172	2.471
236	fir_init	5.448	2.602
130	mult2_b_8	2.037	1.817
123	incr_addr_r[1]	1.674	2.105
122	mult_b_sel[1]	2.590	2.733
99	mult_sel[1]	4.087	2.156
99	mult1_a_10_45	3.584	1.973
97	mult_sel[0]	4.162	2.469

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R27C37	0.833
R27C38	0.806
R30C30	0.806
R25C31	0.778
R37C18	0.764
R27C33	0.764
R25C28	0.750
R25C39	0.750
R34C33	0.750
R34C38	0.750

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command