Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\ipcore\ASRC\data\ASRC_Top_en.v
C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\ipcore\ASRC\data\ASRC_Top_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Fri May 22 16:40:07 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module ASRC_TOP
Synthesis Process Running parser:
    CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 84.582MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 84.582MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.253s, Peak memory usage = 84.582MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 84.582MB
    Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.415s, Peak memory usage = 84.582MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 84.582MB
    Inferring Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 84.582MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 84.582MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 84.582MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.29s, Peak memory usage = 84.582MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 84.582MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 84.582MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 108.801MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.365s, Peak memory usage = 108.801MB
Generate output files:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 111.246MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 111.246MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 317
I/O Buf 317
    IBUF 160
    OBUF 157
Register 1766
    DFFRE 70
    DFFPE 18
    DFFCE 1678
LUT 2299
    LUT2 449
    LUT3 531
    LUT4 1319
ALU 826
    ALU 826
INV 28
    INV 28
DSP
    MULT27X36 5
BSRAM 11
    SDPB 8
    pROM 3

Resource Utilization Summary

Resource Usage Utilization
Logic 3153(2327 LUT, 826 ALU) / 23040 14%
Register 1766 / 23685 8%
  --Register as Latch 0 / 23685 0%
  --Register as FF 1766 / 23685 8%
BSRAM 11 / 56 20%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 115.669(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.355
Data Arrival Time 5.719
Data Required Time 7.074
From ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
To ASRC_Top_inst/fir_filter/n529_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1790 clk_ibuf/O
0.337 0.337 tNET RR 16 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
2.146 1.809 tC2Q RR 1 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[2]
2.484 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s11/I0
2.958 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s11/F
3.295 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s13/I0
3.769 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s13/F
4.106 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s7/I0
4.580 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s7/F
4.917 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s5/I1
5.382 0.465 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_18_s5/F
5.719 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/B[18]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1790 clk_ibuf/O
10.337 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/CLK[0]
7.074 -3.263 tSu 1 ASRC_Top_inst/fir_filter/n529_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay: cell: 1.886, 35.033%; route: 1.687, 31.355%; tC2Q: 1.809, 33.612%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 2

Path Summary:
Slack 1.707
Data Arrival Time 5.491
Data Required Time 7.198
From ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
To ASRC_Top_inst/fir_filter/n529_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1790 clk_ibuf/O
0.337 0.337 tNET RR 16 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
2.146 1.809 tC2Q RR 1 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[5]
2.484 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s10/I0
2.958 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s10/F
3.295 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s12/I0
3.769 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s12/F
4.106 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s8/I0
4.580 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s8/F
4.917 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s5/I3
5.154 0.236 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_21_s5/F
5.491 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/B[21]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1790 clk_ibuf/O
10.337 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/CLK[0]
7.198 -3.139 tSu 1 ASRC_Top_inst/fir_filter/n529_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay: cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 3

Path Summary:
Slack 1.758
Data Arrival Time 5.719
Data Required Time 7.477
From ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
To ASRC_Top_inst/fir_filter/n529_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1790 clk_ibuf/O
0.337 0.337 tNET RR 16 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
2.146 1.809 tC2Q RR 1 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[10]
2.484 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s11/I0
2.958 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s11/F
3.295 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s13/I0
3.769 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s13/F
4.106 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s7/I0
4.580 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s7/F
4.917 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s5/I1
5.382 0.465 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_26_s5/F
5.719 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/B[26]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1790 clk_ibuf/O
10.337 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/CLK[0]
7.477 -2.860 tSu 1 ASRC_Top_inst/fir_filter/n529_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay: cell: 1.886, 35.033%; route: 1.687, 31.355%; tC2Q: 1.809, 33.612%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 4

Path Summary:
Slack 1.786
Data Arrival Time 5.491
Data Required Time 7.277
From ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
To ASRC_Top_inst/fir_filter/n529_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1790 clk_ibuf/O
0.337 0.337 tNET RR 16 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
2.146 1.809 tC2Q RR 1 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[7]
2.484 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s10/I0
2.958 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s10/F
3.295 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s12/I0
3.769 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s12/F
4.106 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s8/I0
4.580 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s8/F
4.917 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s5/I3
5.154 0.236 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_23_s5/F
5.491 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/B[23]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1790 clk_ibuf/O
10.337 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/CLK[0]
7.277 -3.060 tSu 1 ASRC_Top_inst/fir_filter/n529_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay: cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 5

Path Summary:
Slack 1.903
Data Arrival Time 5.491
Data Required Time 7.394
From ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
To ASRC_Top_inst/fir_filter/n529_s
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 1790 clk_ibuf/O
0.337 0.337 tNET RR 16 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
2.146 1.809 tC2Q RR 1 ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[9]
2.484 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s10/I0
2.958 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s10/F
3.295 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s12/I0
3.769 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s12/F
4.106 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s8/I0
4.580 0.474 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s8/F
4.917 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s5/I3
5.154 0.236 tINS RR 1 ASRC_Top_inst/fir_filter/mult_b_25_s5/F
5.491 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/B[25]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 1790 clk_ibuf/O
10.337 0.337 tNET RR 1 ASRC_Top_inst/fir_filter/n529_s/CLK[0]
7.394 -2.943 tSu 1 ASRC_Top_inst/fir_filter/n529_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay: cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.337, 100.000%