Timing Messages

Report Title Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\impl\gwsynthesis\ASRC.vg
Physical Constraints File E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\asrc.cst
Timing Constraint File E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\asrc.sdc
Tool Version V1.9.12.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Fri Jun 12 16:43:36 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.873V 0C ES
Hold Delay Model Fast 0.927V 85C ES
Numbers of Paths Analyzed 7548
Numbers of Endpoints Analyzed 7526
Numbers of Falling Endpoints 3
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 tck_pad_i Base 50.000 20.000 0.000 25.000 tck_pad_i
2 sym_clk Base 20.000 50.000 0.000 10.000 SYM_CLK
3 in_clkout Base 10.000 100.000 0.000 5.000 test_top_inst_60_2

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 tck_pad_i 20.000(MHz) 166.316(MHz) 3 TOP
2 sym_clk 50.000(MHz) 95.871(MHz) 4 TOP
3 in_clkout 100.000(MHz) 198.534(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
tck_pad_i Setup 0.000 0
tck_pad_i Hold 0.000 0
sym_clk Setup 0.000 0
sym_clk Hold 0.000 0
in_clkout Setup 0.000 0
in_clkout Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 4.963 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.006 4.763
2 5.500 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.000 4.443
3 5.500 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.000 4.443
4 5.550 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.000 4.393
5 5.665 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.006 4.272
6 5.674 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.006 4.263
7 5.728 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.000 4.214
8 5.938 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.028 3.977
9 6.078 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.019 3.845
10 6.078 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.019 3.845
11 6.381 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.021 3.360
12 6.491 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.022 3.250
13 6.491 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.022 3.250
14 6.491 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.022 3.250
15 6.491 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.022 3.250
16 6.502 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D in_clkout:[R] in_clkout:[R] 10.000 0.019 3.421
17 6.660 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.015 3.075
18 6.660 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.015 3.075
19 6.843 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D in_clkout:[R] in_clkout:[R] 10.000 -0.008 3.108
20 6.873 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/start_reg_s0/D in_clkout:[R] in_clkout:[R] 10.000 -0.010 3.080
21 6.882 gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE in_clkout:[R] in_clkout:[R] 10.000 -0.011 2.848
22 6.906 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D in_clkout:[R] in_clkout:[R] 10.000 -0.009 3.045
23 6.953 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/Q gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE in_clkout:[R] in_clkout:[R] 10.000 0.020 2.747
24 6.973 gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D in_clkout:[R] in_clkout:[R] 10.000 -0.026 2.995
25 6.979 gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D in_clkout:[R] in_clkout:[R] 10.000 -0.017 2.981

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5] in_clkout:[R] in_clkout:[R] 0.000 -0.009 0.256
2 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[4] in_clkout:[R] in_clkout:[R] 0.000 -0.009 0.256
3 0.213 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] in_clkout:[R] in_clkout:[R] 0.000 -0.009 0.256
4 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] in_clkout:[R] in_clkout:[R] 0.000 -0.005 0.254
5 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8] in_clkout:[R] in_clkout:[R] 0.000 -0.004 0.254
6 0.216 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0] in_clkout:[R] in_clkout:[R] 0.000 -0.004 0.254
7 0.218 test_top_inst/asrc/ASRC_Top_inst/input_storage0/read_addr_7_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/ADB[11] sym_clk:[R] sym_clk:[R] 0.000 0.019 0.230
8 0.222 test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/ADA[9] sym_clk:[R] sym_clk:[R] 0.000 0.022 0.233
9 0.222 test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/ADA[9] sym_clk:[R] sym_clk:[R] 0.000 0.019 0.237
10 0.223 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[6] in_clkout:[R] in_clkout:[R] 0.000 -0.004 0.261
11 0.225 test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_6_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/ADA[10] sym_clk:[R] sym_clk:[R] 0.000 0.022 0.236
12 0.247 test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.270
13 0.247 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/Q test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.270
14 0.247 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/Q test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.270
15 0.247 test_top_inst/cnt_cycle_clkin_5_s0/Q test_top_inst/cnt_cycle_clkin_5_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.270
16 0.247 test_top_inst/mem_addr_1_s1/Q test_top_inst/mem_addr_1_s1/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.270
17 0.247 gw_gao_inst_0/u_la0_top/word_count_0_s0/Q gw_gao_inst_0/u_la0_top/word_count_0_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.270
18 0.247 gw_gao_inst_0/u_la0_top/word_count_13_s0/Q gw_gao_inst_0/u_la0_top/word_count_13_s0/D tck_pad_i:[R] tck_pad_i:[R] 0.000 0.000 0.270
19 0.250 test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
20 0.250 test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
21 0.250 test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
22 0.250 test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
23 0.250 test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
24 0.250 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/Q test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273
25 0.250 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/Q test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/D sym_clk:[R] sym_clk:[R] 0.000 0.000 0.273

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 2.227 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.061 2.521
2 2.236 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.070 2.521
3 2.236 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.070 2.521
4 2.425 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.078 2.340
5 2.643 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.091 2.136
6 2.813 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.096 1.970
7 2.813 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.096 1.970
8 2.813 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.096 1.970
9 2.924 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET in_clkout:[F] in_clkout:[R] 5.000 -0.070 1.833
10 2.924 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.070 1.833
11 2.924 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.070 1.833
12 2.924 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.070 1.833
13 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.057 1.638
14 3.106 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.057 1.638
15 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.066 1.638
16 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.066 1.638
17 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.066 1.638
18 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.066 1.638
19 3.115 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.066 1.638
20 3.139 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.074 1.622
21 3.139 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.074 1.622
22 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.083 1.624
23 3.146 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.083 1.624
24 3.153 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.089 1.624
25 3.153 gw_gao_inst_0/u_la0_top/rst_ao_s0/Q gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR in_clkout:[F] in_clkout:[R] 5.000 -0.089 1.624

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.235 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.009 1.234
2 1.235 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.009 1.234
3 1.238 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.234
4 1.238 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.234
5 1.238 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_4_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.234
6 1.238 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_1_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.234
7 1.242 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.002 1.234
8 1.242 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/RESET sym_clk:[R] sym_clk:[R] 0.000 -0.002 1.234
9 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_valid_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
10 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_12_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
11 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_13_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
12 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_18_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
13 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_acc2_0_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
14 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_12_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
15 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_13_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
16 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_18_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
17 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_19_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
18 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_20_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
19 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_21_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
20 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_22_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
21 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_23_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
22 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[0]_0_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
23 1.269 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[1]_0_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.005 1.226
24 1.273 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_14_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.014 1.238
25 1.273 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_17_s0/CLEAR sym_clk:[R] sym_clk:[R] 0.000 -0.014 1.238

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 2.706 3.606 0.900 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
2 2.711 3.611 0.900 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
3 2.711 3.611 0.900 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
4 2.715 3.615 0.900 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
5 2.730 3.630 0.900 High Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
6 2.735 3.635 0.900 High Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
7 2.735 3.635 0.900 High Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
8 2.740 3.640 0.900 High Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
9 3.372 3.597 0.225 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
10 3.372 3.597 0.225 Low Pulse Width in_clkout gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 4.963
Data Arrival Time 7.242
Data Required Time 12.206
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.500 0.600 tNET RR 1 R25C51[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
6.948 0.448 tINS RR 1 R25C51[3][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
7.242 0.295 tNET RR 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.486 2.486 tNET RR 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.206 -0.280 tSu 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.006
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.759, 36.939%; route: 2.659, 55.834%; tC2Q: 0.344, 7.227%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%

Path2

Path Summary:

Slack 5.500
Data Arrival Time 6.922
Data Required Time 12.422
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.457 0.557 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n505_s1/I3
6.922 0.465 tINS RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n505_s1/F
6.922 0.000 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.422 -0.057 tSu 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.776, 39.985%; route: 2.322, 52.266%; tC2Q: 0.344, 7.749%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path3

Path Summary:

Slack 5.500
Data Arrival Time 6.922
Data Required Time 12.422
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.457 0.557 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n504_s1/I2
6.922 0.465 tINS RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n504_s1/F
6.922 0.000 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.422 -0.057 tSu 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.776, 39.985%; route: 2.322, 52.266%; tC2Q: 0.344, 7.749%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path4

Path Summary:

Slack 5.550
Data Arrival Time 6.872
Data Required Time 12.422
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.457 0.557 tNET RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n503_s1/I2
6.872 0.415 tINS RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n503_s1/F
6.872 0.000 tNET RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
12.422 -0.057 tSu 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.727, 39.309%; route: 2.322, 52.855%; tC2Q: 0.344, 7.836%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path5

Path Summary:

Slack 5.665
Data Arrival Time 6.751
Data Required Time 12.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.277 0.377 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n502_s1/I3
6.751 0.474 tINS RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n502_s1/F
6.751 0.000 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.415 -0.057 tSu 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.785, 41.796%; route: 2.142, 50.145%; tC2Q: 0.344, 8.059%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path6

Path Summary:

Slack 5.674
Data Arrival Time 6.742
Data Required Time 12.415
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.277 0.377 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s2/I2
6.742 0.465 tINS RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s2/F
6.742 0.000 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.415 -0.057 tSu 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew -0.006
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.776, 41.673%; route: 2.142, 50.251%; tC2Q: 0.344, 8.076%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path7

Path Summary:

Slack 5.728
Data Arrival Time 6.693
Data Required Time 12.422
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.457 0.557 tNET RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n501_s1/I2
6.693 0.236 tINS RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n501_s1/F
6.693 0.000 tNET RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.422 -0.057 tSu 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.548, 36.733%; route: 2.322, 55.099%; tC2Q: 0.344, 8.169%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path8

Path Summary:

Slack 5.938
Data Arrival Time 6.456
Data Required Time 12.394
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
6.220 0.319 tNET RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n507_s1/I3
6.456 0.236 tINS RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n507_s1/F
6.456 0.000 tNET RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.451 2.451 tNET RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
12.394 -0.057 tSu 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew -0.028
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.548, 38.925%; route: 2.085, 52.419%; tC2Q: 0.344, 8.656%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.451, 100.000%

Path9

Path Summary:

Slack 6.078
Data Arrival Time 6.324
Data Required Time 12.402
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
5.909 0.009 tNET RR 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n508_s1/I2
6.324 0.415 tINS RR 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n508_s1/F
6.324 0.000 tNET RR 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.402 -0.057 tSu 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.727, 44.909%; route: 1.774, 46.138%; tC2Q: 0.344, 8.953%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path10

Path Summary:

Slack 6.078
Data Arrival Time 6.324
Data Required Time 12.402
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/I1
5.900 0.474 tINS RR 10 R29C52[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s4/F
5.909 0.009 tNET RR 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n506_s1/I2
6.324 0.415 tINS RR 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n506_s1/F
6.324 0.000 tNET RR 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.402 -0.057 tSu 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.727, 44.909%; route: 1.774, 46.138%; tC2Q: 0.344, 8.953%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path11

Path Summary:

Slack 6.381
Data Arrival Time 5.820
Data Required Time 12.201
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.460 2.460 tNET RR 1 R29C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
2.791 0.331 tC2Q RF 4 R29C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/Q
3.161 0.370 tNET FF 1 R25C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s3/I1
3.576 0.415 tINS FR 3 R25C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s3/F
3.962 0.386 tNET RR 1 R29C50[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/I2
4.426 0.465 tINS RR 2 R29C50[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s4/F
4.814 0.388 tNET RR 1 R27C49[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/I0
5.230 0.415 tINS RR 1 R27C49[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s5/F
5.232 0.002 tNET RR 1 R27C49[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I2
5.696 0.465 tINS RR 1 R27C49[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
5.820 0.124 tNET RR 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.481 2.481 tNET RR 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.201 -0.280 tSu 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.021
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%
Arrival Data Path Delay cell: 1.760, 52.360%; route: 1.270, 37.797%; tC2Q: 0.331, 9.843%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.481, 100.000%

Path12

Path Summary:

Slack 6.491
Data Arrival Time 5.708
Data Required Time 12.199
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.708 0.862 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.199 -0.280 tSu 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 11.492%; route: 2.532, 77.916%; tC2Q: 0.344, 10.592%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path13

Path Summary:

Slack 6.491
Data Arrival Time 5.708
Data Required Time 12.199
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.708 0.862 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.199 -0.280 tSu 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 11.492%; route: 2.532, 77.916%; tC2Q: 0.344, 10.592%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path14

Path Summary:

Slack 6.491
Data Arrival Time 5.708
Data Required Time 12.199
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.708 0.862 tNET RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
12.199 -0.280 tSu 1 R26C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 11.492%; route: 2.532, 77.916%; tC2Q: 0.344, 10.592%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path15

Path Summary:

Slack 6.491
Data Arrival Time 5.708
Data Required Time 12.199
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.708 0.862 tNET RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.199 -0.280 tSu 1 R26C52[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew 0.022
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 11.492%; route: 2.532, 77.916%; tC2Q: 0.344, 10.592%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path16

Path Summary:

Slack 6.502
Data Arrival Time 5.900
Data Required Time 12.402
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
2.823 0.344 tC2Q RR 9 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
3.861 1.037 tNET RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/I0
4.325 0.465 tINS RR 1 R21C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s12/F
4.670 0.344 tNET RR 1 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/I3
5.043 0.373 tINS RR 2 R25C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n500_s6/F
5.427 0.384 tNET RR 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n509_s2/I2
5.900 0.474 tINS RR 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n509_s2/F
5.900 0.000 tNET RR 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
12.402 -0.057 tSu 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew -0.019
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%
Arrival Data Path Delay cell: 1.312, 38.343%; route: 1.765, 51.595%; tC2Q: 0.344, 10.062%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path17

Path Summary:

Slack 6.660
Data Arrival Time 5.532
Data Required Time 12.193
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.532 0.686 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.193 -0.280 tSu 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.015
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 12.148%; route: 2.357, 76.656%; tC2Q: 0.344, 11.196%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path18

Path Summary:

Slack 6.660
Data Arrival Time 5.532
Data Required Time 12.193
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.472 1.671 tNET RR 1 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/I1
4.846 0.373 tINS RR 10 R29C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/F
5.532 0.686 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.193 -0.280 tSu 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.015
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.373, 12.148%; route: 2.357, 76.656%; tC2Q: 0.344, 11.196%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path19

Path Summary:

Slack 6.843
Data Arrival Time 5.586
Data Required Time 12.428
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.477 2.477 tNET RR 1 R25C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
2.821 0.344 tC2Q RR 5 R25C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
3.539 0.718 tNET RR 1 R29C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s2/I3
3.987 0.448 tINS RR 6 R29C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n410_s2/F
4.704 0.717 tNET RR 1 R25C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s1/I1
5.168 0.465 tINS RR 1 R25C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s1/F
5.170 0.002 tNET RR 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s4/I0
5.586 0.415 tINS RR 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n405_s4/F
5.586 0.000 tNET RR 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.486 2.486 tNET RR 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.428 -0.057 tSu 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.008
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.477, 100.000%
Arrival Data Path Delay cell: 1.327, 42.707%; route: 1.437, 46.218%; tC2Q: 0.344, 11.075%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%

Path20

Path Summary:

Slack 6.873
Data Arrival Time 5.536
Data Required Time 12.409
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.456 2.456 tNET RR 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
2.800 0.344 tC2Q RR 11 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
3.243 0.443 tNET RR 2 R15C51[0][B] gw_gao_inst_0/u_la0_top/n2503_s21/I1
3.686 0.443 tINS RR 1 R15C51[0][B] gw_gao_inst_0/u_la0_top/n2503_s21/COUT
3.686 0.000 tNET RR 2 R15C51[1][A] gw_gao_inst_0/u_la0_top/n2503_s22/CIN
3.731 0.045 tINS RR 1 R15C51[1][A] gw_gao_inst_0/u_la0_top/n2503_s22/COUT
3.731 0.000 tNET RR 2 R15C51[1][B] gw_gao_inst_0/u_la0_top/n2503_s23/CIN
3.776 0.045 tINS RR 1 R15C51[1][B] gw_gao_inst_0/u_la0_top/n2503_s23/COUT
3.776 0.000 tNET RR 2 R15C51[2][A] gw_gao_inst_0/u_la0_top/n2503_s24/CIN
3.821 0.045 tINS RR 1 R15C51[2][A] gw_gao_inst_0/u_la0_top/n2503_s24/COUT
3.821 0.000 tNET RR 2 R15C51[2][B] gw_gao_inst_0/u_la0_top/n2503_s25/CIN
3.866 0.045 tINS RR 1 R15C51[2][B] gw_gao_inst_0/u_la0_top/n2503_s25/COUT
3.866 0.000 tNET RR 2 R15C52[0][A] gw_gao_inst_0/u_la0_top/n2503_s26/CIN
3.911 0.045 tINS RR 1 R15C52[0][A] gw_gao_inst_0/u_la0_top/n2503_s26/COUT
3.911 0.000 tNET RR 2 R15C52[0][B] gw_gao_inst_0/u_la0_top/n2503_s27/CIN
3.956 0.045 tINS RR 1 R15C52[0][B] gw_gao_inst_0/u_la0_top/n2503_s27/COUT
3.956 0.000 tNET RR 2 R15C52[1][A] gw_gao_inst_0/u_la0_top/n2503_s28/CIN
4.001 0.045 tINS RR 2 R15C52[1][A] gw_gao_inst_0/u_la0_top/n2503_s28/COUT
4.689 0.687 tNET RR 1 R17C50[3][B] gw_gao_inst_0/u_la0_top/start_reg1_s1/I2
5.158 0.469 tINS RR 1 R17C50[3][B] gw_gao_inst_0/u_la0_top/start_reg1_s1/F
5.300 0.142 tNET RR 1 R18C50[0][B] gw_gao_inst_0/u_la0_top/start_reg1_s0/I1
5.536 0.236 tINS RR 1 R18C50[0][B] gw_gao_inst_0/u_la0_top/start_reg1_s0/F
5.536 0.000 tNET RR 1 R18C50[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.466 2.466 tNET RR 1 R18C50[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
12.409 -0.057 tSu 1 R18C50[0][B] gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew 0.010
Setup Relationship 10.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 1.464, 47.516%; route: 1.272, 41.308%; tC2Q: 0.344, 11.176%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.466, 100.000%

Path21

Path Summary:

Slack 6.882
Data Arrival Time 5.306
Data Required Time 12.188
From gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR 1 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
2.802 0.344 tC2Q RR 16 R18C51[3][B] gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/Q
4.767 1.965 tNET RR 1 R29C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/I3
5.182 0.415 tINS RR 1 R29C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s7/F
5.306 0.124 tNET RR 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.468 2.468 tNET RR 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.188 -0.280 tSu 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.011
Setup Relationship 10.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.458, 100.000%
Arrival Data Path Delay cell: 0.415, 14.573%; route: 2.089, 73.341%; tC2Q: 0.344, 12.085%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.468, 100.000%

Path22

Path Summary:

Slack 6.906
Data Arrival Time 5.501
Data Required Time 12.407
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.456 2.456 tNET RR 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
2.800 0.344 tC2Q RR 11 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
4.169 1.369 tNET RR 1 R27C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I1
4.634 0.465 tINS RR 1 R27C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
4.636 0.002 tNET RR 1 R27C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s13/I0
5.084 0.448 tINS RR 1 R27C51[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s13/F
5.086 0.002 tNET RR 1 R27C51[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I3
5.501 0.415 tINS RR 1 R27C51[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
5.501 0.000 tNET RR 1 R27C51[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.464 2.464 tNET RR 1 R27C51[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
12.407 -0.057 tSu 1 R27C51[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0

Path Statistics:

Clock Skew 0.009
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 1.327, 43.591%; route: 1.374, 45.105%; tC2Q: 0.344, 11.304%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.464, 100.000%

Path23

Path Summary:

Slack 6.953
Data Arrival Time 5.233
Data Required Time 12.186
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
To gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.486 2.486 tNET RR 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
2.830 0.344 tC2Q RR 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/Q
3.588 0.758 tNET RR 1 R18C50[3][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s4/I3
4.036 0.448 tINS RR 4 R18C50[3][B] gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s4/F
4.043 0.007 tNET RR 1 R18C50[2][B] gw_gao_inst_0/u_la0_top/n2573_s1/I1
4.516 0.474 tINS RR 1 R18C50[2][B] gw_gao_inst_0/u_la0_top/n2573_s1/F
4.640 0.124 tNET RR 1 R18C50[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.109 0.469 tINS RR 1 R18C50[3][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
5.233 0.124 tNET RR 1 R18C50[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.466 2.466 tNET RR 1 R18C50[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.186 -0.280 tSu 1 R18C50[1][A] gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew -0.020
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%
Arrival Data Path Delay cell: 1.391, 50.614%; route: 1.012, 36.855%; tC2Q: 0.344, 12.531%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.466, 100.000%

Path24

Path Summary:

Slack 6.973
Data Arrival Time 5.450
Data Required Time 12.424
From gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.456 2.456 tNET RR 1 R14C52[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
2.800 0.344 tC2Q RR 9 R14C52[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q
3.969 1.169 tNET RR 1 R27C50[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/I2
4.205 0.236 tINS RR 1 R27C50[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s12/F
4.207 0.002 tNET RR 1 R27C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/I3
4.655 0.448 tINS RR 1 R27C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s11/F
4.797 0.142 tNET RR 1 R27C49[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/I0
5.033 0.236 tINS RR 1 R27C49[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s10/F
5.035 0.002 tNET RR 1 R27C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/I1
5.450 0.415 tINS RR 1 R27C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_7_s8/F
5.450 0.000 tNET RR 1 R27C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.481 2.481 tNET RR 1 R27C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0/CLK
12.424 -0.057 tSu 1 R27C49[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_7_s0

Path Statistics:

Clock Skew 0.026
Setup Relationship 10.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 1.335, 44.591%; route: 1.315, 43.914%; tC2Q: 0.344, 11.495%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.481, 100.000%

Path25

Path Summary:

Slack 6.979
Data Arrival Time 5.437
Data Required Time 12.415
From gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
2.456 2.456 tNET RR 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
2.800 0.344 tC2Q RR 11 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
4.047 1.248 tNET RR 1 R27C51[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/I1
4.463 0.415 tINS RR 1 R27C51[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s10/F
4.465 0.002 tNET RR 1 R27C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s9/I0
4.880 0.415 tINS RR 1 R27C51[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s9/F
5.022 0.142 tNET RR 1 R27C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/I3
5.437 0.415 tINS RR 1 R27C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_6_s7/F
5.437 0.000 tNET RR 1 R27C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0/CLK
12.415 -0.057 tSu 1 R27C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_6_s0

Path Statistics:

Clock Skew 0.017
Setup Relationship 10.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%
Arrival Data Path Delay cell: 1.245, 41.774%; route: 1.392, 46.679%; tC2Q: 0.344, 11.547%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.213
Data Arrival Time 1.257
Data Required Time 1.044
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.002 1.002 tNET RR 1 R32C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK
1.131 0.130 tC2Q RR 1 R32C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q
1.257 0.126 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[5]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.011 1.011 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.044 0.033 tHld 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 49.296%; tC2Q: 0.130, 50.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.011, 100.000%

Path2

Path Summary:

Slack 0.213
Data Arrival Time 1.257
Data Required Time 1.044
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.002 1.002 tNET RR 1 R32C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/CLK
1.131 0.130 tC2Q RR 1 R32C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q
1.257 0.126 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[4]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.011 1.011 tNET RR 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.044 0.033 tHld 1 BSRAM_R28[16] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.002, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 49.296%; tC2Q: 0.130, 50.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.011, 100.000%

Path3

Path Summary:

Slack 0.213
Data Arrival Time 1.250
Data Required Time 1.037
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
0.994 0.994 tNET RR 1 R30C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
1.124 0.130 tC2Q RR 1 R30C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
1.250 0.126 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.003 1.003 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.037 0.033 tHld 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.994, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.126, 49.296%; tC2Q: 0.130, 50.704%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.003, 100.000%

Path4

Path Summary:

Slack 0.216
Data Arrival Time 1.256
Data Required Time 1.040
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.003 1.003 tNET RR 1 R29C44[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK
1.132 0.130 tC2Q RR 1 R29C44[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q
1.256 0.124 tNET RR 1 BSRAM_R28[13] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.007 1.007 tNET RR 1 BSRAM_R28[13] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.040 0.033 tHld 1 BSRAM_R28[13] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.003, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.007, 100.000%

Path5

Path Summary:

Slack 0.216
Data Arrival Time 1.253
Data Required Time 1.037
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
0.999 0.999 tNET RR 1 R29C47[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
1.129 0.130 tC2Q RR 1 R29C47[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
1.253 0.124 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.003 1.003 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.037 0.033 tHld 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.999, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.003, 100.000%

Path6

Path Summary:

Slack 0.216
Data Arrival Time 1.253
Data Required Time 1.037
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
0.999 0.999 tNET RR 1 R29C47[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK
1.129 0.130 tC2Q RR 1 R29C47[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q
1.253 0.124 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.003 1.003 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.037 0.033 tHld 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.999, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 48.936%; tC2Q: 0.130, 51.064%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.003, 100.000%

Path7

Path Summary:

Slack 0.218
Data Arrival Time 1.648
Data Required Time 1.430
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/read_addr_7_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.417 0.644 tNET RR 1 R24C24[3][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/read_addr_7_s0/CLK
1.547 0.130 tC2Q RR 14 R24C24[3][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/read_addr_7_s0/Q
1.648 0.101 tNET RR 1 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/ADB[11]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/CLKB
1.430 0.032 tHld 1 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s

Path Statistics:

Clock Skew -0.019
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.773, 54.545%; route: 0.644, 45.455%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.101, 43.750%; tC2Q: 0.130, 56.250%
Required Clock Path Delay cell: 0.773, 55.274%; route: 0.625, 44.726%

Path8

Path Summary:

Slack 0.222
Data Arrival Time 1.654
Data Required Time 1.432
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C33[2][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/CLK
1.550 0.130 tC2Q RR 17 R24C33[2][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/Q
1.654 0.103 tNET RR 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/CLKA
1.432 0.033 tHld 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s

Path Statistics:

Clock Skew -0.022
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.103, 44.402%; tC2Q: 0.130, 55.598%
Required Clock Path Delay cell: 0.773, 55.274%; route: 0.625, 44.726%

Path9

Path Summary:

Slack 0.222
Data Arrival Time 1.657
Data Required Time 1.435
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C33[2][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/CLK
1.550 0.130 tC2Q RR 17 R24C33[2][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_5_s0/Q
1.657 0.107 tNET RR 1 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/ADA[9]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.402 0.629 tNET RR 1 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKA
1.435 0.033 tHld 1 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s

Path Statistics:

Clock Skew -0.019
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.107, 45.247%; tC2Q: 0.130, 54.753%
Required Clock Path Delay cell: 0.773, 55.132%; route: 0.629, 44.868%

Path10

Path Summary:

Slack 0.223
Data Arrival Time 1.260
Data Required Time 1.037
From gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk in_clkout:[R]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
0.999 0.999 tNET RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
1.129 0.130 tC2Q RR 8 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/Q
1.260 0.131 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[6]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
1.003 1.003 tNET RR 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.037 0.033 tHld 1 BSRAM_R28[14] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew 0.004
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.999, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.131, 50.345%; tC2Q: 0.130, 49.655%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.003, 100.000%

Path11

Path Summary:

Slack 0.225
Data Arrival Time 1.657
Data Required Time 1.432
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_6_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C33[2][B] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_6_s0/CLK
1.550 0.130 tC2Q RR 15 R24C33[2][B] test_top_inst/asrc/ASRC_Top_inst/input_storage0/write_addr_6_s0/Q
1.657 0.106 tNET RR 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/ADA[10]

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/CLKA
1.432 0.033 tHld 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s

Path Statistics:

Clock Skew -0.022
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.106, 45.038%; tC2Q: 0.130, 54.962%
Required Clock Path Delay cell: 0.773, 55.274%; route: 0.625, 44.726%

Path12

Path Summary:

Slack 0.247
Data Arrival Time 1.685
Data Required Time 1.438
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.415 0.642 tNET RR 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/CLK
1.542 0.127 tC2Q RF 3 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/Q
1.547 0.005 tNET FF 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n499_s2/I3
1.685 0.138 tINS FF 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n499_s2/F
1.685 0.000 tNET FF 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.415 0.642 tNET RR 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0/CLK
1.438 0.022 tHld 1 R23C31[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_in_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 54.623%; route: 0.642, 45.377%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 0.773, 54.623%; route: 0.642, 45.377%

Path13

Path Summary:

Slack 0.247
Data Arrival Time 1.673
Data Required Time 1.425
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0
To test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/CLK
1.529 0.127 tC2Q RF 3 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/Q
1.535 0.005 tNET FF 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n76_s2/I3
1.673 0.138 tINS FF 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n76_s2/F
1.673 0.000 tNET FF 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0/CLK
1.425 0.022 tHld 1 R35C44[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%

Path14

Path Summary:

Slack 0.247
Data Arrival Time 1.674
Data Required Time 1.426
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0
To test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.404 0.631 tNET RR 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/CLK
1.531 0.127 tC2Q RF 2 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/Q
1.536 0.005 tNET FF 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n64_s2/I3
1.674 0.138 tINS FF 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n64_s2/F
1.674 0.000 tNET FF 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.404 0.631 tNET RR 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0/CLK
1.426 0.022 tHld 1 R33C45[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/period_clkin_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.061%; route: 0.631, 44.939%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 0.773, 55.061%; route: 0.631, 44.939%

Path15

Path Summary:

Slack 0.247
Data Arrival Time 1.670
Data Required Time 1.423
From test_top_inst/cnt_cycle_clkin_5_s0
To test_top_inst/cnt_cycle_clkin_5_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.400 0.627 tNET RR 1 R15C48[0][A] test_top_inst/cnt_cycle_clkin_5_s0/CLK
1.527 0.127 tC2Q RF 4 R15C48[0][A] test_top_inst/cnt_cycle_clkin_5_s0/Q
1.533 0.005 tNET FF 1 R15C48[0][A] test_top_inst/n289_s2/I2
1.670 0.138 tINS FF 1 R15C48[0][A] test_top_inst/n289_s2/F
1.670 0.000 tNET FF 1 R15C48[0][A] test_top_inst/cnt_cycle_clkin_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.400 0.627 tNET RR 1 R15C48[0][A] test_top_inst/cnt_cycle_clkin_5_s0/CLK
1.423 0.022 tHld 1 R15C48[0][A] test_top_inst/cnt_cycle_clkin_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.202%; route: 0.627, 44.798%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 0.773, 55.202%; route: 0.627, 44.798%

Path16

Path Summary:

Slack 0.247
Data Arrival Time 1.673
Data Required Time 1.425
From test_top_inst/mem_addr_1_s1
To test_top_inst/mem_addr_1_s1
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R17C48[1][A] test_top_inst/mem_addr_1_s1/CLK
1.529 0.127 tC2Q RF 4 R17C48[1][A] test_top_inst/mem_addr_1_s1/Q
1.535 0.005 tNET FF 1 R17C48[1][A] test_top_inst/n256_s0/I3
1.673 0.138 tINS FF 1 R17C48[1][A] test_top_inst/n256_s0/F
1.673 0.000 tNET FF 1 R17C48[1][A] test_top_inst/mem_addr_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R17C48[1][A] test_top_inst/mem_addr_1_s1/CLK
1.425 0.022 tHld 1 R17C48[1][A] test_top_inst/mem_addr_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%

Path17

Path Summary:

Slack 0.247
Data Arrival Time 2.675
Data Required Time 2.427
From gw_gao_inst_0/u_la0_top/word_count_0_s0
To gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.773 0.773 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.773 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.381 0.608 tINS RR 298 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.405 1.024 tNET RR 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.532 0.127 tC2Q RF 5 R6C50[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.537 0.005 tNET FF 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.675 0.138 tINS FF 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.675 0.000 tNET FF 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.773 0.773 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.773 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.381 0.608 tINS RR 298 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.405 1.024 tNET RR 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.427 0.022 tHld 1 R6C50[0][A] gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.381, 57.422%; route: 1.024, 42.578%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 1.381, 57.422%; route: 1.024, 42.578%

Path18

Path Summary:

Slack 0.247
Data Arrival Time 2.681
Data Required Time 2.433
From gw_gao_inst_0/u_la0_top/word_count_13_s0
To gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk tck_pad_i:[R]
Latch Clk tck_pad_i:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.773 0.773 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.773 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.381 0.608 tINS RR 298 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.411 1.030 tNET RR 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.537 0.127 tC2Q RF 4 R7C52[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
2.543 0.005 tNET FF 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I1
2.681 0.138 tINS FF 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
2.681 0.000 tNET FF 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 tck_pad_i
0.000 0.000 tCL RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/I
0.773 0.773 tINS RR 1 IOR1[A] gw_gao_inst_0/tck_ibuf/O
0.773 0.000 tNET RR 1 R28C89 gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.381 0.608 tINS RR 298 R28C89 gw_gao_inst_0/u_gw_jtag/tck_o
2.411 1.030 tNET RR 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.433 0.022 tHld 1 R7C52[0][A] gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.381, 57.288%; route: 1.030, 42.712%
Arrival Data Path Delay cell: 0.138, 51.000%; route: 0.005, 2.000%; tC2Q: 0.127, 47.000%
Required Clock Path Delay cell: 1.381, 57.288%; route: 1.030, 42.712%

Path19

Path Summary:

Slack 0.250
Data Arrival Time 1.680
Data Required Time 1.430
From test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.407 0.634 tNET RR 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/CLK
1.534 0.127 tC2Q RF 30 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/Q
1.542 0.008 tNET FF 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n2782_s3/I2
1.680 0.138 tINS FF 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n2782_s3/F
1.680 0.000 tNET FF 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.407 0.634 tNET RR 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0/CLK
1.430 0.022 tHld 1 R8C23[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_sel_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 54.920%; route: 0.634, 45.080%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 54.920%; route: 0.634, 45.080%

Path20

Path Summary:

Slack 0.250
Data Arrival Time 1.670
Data Required Time 1.420
From test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/CLK
1.524 0.127 tC2Q RF 4 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/Q
1.533 0.008 tNET FF 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n955_s3/I0
1.670 0.138 tINS FF 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n955_s3/F
1.670 0.000 tNET FF 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0/CLK
1.420 0.022 tHld 1 R11C24[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mem_write_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.309%; route: 0.625, 44.691%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 55.309%; route: 0.625, 44.691%

Path21

Path Summary:

Slack 0.250
Data Arrival Time 1.690
Data Required Time 1.440
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.417 0.644 tNET RR 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/CLK
1.544 0.127 tC2Q RF 3 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/Q
1.552 0.008 tNET FF 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n453_s2/I2
1.690 0.138 tINS FF 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n453_s2/F
1.690 0.000 tNET FF 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.417 0.644 tNET RR 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0/CLK
1.440 0.022 tHld 1 R24C30[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 54.545%; route: 0.644, 45.455%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 54.545%; route: 0.644, 45.455%

Path22

Path Summary:

Slack 0.250
Data Arrival Time 1.693
Data Required Time 1.443
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/CLK
1.548 0.127 tC2Q RF 4 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/Q
1.556 0.008 tNET FF 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n451_s2/I2
1.693 0.138 tINS FF 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n451_s2/F
1.693 0.000 tNET FF 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0/CLK
1.443 0.022 tHld 1 R24C29[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%

Path23

Path Summary:

Slack 0.250
Data Arrival Time 1.693
Data Required Time 1.443
From test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/CLK
1.548 0.127 tC2Q RF 3 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/Q
1.556 0.008 tNET FF 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n448_s2/I2
1.693 0.138 tINS FF 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n448_s2/F
1.693 0.000 tNET FF 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.421 0.648 tNET RR 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0/CLK
1.443 0.022 tHld 1 R24C29[0][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/cnt_fract_period_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 54.407%; route: 0.648, 45.593%

Path24

Path Summary:

Slack 0.250
Data Arrival Time 1.675
Data Required Time 1.425
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0
To test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/CLK
1.529 0.127 tC2Q RF 6 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/Q
1.538 0.008 tNET FF 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n298_s2/I1
1.675 0.138 tINS FF 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n298_s2/F
1.675 0.000 tNET FF 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.403 0.630 tNET RR 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0/CLK
1.425 0.022 tHld 1 R35C48[1][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkin_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 55.114%; route: 0.630, 44.886%

Path25

Path Summary:

Slack 0.250
Data Arrival Time 1.673
Data Required Time 1.422
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0
To test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.400 0.627 tNET RR 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/CLK
1.527 0.127 tC2Q RF 6 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/Q
1.535 0.008 tNET FF 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n621_s2/I1
1.673 0.138 tINS FF 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/n621_s2/F
1.673 0.000 tNET FF 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.400 0.627 tNET RR 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0/CLK
1.422 0.022 tHld 1 R31C46[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/cnt_clkout_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.220%; route: 0.627, 44.780%
Arrival Data Path Delay cell: 0.138, 50.495%; route: 0.008, 2.970%; tC2Q: 0.127, 46.535%
Required Clock Path Delay cell: 0.773, 55.220%; route: 0.627, 44.780%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 2.227
Data Arrival Time 9.911
Data Required Time 12.139
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.911 2.123 tNET FF 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.451 2.451 tNET RR 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
12.139 -0.313 tSu 1 R29C51[2][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew 0.061
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.123, 84.205%; tC2Q: 0.398, 15.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.451, 100.000%

Path2

Path Summary:

Slack 2.236
Data Arrival Time 9.911
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.911 2.123 tNET FF 1 R29C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
12.147 -0.313 tSu 1 R29C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.123, 84.205%; tC2Q: 0.398, 15.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path3

Path Summary:

Slack 2.236
Data Arrival Time 9.911
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.911 2.123 tNET FF 1 R29C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.147 -0.313 tSu 1 R29C50[2][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.123, 84.205%; tC2Q: 0.398, 15.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path4

Path Summary:

Slack 2.425
Data Arrival Time 9.730
Data Required Time 12.155
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.730 1.942 tNET FF 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.468 2.468 tNET RR 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.155 -0.313 tSu 1 R29C49[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew 0.078
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.942, 82.983%; tC2Q: 0.398, 17.017%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.468, 100.000%

Path5

Path Summary:

Slack 2.643
Data Arrival Time 9.526
Data Required Time 12.168
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.526 1.737 tNET FF 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.481 2.481 tNET RR 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.168 -0.313 tSu 1 R27C49[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew 0.091
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.737, 81.351%; tC2Q: 0.398, 18.649%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.481, 100.000%

Path6

Path Summary:

Slack 2.813
Data Arrival Time 9.360
Data Required Time 12.173
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.360 1.572 tNET FF 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.486 2.486 tNET RR 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.173 -0.313 tSu 1 R25C50[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew 0.096
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.572, 79.786%; tC2Q: 0.398, 20.214%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%

Path7

Path Summary:

Slack 2.813
Data Arrival Time 9.360
Data Required Time 12.173
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.360 1.572 tNET FF 1 R25C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.486 2.486 tNET RR 1 R25C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.173 -0.313 tSu 1 R25C50[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew 0.096
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.572, 79.786%; tC2Q: 0.398, 20.214%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%

Path8

Path Summary:

Slack 2.813
Data Arrival Time 9.360
Data Required Time 12.173
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.360 1.572 tNET FF 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.486 2.486 tNET RR 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.173 -0.313 tSu 1 R25C50[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew 0.096
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.572, 79.786%; tC2Q: 0.398, 20.214%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.486, 100.000%

Path9

Path Summary:

Slack 2.924
Data Arrival Time 9.223
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.223 1.435 tNET FF 1 R29C52[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.147 -0.313 tSu 1 R29C52[3][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.435, 78.272%; tC2Q: 0.398, 21.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path10

Path Summary:

Slack 2.924
Data Arrival Time 9.223
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.223 1.435 tNET FF 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
12.147 -0.313 tSu 1 R29C52[0][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.435, 78.272%; tC2Q: 0.398, 21.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path11

Path Summary:

Slack 2.924
Data Arrival Time 9.223
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.223 1.435 tNET FF 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.147 -0.313 tSu 1 R29C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.435, 78.272%; tC2Q: 0.398, 21.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path12

Path Summary:

Slack 2.924
Data Arrival Time 9.223
Data Required Time 12.147
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.223 1.435 tNET FF 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.460 2.460 tNET RR 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.147 -0.313 tSu 1 R29C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew 0.070
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.435, 78.272%; tC2Q: 0.398, 21.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.460, 100.000%

Path13

Path Summary:

Slack 3.106
Data Arrival Time 9.028
Data Required Time 12.134
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C51[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.447 2.447 tNET RR 1 R14C51[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
12.134 -0.313 tSu 1 R14C51[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew 0.057
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.447, 100.000%

Path14

Path Summary:

Slack 3.106
Data Arrival Time 9.028
Data Required Time 12.134
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C51[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.447 2.447 tNET RR 1 R14C51[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
12.134 -0.313 tSu 1 R14C51[3][A] gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew 0.057
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.447, 100.000%

Path15

Path Summary:

Slack 3.115
Data Arrival Time 9.028
Data Required Time 12.143
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.456 2.456 tNET RR 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
12.143 -0.313 tSu 1 R14C52[2][A] gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew 0.066
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%

Path16

Path Summary:

Slack 3.115
Data Arrival Time 9.028
Data Required Time 12.143
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C52[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.456 2.456 tNET RR 1 R14C52[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
12.143 -0.313 tSu 1 R14C52[2][B] gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew 0.066
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%

Path17

Path Summary:

Slack 3.115
Data Arrival Time 9.028
Data Required Time 12.143
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C52[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.456 2.456 tNET RR 1 R14C52[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
12.143 -0.313 tSu 1 R14C52[1][A] gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew 0.066
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%

Path18

Path Summary:

Slack 3.115
Data Arrival Time 9.028
Data Required Time 12.143
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C52[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.456 2.456 tNET RR 1 R14C52[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
12.143 -0.313 tSu 1 R14C52[1][B] gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew 0.066
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%

Path19

Path Summary:

Slack 3.115
Data Arrival Time 9.028
Data Required Time 12.143
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.028 1.240 tNET FF 1 R14C52[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.456 2.456 tNET RR 1 R14C52[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
12.143 -0.313 tSu 1 R14C52[0][B] gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew 0.066
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.240, 75.687%; tC2Q: 0.398, 24.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.456, 100.000%

Path20

Path Summary:

Slack 3.139
Data Arrival Time 9.012
Data Required Time 12.151
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.012 1.224 tNET FF 1 R14C49[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.464 2.464 tNET RR 1 R14C49[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
12.151 -0.313 tSu 1 R14C49[2][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew 0.074
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.224, 75.451%; tC2Q: 0.398, 24.549%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.464, 100.000%

Path21

Path Summary:

Slack 3.139
Data Arrival Time 9.012
Data Required Time 12.151
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.012 1.224 tNET FF 1 R14C49[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.464 2.464 tNET RR 1 R14C49[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
12.151 -0.313 tSu 1 R14C49[0][B] gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew 0.074
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.224, 75.451%; tC2Q: 0.398, 24.549%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.464, 100.000%

Path22

Path Summary:

Slack 3.146
Data Arrival Time 9.014
Data Required Time 12.160
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.014 1.225 tNET FF 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.160 -0.313 tSu 1 R27C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew 0.083
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.225, 75.472%; tC2Q: 0.398, 24.528%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path23

Path Summary:

Slack 3.146
Data Arrival Time 9.014
Data Required Time 12.160
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.014 1.225 tNET FF 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.473 2.473 tNET RR 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.160 -0.313 tSu 1 R27C52[1][B] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew 0.083
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.225, 75.472%; tC2Q: 0.398, 24.528%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.473, 100.000%

Path24

Path Summary:

Slack 3.153
Data Arrival Time 9.014
Data Required Time 12.166
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.014 1.225 tNET FF 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.166 -0.313 tSu 1 R26C52[0][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew 0.089
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.225, 75.472%; tC2Q: 0.398, 24.528%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Path25

Path Summary:

Slack 3.153
Data Arrival Time 9.014
Data Required Time 12.166
From gw_gao_inst_0/u_la0_top/rst_ao_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk in_clkout:[F]
Latch Clk in_clkout:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
7.390 2.390 tNET FF 1 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.788 0.398 tC2Q FF 53 R15C48[3][A] gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.014 1.225 tNET FF 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR 184 R13C50[1][B] test_top_inst/clk_out_s1/Q
12.479 2.479 tNET RR 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.166 -0.313 tSu 1 R26C52[1][A] gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew 0.089
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 2.390, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.225, 75.472%; tC2Q: 0.398, 24.528%
Required Clock Path Delay cell: 0.000, 0.000%; route: 2.479, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.235
Data Arrival Time 2.631
Data Required Time 1.396
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.406 0.633 tNET RR 1 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB
1.396 -0.010 tHld 1 BSRAM_R28[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 54.990%; route: 0.633, 45.010%

Path2

Path Summary:

Slack 1.235
Data Arrival Time 2.631
Data Required Time 1.396
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R10[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.406 0.633 tNET RR 1 BSRAM_R10[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB
1.396 -0.010 tHld 1 BSRAM_R10[9] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s

Path Statistics:

Clock Skew 0.009
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 54.990%; route: 0.633, 45.010%

Path3

Path Summary:

Slack 1.238
Data Arrival Time 2.631
Data Required Time 1.392
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[12] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.402 0.629 tNET RR 1 BSRAM_R28[12] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB
1.392 -0.010 tHld 1 BSRAM_R28[12] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.132%; route: 0.629, 44.868%

Path4

Path Summary:

Slack 1.238
Data Arrival Time 2.631
Data Required Time 1.392
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.402 0.629 tNET RR 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s/CLKB
1.392 -0.010 tHld 1 BSRAM_R28[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_5_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.132%; route: 0.629, 44.868%

Path5

Path Summary:

Slack 1.238
Data Arrival Time 2.631
Data Required Time 1.392
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_4_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R10[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_4_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.402 0.629 tNET RR 1 BSRAM_R10[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_4_s/CLKB
1.392 -0.010 tHld 1 BSRAM_R10[10] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_4_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.132%; route: 0.629, 44.868%

Path6

Path Summary:

Slack 1.238
Data Arrival Time 2.631
Data Required Time 1.392
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_1_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[8] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_1_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.402 0.629 tNET RR 1 BSRAM_R28[8] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_1_s/CLKB
1.392 -0.010 tHld 1 BSRAM_R28[8] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_1_s

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.132%; route: 0.629, 44.868%

Path7

Path Summary:

Slack 1.242
Data Arrival Time 2.631
Data Required Time 1.389
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[11] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 BSRAM_R28[11] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/CLKB
1.389 -0.010 tHld 1 BSRAM_R28[11] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.274%; route: 0.625, 44.726%

Path8

Path Summary:

Slack 1.242
Data Arrival Time 2.631
Data Required Time 1.389
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.631 0.708 tNET RR 16 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.398 0.625 tNET RR 1 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s/CLKB
1.389 -0.010 tHld 1 BSRAM_R28[7] test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_0_s

Path Statistics:

Clock Skew 0.002
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.649%; route: 0.973, 78.848%; tC2Q: 0.130, 10.503%
Required Clock Path Delay cell: 0.773, 55.274%; route: 0.625, 44.726%

Path9

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_valid_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R29C37[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_valid_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R29C37[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_valid_s0/CLK
1.353 -0.048 tHld 1 R29C37[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_valid_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path10

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_12_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R29C21[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R29C21[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_12_s0/CLK
1.353 -0.048 tHld 1 R29C21[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_12_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path11

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_13_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R29C21[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R29C21[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_13_s0/CLK
1.353 -0.048 tHld 1 R29C21[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_13_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path12

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_18_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R29C21[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R29C21[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_18_s0/CLK
1.353 -0.048 tHld 1 R29C21[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_18_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path13

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_acc2_0_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R29C29[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_acc2_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R29C29[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_acc2_0_s0/CLK
1.353 -0.048 tHld 1 R29C29[0][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_acc2_0_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path14

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_12_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C33[2][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C33[2][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_12_s0/CLK
1.353 -0.048 tHld 1 R11C33[2][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_12_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path15

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_13_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C33[2][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C33[2][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_13_s0/CLK
1.353 -0.048 tHld 1 R11C33[2][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/in_coeff_reg_temp_13_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path16

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_18_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_18_s0/CLK
1.353 -0.048 tHld 1 R11C37[0][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_18_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path17

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_19_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[0][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[0][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_19_s0/CLK
1.353 -0.048 tHld 1 R11C37[0][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_19_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path18

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_20_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[1][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_20_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[1][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_20_s0/CLK
1.353 -0.048 tHld 1 R11C37[1][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_20_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path19

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_21_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_21_s0/CLK
1.353 -0.048 tHld 1 R11C37[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_21_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path20

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_22_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[2][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[2][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_22_s0/CLK
1.353 -0.048 tHld 1 R11C37[2][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_22_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path21

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_23_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C37[2][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_23_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C37[2][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_23_s0/CLK
1.353 -0.048 tHld 1 R11C37[2][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult2_out1_buf_23_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path22

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[0]_0_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C25[3][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[0]_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C25[3][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[0]_0_s0/CLK
1.353 -0.048 tHld 1 R11C25[3][A] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[0]_0_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path23

Path Summary:

Slack 1.269
Data Arrival Time 2.622
Data Required Time 1.353
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[1]_0_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.622 0.700 tNET RR 1 R11C25[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[1]_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.401 0.628 tNET RR 1 R11C25[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[1]_0_s0/CLK
1.353 -0.048 tHld 1 R11C25[1][B] test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/h0[1]_0_s0

Path Statistics:

Clock Skew 0.005
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.720%; route: 0.965, 78.708%; tC2Q: 0.130, 10.573%
Required Clock Path Delay cell: 0.773, 55.167%; route: 0.628, 44.833%

Path24

Path Summary:

Slack 1.273
Data Arrival Time 2.635
Data Required Time 1.362
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_14_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.635 0.713 tNET RR 1 R27C33[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.410 0.637 tNET RR 1 R27C33[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_14_s0/CLK
1.362 -0.048 tHld 1 R27C33[0][B] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_14_s0

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.610%; route: 0.977, 78.924%; tC2Q: 0.130, 10.465%
Required Clock Path Delay cell: 0.773, 54.815%; route: 0.637, 45.185%

Path25

Path Summary:

Slack 1.273
Data Arrival Time 2.635
Data Required Time 1.362
From test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0
To test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_17_s0
Launch Clk sym_clk:[R]
Latch Clk sym_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.397 0.624 tNET RR 1 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/CLK
1.526 0.130 tC2Q RR 3 R32C38[0][A] test_top_inst/asrc/ASRC_Top_inst/ratio_dect/buff_rst_s0/Q
1.791 0.265 tNET RR 1 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/I1
1.922 0.131 tINS RR 902 R23C34[1][A] test_top_inst/asrc/ASRC_Top_inst/input_storage0/n135_s1/F
2.635 0.713 tNET RR 1 R27C33[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sym_clk
0.000 0.000 tCL RR 1 IOB29[A] SYM_CLK_ibuf/I
0.773 0.773 tINS RR 1729 IOB29[A] SYM_CLK_ibuf/O
1.410 0.637 tNET RR 1 R27C33[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_17_s0/CLK
1.362 -0.048 tHld 1 R27C33[1][A] test_top_inst/asrc/ASRC_Top_inst/fir_filter/out_data0_17_s0

Path Statistics:

Clock Skew 0.014
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.773, 55.345%; route: 0.624, 44.655%
Arrival Data Path Delay cell: 0.131, 10.610%; route: 0.977, 78.924%; tC2Q: 0.130, 10.465%
Required Clock Path Delay cell: 0.773, 54.815%; route: 0.637, 45.185%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 2.706
Actual Width: 3.606
Required Width: 0.900
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.405 2.405 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.011 1.011 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW2

MPW Summary:

Slack: 2.711
Actual Width: 3.611
Required Width: 0.900
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.397 2.397 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.007 1.007 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW3

MPW Summary:

Slack: 2.711
Actual Width: 3.611
Required Width: 0.900
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.397 2.397 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.007 1.007 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW4

MPW Summary:

Slack: 2.715
Actual Width: 3.615
Required Width: 0.900
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.388 2.388 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.003 1.003 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW5

MPW Summary:

Slack: 2.730
Actual Width: 3.630
Required Width: 0.900
Type: High Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
2.475 2.475 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
6.105 1.105 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW6

MPW Summary:

Slack: 2.735
Actual Width: 3.635
Required Width: 0.900
Type: High Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
2.466 2.466 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
6.101 1.101 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack: 2.735
Actual Width: 3.635
Required Width: 0.900
Type: High Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
2.466 2.466 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
6.101 1.101 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW8

MPW Summary:

Slack: 2.740
Actual Width: 3.640
Required Width: 0.900
Type: High Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 in_clkout
0.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
2.458 2.458 tNET RR gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
6.098 1.098 tNET FF gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW9

MPW Summary:

Slack: 3.372
Actual Width: 3.597
Required Width: 0.225
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.432 2.432 tNET FF gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.029 1.029 tNET RR gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK

MPW10

MPW Summary:

Slack: 3.372
Actual Width: 3.597
Required Width: 0.225
Type: Low Pulse Width
Clock: in_clkout
Objects: gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 in_clkout
5.000 0.000 tCL FF test_top_inst/clk_out_s1/Q
7.432 2.432 tNET FF gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 in_clkout
10.000 0.000 tCL RR test_top_inst/clk_out_s1/Q
11.029 1.029 tNET RR gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1729 SYM_CLK_d 9.569 1.786
902 test_top_inst/asrc/ASRC_Top_inst/n135_5 16.357 1.985
298 gw_gao_inst_0/control0[0] 44.122 2.655
271 test_top_inst/asrc/ASRC_Top_inst/fir_init_Z 13.738 2.480
184 test_top_inst_60_2 4.963 2.812
150 test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n3399_4 9.569 2.107
105 test_top_inst/asrc/ASRC_Top_inst/shared_divider/div/n768_4 15.111 2.856
105 test_top_inst/asrc/ASRC_Top_inst/ratio_dect/err_sign_d 14.873 2.131
105 test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n3402_5 11.590 1.675
102 test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/n3397_4 10.265 2.793

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R19C26 62.50%
R27C23 62.50%
R11C27 61.11%
R24C33 59.72%
R28C32 58.33%
R27C24 58.33%
R19C25 58.33%
R28C35 56.94%
R28C33 56.94%
R26C35 56.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK Actived create_clock -name sym_clk -period 20 -waveform {0 10} [get_ports {SYM_CLK}]
TC_CLOCK Actived create_clock -name in_clkout -period 10 -waveform {0 5} [get_nets {test_top_inst_60_2}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {tck_pad_i}] -group [get_clocks {in_clkout}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {sym_clk}] -group [get_clocks {in_clkout}]