Power Messages

Report Title	Power Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\impl\gwsynthesis\ASRC.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\asrc.cst
Timing Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\asrc.sdc
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Fri Jun 12 16:43:36 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	108.540
Quiescent Power (mW)	53.529
Dynamic Power (mW)	55.011

Thermal Information:

Junction Temperature	27.974
Theta JA	27.400
Max Allowed Ambient Temperature	82.026

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	54.898	30.019	76.425
VCCX	3.300	0.849	3.000	12.702
VCCIO33	3.300	0.849	1.034	6.213
VCCLDO	3.300	0.000	4.000	13.200

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	1.790	NA	6.144
IO	17.203	10.839	7.844
BSRAM	35.601	NA	NA
DSP	11.256	NA	1.229

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	48.648	48.648(48.648)
top/gw_gao_inst_0/	13.020	13.020(13.020)
top/gw_gao_inst_0/u_icon_top/	0.001	0.001(0.000)
top/gw_gao_inst_0/u_la0_top/	13.019	13.019(12.964)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/	0.004	0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/	0.001	0.001(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/	12.960	12.960(0.000)
top/test_top_inst/	35.628	35.628(35.614)
top/test_top_inst/Data_pROM/	0.484	0.484(0.000)
top/test_top_inst/asrc/	35.130	35.130(35.130)
top/test_top_inst/asrc/ASRC_Top_inst/	35.130	35.130(35.130)
top/test_top_inst/asrc/ASRC_Top_inst/fir_filter/	2.625	2.625(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/input_storage0/	21.612	21.612(21.514)
top/test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/	21.514	21.514(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/	10.310	10.310(9.700)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/coeff_rom_inst/	0.695	0.695(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_0/	2.252	2.252(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_1/	2.251	2.251(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_2/	2.251	2.251(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/phase_interpolator/mult_3/	2.251	2.251(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/ratio_dect/	0.368	0.368(0.093)
top/test_top_inst/asrc/ASRC_Top_inst/ratio_dect/ave_filter/	0.093	0.093(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/shared_divider/	0.215	0.215(0.166)
top/test_top_inst/asrc/ASRC_Top_inst/shared_divider/div/	0.166	0.166(0.078)
top/test_top_inst/asrc/ASRC_Top_inst/shared_divider/div/non_restoring_division_inst/	0.039	0.039(0.000)
top/test_top_inst/asrc/ASRC_Top_inst/shared_divider/div/non_restoring_division_inst2/	0.039	0.039(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
sym_clk	50.000	35.626
tck_pad_i	20.000	2.190
in_clkout	100.000	10.831