Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\asrc\asrc.v E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\data_prom\data_prom.v E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\test_top.v E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\src\top.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.12.03_x64_internal\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.12.03\Gowin_ASRC_refDesign\RefDesign\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.03 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Fri Jun 12 16:43:21 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 783.703MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 783.703MB Optimizing Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 783.703MB Optimizing Phase 2: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.517s, Peak memory usage = 783.703MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.245s, Peak memory usage = 783.703MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 783.703MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 783.703MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 783.703MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.272s, Peak memory usage = 783.703MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 783.703MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 783.703MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 783.703MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.234s, Peak memory usage = 783.703MB Generate output files: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.416s, Peak memory usage = 783.703MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 783.703MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 40 |
| I/O Buf | 40 |
| IBUF | 5 |
| OBUF | 35 |
| Register | 2175 |
| DFFRE | 71 |
| DFFPE | 70 |
| DFFCE | 2034 |
| LUT | 2793 |
| LUT2 | 523 |
| LUT3 | 640 |
| LUT4 | 1630 |
| ALU | 839 |
| ALU | 839 |
| INV | 33 |
| INV | 33 |
| DSP | |
| MULT27X36 | 5 |
| BSRAM | 17 |
| SDPB | 12 |
| pROM | 5 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3665(2826 LUT, 839 ALU) / 23040 | 16% |
| Register | 2175 / 23685 | 10% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 2175 / 23685 | 10% |
| BSRAM | 17 / 56 | 31% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | SYM_CLK | Base | 10.000 | 100.000 | 0.000 | 5.000 | SYM_CLK_ibuf/I | ||
| 2 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
| 3 | test_top_inst/test_top_inst_60_2 | Base | 10.000 | 100.000 | 0.000 | 5.000 | test_top_inst/clk_out_s1/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | SYM_CLK | 100.000(MHz) | 115.669(MHz) | 5 | TOP |
| 2 | tck_pad_i | 20.000(MHz) | 193.742(MHz) | 3 | TOP |
| 3 | test_top_inst/test_top_inst_60_2 | 100.000(MHz) | 238.756(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.355 |
| Data Arrival Time | 5.719 |
| Data Required Time | 7.074 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[2] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s11/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s11/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s13/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s13/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s7/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s7/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s5/I1 |
| 5.382 | 0.465 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_18_s5/F |
| 5.719 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[18] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.074 | -3.263 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.886, 35.033%; route: 1.687, 31.355%; tC2Q: 1.809, 33.612% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 2
Path Summary:| Slack | 1.707 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.198 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[5] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_21_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[21] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.198 | -3.139 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 3
Path Summary:| Slack | 1.758 |
| Data Arrival Time | 5.719 |
| Data Required Time | 7.477 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[10] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s11/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s11/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s13/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s13/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s7/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s7/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s5/I1 |
| 5.382 | 0.465 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_26_s5/F |
| 5.719 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[26] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.477 | -2.860 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.886, 35.033%; route: 1.687, 31.355%; tC2Q: 1.809, 33.612% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 4
Path Summary:| Slack | 1.786 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.277 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[7] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_23_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[23] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.277 | -3.060 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 5
Path Summary:| Slack | 1.903 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.394 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[9] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_25_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[25] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.394 | -2.943 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 6
Path Summary:| Slack | 1.980 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.472 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[9] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_9_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[9] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.472 | -2.866 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 7
Path Summary:| Slack | 2.008 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.499 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[10] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_10_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[10] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.499 | -2.838 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 8
Path Summary:| Slack | 2.056 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.547 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[14] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_30_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[30] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.547 | -2.790 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 9
Path Summary:| Slack | 2.068 |
| Data Arrival Time | 5.491 |
| Data Required Time | 7.560 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[13] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s8/I0 |
| 4.580 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s8/F |
| 4.917 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s5/I3 |
| 5.154 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_13_s5/F |
| 5.491 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[13] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.560 | -2.778 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.657, 32.155%; route: 1.687, 32.744%; tC2Q: 1.809, 35.101% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 10
Path Summary:| Slack | 2.077 |
| Data Arrival Time | 5.482 |
| Data Required Time | 7.560 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[15] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/I1 |
| 4.571 | 0.465 | tINS | RR | 4 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/F |
| 4.908 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_31_s5/I3 |
| 5.145 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_31_s5/F |
| 5.482 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[31] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.560 | -2.778 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.648, 32.036%; route: 1.687, 32.801%; tC2Q: 1.809, 35.163% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 11
Path Summary:| Slack | 2.103 |
| Data Arrival Time | 5.482 |
| Data Required Time | 7.585 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[15] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/I1 |
| 4.571 | 0.465 | tINS | RR | 4 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/F |
| 4.908 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_32_s5/I3 |
| 5.145 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_32_s5/F |
| 5.482 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[32] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.585 | -2.753 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.648, 32.036%; route: 1.687, 32.801%; tC2Q: 1.809, 35.163% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 12
Path Summary:| Slack | 2.140 |
| Data Arrival Time | 5.482 |
| Data Required Time | 7.623 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[15] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/I1 |
| 4.571 | 0.465 | tINS | RR | 4 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/F |
| 4.908 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s5/I3 |
| 5.145 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s5/F |
| 5.482 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[33] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.623 | -2.715 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.648, 32.036%; route: 1.687, 32.801%; tC2Q: 1.809, 35.163% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 13
Path Summary:| Slack | 2.260 |
| Data Arrival Time | 5.482 |
| Data Required Time | 7.742 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[15] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/I1 |
| 4.571 | 0.465 | tINS | RR | 4 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/F |
| 4.908 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_34_s5/I3 |
| 5.145 | 0.236 | tINS | RR | 2 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_34_s5/F |
| 5.482 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[35] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.742 | -2.595 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.648, 32.036%; route: 1.687, 32.801%; tC2Q: 1.809, 35.163% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 14
Path Summary:| Slack | 2.265 |
| Data Arrival Time | 5.482 |
| Data Required Time | 7.747 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[15] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s13/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s12/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/I1 |
| 4.571 | 0.465 | tINS | RR | 4 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_33_s8/F |
| 4.908 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_34_s5/I3 |
| 5.145 | 0.236 | tINS | RR | 2 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_34_s5/F |
| 5.482 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[34] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.747 | -2.591 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.648, 32.036%; route: 1.687, 32.801%; tC2Q: 1.809, 35.163% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 15
Path Summary:| Slack | 2.324 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.004 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[3] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s7/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s7/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_19_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[19] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.004 | -3.333 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 16
Path Summary:| Slack | 2.324 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.004 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[1] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s9/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s9/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s8/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s8/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_1_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[1] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.004 | -3.333 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 17
Path Summary:| Slack | 2.334 |
| Data Arrival Time | 4.859 |
| Data Required Time | 7.193 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[4] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s8/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s8/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s6/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s6/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s5/I2 |
| 4.521 | 0.415 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_20_s5/F |
| 4.859 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[20] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.193 | -3.145 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.362, 30.132%; route: 1.350, 29.858%; tC2Q: 1.809, 40.010% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 18
Path Summary:| Slack | 2.403 |
| Data Arrival Time | 4.671 |
| Data Required Time | 7.074 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/DO[0] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s8/I1 |
| 3.760 | 0.465 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s8/F |
| 4.097 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s5/I3 |
| 4.333 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_0_s5/F |
| 4.671 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[0] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.074 | -3.263 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.174, 27.103%; route: 1.350, 31.153%; tC2Q: 1.809, 41.744% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 19
Path Summary:| Slack | 2.513 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.193 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[2] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s9/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s9/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s8/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s8/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_2_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[2] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.193 | -3.145 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 20
Path Summary:| Slack | 2.518 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.198 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[3] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s9/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s9/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s8/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s8/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_3_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[3] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.198 | -3.139 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 21
Path Summary:| Slack | 2.606 |
| Data Arrival Time | 4.671 |
| Data Required Time | 7.277 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_6_s/DO[5] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s8/I1 |
| 3.760 | 0.465 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s8/F |
| 4.097 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s5/I3 |
| 4.333 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_5_s5/F |
| 4.671 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[5] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.277 | -3.060 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.174, 27.103%; route: 1.350, 31.153%; tC2Q: 1.809, 41.744% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 22
Path Summary:| Slack | 2.629 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.309 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_3_s/DO[6] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s10/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s10/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s7/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s7/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_22_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[22] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.309 | -3.028 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 23
Path Summary:| Slack | 2.629 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.309 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[4] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s9/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s9/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s8/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s8/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_4_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[4] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.309 | -3.028 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 24
Path Summary:| Slack | 2.641 |
| Data Arrival Time | 4.859 |
| Data Required Time | 7.499 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_7_s/DO[12] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s8/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s8/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s6/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s6/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s5/I2 |
| 4.521 | 0.415 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_28_s5/F |
| 4.859 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[28] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.499 | -2.838 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.362, 30.132%; route: 1.350, 29.858%; tC2Q: 1.809, 40.010% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
Path 25
Path Summary:| Slack | 2.714 |
| Data Arrival Time | 4.680 |
| Data Required Time | 7.394 |
| From | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s |
| To | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 0.337 | 0.337 | tNET | RR | 16 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/CLKB |
| 2.146 | 1.809 | tC2Q | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/input_storage0/fifo/input_mem_input_mem_0_2_s/DO[7] |
| 2.484 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s9/I0 |
| 2.958 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s9/F |
| 3.295 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s8/I0 |
| 3.769 | 0.474 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s8/F |
| 4.106 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s5/I3 |
| 4.342 | 0.236 | tINS | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/mult_b_7_s5/F |
| 4.680 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/B[7] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1729 | SYM_CLK_ibuf/O |
| 10.337 | 0.337 | tNET | RR | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s/CLK[0] |
| 7.394 | -2.943 | tSu | 1 | test_top_inst/asrc/ASRC_Top_inst/fir_filter/n529_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |
| Arrival Data Path Delay: | cell: 1.184, 27.254%; route: 1.350, 31.088%; tC2Q: 1.809, 41.658% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.337, 100.000% |