PnR Messages

Report Title PnR Report
Design File E:\work_files\IP_A_new\GoConfig\00_2024\JTAG_JTAG\ref_release\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2024\JTAG_JTAG\ref_release\fpga_project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.9.03 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Mon May 6 14:59:52 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.026s, Elapsed time = 0h 0m 0.026s Placement Phase 1: CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.033s Placement Phase 2: CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.032s Placement Phase 3: CPU time = 0h 0m 0.402s, Elapsed time = 0h 0m 0.402s Total Placement: CPU time = 0h 0m 0.494s, Elapsed time = 0h 0m 0.493s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.047s, Elapsed time = 0h 0m 0.047s Routing Phase 2: CPU time = 0h 0m 0.133s, Elapsed time = 0h 0m 0.133s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.18s, Elapsed time = 0h 0m 0.18s Generate output files: CPU time = 0h 0m 0.332s, Elapsed time = 0h 0m 0.331s
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 266MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 285/2304 13%
    --LUT,ALU,ROM16 285(231 LUT, 54 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 282/2643 11%
    --Logic Register as Latch 0/2304 0%
    --Logic Register as FF 279/2016 14%
    --I/O Register as Latch 0/339 0%
    --I/O Register as FF 3/339 <1%
CLS 238/1152 21%
I/O Port 8 -
I/O Buf 8 -
    --Input Buf 5 -
    --Output Buf 3 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 1 SDPB
 25%
PLL 0/1 0%
DCS 0/4 0%
DQCE 0/12 0%
OSC 1/1 100%
User Flash 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DHCEN 0/8 0%
DHCENC 0/4 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 5/28(17%)
bank 1 1/28(3%)
bank 2 1/29(3%)
bank 3 0/8(0%)
bank 4 1/10(10%)
bank 5 0/10(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 1/8(13%)
LW 1/8(13%)
GCLK_PIN 0/8(0%)
PLL 0/1(0%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
GW_OSC_CLK_d PRIMARY LEFT RIGHT
inst_JTAG_HUB/inst_goConfig_JTAG/u_test1/u_fifo2bx8192d/n22_5 LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
tck_mcu 131/0 Y in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
tdi_mcu 136/0 Y in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
tms_mcu 130/0 Y in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
GW_BACKGROUND_EXT_SEL 83/1 Y in IOR15[B] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
rstn 23/4 N in IOL14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
tdo_mcu 137/0 Y out IOT7[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
GW_OSC_CLK 113/0 N out IOT17[B] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
Test_LED 39/2 Y out IOB2[B] LVCMOS18 8 DOWN NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
143/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
142/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
141/0 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
140/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
139/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
138/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
137/0 tdo_mcu out IOT7[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
136/0 tdi_mcu in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
133/0 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
132/0 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
131/0 tck_mcu in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
130/0 tms_mcu in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
128/0 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
127/0 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
129/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
122/0 - in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
121/0 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
126/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
125/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
117/0 - in IOT15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
115/0 - in IOT15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
120/0 - in IOT16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
119/0 - in IOT16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
114/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
113/0 GW_OSC_CLK out IOT17[B] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
110/0 - in IOT18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
109/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
112/0 - in IOT19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
111/0 - in IOT19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/2 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/2 Test_LED out IOB2[B] LVCMOS18 8 DOWN NA NA OFF NA NA NA 1.8
40/2 - in IOB3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/2 - in IOB3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/2 - in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/2 - in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/2 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/2 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/2 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/2 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/2 - in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/2 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
55/2 - in IOB9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/2 - in IOB9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/2 - in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
58/2 - in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/2 - in IOB12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/2 - in IOB12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/2 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/2 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/2 - in IOB14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
65/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
67/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
68/2 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/2 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/2 - in IOB18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/2 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/5 - in IOL4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/5 - in IOL4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/5 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/5 - in IOL5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
5/5 - in IOL6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/5 - in IOL6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/5 - in IOL7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/5 - in IOL7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/5 - in IOL8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
12/5 - in IOL8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/4 - in IOL9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/4 - in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/4 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/4 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/4 - in IOL12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/4 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/4 - in IOL13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/4 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/4 rstn in IOL14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/4 - in IOL14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/3 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/3 - in IOL16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/3 - in IOL16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/3 - in IOL17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/3 - in IOL17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/3 - in IOL18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/3 - in IOL18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
107/1 - in IOR1[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
106/1 - in IOR1[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
105/1 - in IOR2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
104/1 - in IOR2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
100/1 - in IOR3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
99/1 - in IOR3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
98/1 - in IOR4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
97/1 - in IOR4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
96/1 - in IOR5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
95/1 - in IOR5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
94/1 - in IOR6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
93/1 - in IOR6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
92/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
91/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
89/1 - in IOR13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/1 - in IOR13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/1 - in IOR14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/1 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/1 GW_BACKGROUND_EXT_SEL in IOR15[B] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
82/1 - in IOR16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/1 - in IOR16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
78/1 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
76/1 - in IOR18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
75/1 - in IOR18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
74/1 - in IOR19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
73/1 - in IOR19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8