Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FlashController\data\gowin_flash_controller.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\FlashController\data\gowin_flash_controller_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Fri Aug 8 15:08:50 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Gowin_Flash_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.179s, Peak memory usage = 63.375MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 63.375MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 63.375MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 63.375MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 63.375MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 63.375MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 63.375MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 63.375MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 63.375MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 63.375MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 63.375MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 63.375MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.070MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 93.070MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 93.070MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 93.070MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 83
I/O Buf 83
    IBUF 50
    OBUF 33
Register 346
    DFFC 267
    DFFCE 79
LUT 477
    LUT2 144
    LUT3 72
    LUT4 261
INV 1
    INV 1
User Flash 1
    FLASH96KA 1

Resource Utilization Summary

Resource Usage Utilization
Logic 478(478 LUT, 0 ALU) / 2304 21%
Register 346 / 2646 14%
  --Register as Latch 0 / 2646 0%
  --Register as FF 346 / 2358 15%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_i Base 20.000 50.000 0.000 10.000 clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 50.000(MHz) 135.124(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0
To u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 346 clk_i_ibuf/O
0.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/CLK
0.878 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_5_s0/Q
1.589 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s9/I1
2.403 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s9/F
3.115 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s7/I1
3.929 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s7/F
4.640 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s11/I0
5.405 0.765 tINS FF 10 u_Flash_Ctroller_96KA/u_WR_UFM/n231_s11/F
6.116 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n263_s3/I1
6.931 0.814 tINS FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/n263_s3/F
7.642 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.000 0.000 tINS RR 346 clk_i_ibuf/O
20.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0/CLK
20.242 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.755
Data Arrival Time 7.487
Data Required Time 20.242
From u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_6_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 346 clk_i_ibuf/O
0.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.878 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q
1.589 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/I1
2.403 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/F
3.115 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/I1
3.929 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/F
4.640 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/I1
5.455 0.814 tINS FF 16 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/F
6.166 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n241_s3/I2
6.775 0.609 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n241_s3/F
7.487 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.000 0.000 tINS RR 346 clk_i_ibuf/O
20.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_6_s0/CLK
20.242 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.755
Data Arrival Time 7.487
Data Required Time 20.242
From u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_10_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 346 clk_i_ibuf/O
0.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.878 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q
1.589 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/I1
2.403 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/F
3.115 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/I1
3.929 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/F
4.640 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/I1
5.455 0.814 tINS FF 16 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/F
6.166 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n237_s3/I2
6.775 0.609 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n237_s3/F
7.487 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.000 0.000 tINS RR 346 clk_i_ibuf/O
20.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_10_s0/CLK
20.242 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.755
Data Arrival Time 7.487
Data Required Time 20.242
From u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 346 clk_i_ibuf/O
0.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.878 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q
1.589 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/I1
2.403 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/F
3.115 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/I1
3.929 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/F
4.640 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/I1
5.455 0.814 tINS FF 16 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/F
6.166 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n234_s3/I2
6.775 0.609 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n234_s3/F
7.487 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.000 0.000 tINS RR 346 clk_i_ibuf/O
20.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/CLK
20.242 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.755
Data Arrival Time 7.487
Data Required Time 20.242
From u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
To u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.000 0.000 tINS RR 346 clk_i_ibuf/O
0.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.878 0.340 tC2Q RF 4 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q
1.589 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/I1
2.403 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s31/F
3.115 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/I1
3.929 0.814 tINS FF 2 u_Flash_Ctroller_96KA/u_ER_UFM/n279_s26/F
4.640 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/I1
5.455 0.814 tINS FF 16 u_Flash_Ctroller_96KA/u_ER_UFM/n247_s4/F
6.166 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n233_s3/I2
6.775 0.609 tINS FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/n233_s3/F
7.487 0.711 tNET FF 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_i
20.000 0.000 tCL RR 1 clk_i_ibuf/I
20.000 0.000 tINS RR 346 clk_i_ibuf/O
20.538 0.538 tNET RR 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/CLK
20.242 -0.296 tSu 1 u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.052, 43.925%; route: 3.557, 51.187%; tC2Q: 0.340, 4.888%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%