Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\goConfig_SPI\data\goConfig_SPI_wrap.v
D:\Gowin\Gowin_V1.9.12_x64\IDE\ipcore\goConfig_SPI\data\goConfig_SPI.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Fri Aug 8 15:07:55 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module goConfig_SPI_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.178s, Peak memory usage = 61.785MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 61.785MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 61.785MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 61.785MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 61.785MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 61.785MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 61.785MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 61.785MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 61.785MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 61.785MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 61.785MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 61.785MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.954s, Peak memory usage = 91.008MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 91.008MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.212s, Peak memory usage = 91.008MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 91.008MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 25
I/O Buf 25
    IBUF 14
    OBUF 11
Register 200
    DFF 4
    DFFE 4
    DFFP 2
    DFFPE 9
    DFFC 65
    DFFCE 116
LUT 340
    LUT2 57
    LUT3 85
    LUT4 198
ALU 48
    ALU 48
INV 4
    INV 4
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 392(344 LUT, 48 ALU) / 2304 18%
Register 200 / 2646 8%
  --Register as Latch 0 / 2646 0%
  --Register as FF 200 / 2358 9%
BSRAM 1 / 4 25%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 GW_OSC_CLK Base 20.000 50.000 0.000 10.000 GW_OSC_CLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 GW_OSC_CLK 50.000(MHz) 103.935(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.379
Data Arrival Time 9.863
Data Required Time 20.242
From inst_GW_SPI/U_spi_slave/rden_s0
To inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
0.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.878 0.340 tC2Q RF 1 inst_GW_SPI/U_spi_slave/rden_s0/Q
1.589 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.403 0.814 tINS FF 6 inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.115 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
3.929 0.814 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.640 0.711 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.415 0.774 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.415 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.457 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.457 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
5.499 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
5.499 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
5.541 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
5.541 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
5.584 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
5.584 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
5.626 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
5.626 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
5.668 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
5.668 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
6.085 0.417 tINS FF 3 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/SUM
6.797 0.711 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/I0
7.507 0.710 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
7.507 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
7.549 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
7.549 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
7.591 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
7.591 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
7.633 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
7.633 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
7.676 0.042 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.387 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/I0
9.152 0.765 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/F
9.863 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 GW_OSC_CLK
20.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
20.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
20.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
20.242 -0.296 tSu 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.717, 50.587%; route: 4.268, 45.771%; tC2Q: 0.340, 3.642%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 10.880
Data Arrival Time 9.519
Data Required Time 20.399
From inst_GW_SPI/U_spi_slave/rden_s0
To inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
0.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.878 0.340 tC2Q RF 1 inst_GW_SPI/U_spi_slave/rden_s0/Q
1.589 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.403 0.814 tINS FF 6 inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.115 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
3.929 0.814 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
4.640 0.711 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.415 0.774 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.415 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.457 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.457 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
5.499 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
5.499 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
5.916 0.417 tINS FF 3 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/SUM
6.628 0.711 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/I0
7.338 0.710 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/COUT
7.338 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/CIN
7.380 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/COUT
7.380 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/CIN
7.422 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/COUT
7.422 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/CIN
7.464 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/COUT
7.464 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/CIN
7.507 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
7.507 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
7.549 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
7.549 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
7.591 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
7.591 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
7.633 0.042 tINS FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
7.633 0.000 tNET FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
7.676 0.042 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.387 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/I2
8.981 0.594 tINS FR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/F
9.519 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 GW_OSC_CLK
20.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
20.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
20.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
20.399 -0.139 tSu 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 4.547, 50.625%; route: 4.095, 45.593%; tC2Q: 0.340, 3.782%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 11.424
Data Arrival Time 8.817
Data Required Time 20.242
From inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To inst_GW_SPI/U_spi_slave/spi_data_0_s3
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
0.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n139_s0/I0
5.405 0.765 tINS FF 2 inst_GW_SPI/U_spi_slave/n139_s0/F
6.116 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
6.931 0.814 tINS FF 8 inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
7.642 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n100_s6/I3
8.106 0.464 tINS FF 1 inst_GW_SPI/U_spi_slave/n100_s6/F
8.817 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 GW_OSC_CLK
20.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
20.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
20.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_slave/spi_data_0_s3/CLK
20.242 -0.296 tSu 1 inst_GW_SPI/U_spi_slave/spi_data_0_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 11.424
Data Arrival Time 8.817
Data Required Time 20.242
From inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To inst_GW_SPI/U_spi_slave/spi_data_1_s3
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
0.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n139_s0/I0
5.405 0.765 tINS FF 2 inst_GW_SPI/U_spi_slave/n139_s0/F
6.116 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
6.931 0.814 tINS FF 8 inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
7.642 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n99_s6/I3
8.106 0.464 tINS FF 1 inst_GW_SPI/U_spi_slave/n99_s6/F
8.817 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 GW_OSC_CLK
20.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
20.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
20.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_slave/spi_data_1_s3/CLK
20.242 -0.296 tSu 1 inst_GW_SPI/U_spi_slave/spi_data_1_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 11.424
Data Arrival Time 8.817
Data Required Time 20.242
From inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To inst_GW_SPI/U_spi_slave/spi_data_2_s3
Launch Clk GW_OSC_CLK[R]
Latch Clk GW_OSC_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 GW_OSC_CLK
0.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
0.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
0.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.878 0.340 tC2Q RF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
1.589 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.403 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.115 0.711 tNET FF 1 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
3.929 0.814 tINS FF 2 inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
4.640 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n139_s0/I0
5.405 0.765 tINS FF 2 inst_GW_SPI/U_spi_slave/n139_s0/F
6.116 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
6.931 0.814 tINS FF 8 inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
7.642 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/n98_s6/I3
8.106 0.464 tINS FF 1 inst_GW_SPI/U_spi_slave/n98_s6/F
8.817 0.711 tNET FF 1 inst_GW_SPI/U_spi_slave/spi_data_2_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 GW_OSC_CLK
20.000 0.000 tCL RR 1 GW_OSC_CLK_ibuf/I
20.000 0.000 tINS RR 202 GW_OSC_CLK_ibuf/O
20.538 0.538 tNET RR 1 inst_GW_SPI/U_spi_slave/spi_data_2_s3/CLK
20.242 -0.296 tSu 1 inst_GW_SPI/U_spi_slave/spi_data_2_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%