Timing Messages

Report Title	Timing Analysis Report
Design File	E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\ref_design\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\ref_design\project\src\fpga_project.cst
Timing Constraint File	---
Tool Version	V1.9.12 (64-bit)
Part Number	GW1N-LV2LQ144XC7/I6
Device	GW1N-2
Device Version	C
Created Time	Mon Aug 11 08:47:28 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C7/I6
Hold Delay Model	Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed	3064
Numbers of Endpoints Analyzed	1773
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	Generated	40.000	25.000	0.000	20.000		DEFAULT_CLK	inst_clk_25M/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	25.000(MHz)	98.097(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	Setup	0.000	0
inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	29.806	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.898
2	29.848	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.855
3	29.891	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.813
4	29.933	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.771
5	29.975	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.729
6	30.017	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.686
7	30.059	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.644
8	30.102	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.602
9	30.144	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.560
10	30.186	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.517
11	30.228	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.475
12	30.271	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	9.433
13	31.403	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	8.459
14	31.929	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	8.039
15	31.929	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	8.039
16	31.929	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	8.039
17	31.941	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	8.027
18	32.207	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.761
19	32.207	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.761
20	32.210	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.758
21	32.344	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_0_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.624
22	32.344	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_4_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.624
23	32.344	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_5_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.624
24	32.348	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_1_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.620
25	32.348	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_6_s0/CE	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	7.620

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
2	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
3	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
4	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
5	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
6	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
7	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
8	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
9	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
10	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
11	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
12	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
13	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
14	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
15	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
16	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
17	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
18	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
19	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
20	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
21	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
22	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
23	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
24	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524
25	0.524	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/Q	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/D	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	37.807	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
2	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
3	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
4	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
5	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
6	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
7	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
8	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
9	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
10	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
11	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
12	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
13	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
14	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
15	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
16	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
17	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
18	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
19	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
20	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
21	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
22	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
23	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
24	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041
25	37.927	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	40.000	2.041

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
2	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
3	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
4	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
5	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
6	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
7	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
8	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
9	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
10	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
11	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
12	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
13	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
14	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
15	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
16	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
17	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
18	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
19	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
20	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
21	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
22	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
23	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
24	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391
25	1.382	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]	1.391

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	led_cnt_30_s0
2	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	led_cnt_28_s0
3	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	led_cnt_24_s0
4	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	led_cnt_16_s0
5	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	led_cnt_0_s0
6	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/mosi_shift_reg_4_s1
7	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_0_s0
8	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	inst_bg_spi_usrflash/rd_data_reg_28_s0
9	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_15_s0
10	19.016	19.942	0.926	Low Pulse Width	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_16_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	29.806
Data Arrival Time	10.323
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
9.737	0.042	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
9.737	0.000	tNET	FF	2	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
9.779	0.042	tINS	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
9.779	0.000	tNET	FF	2	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
9.821	0.042	tINS	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
9.821	0.000	tNET	FF	2	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
9.863	0.042	tINS	FF	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
9.863	0.000	tNET	FF	2	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
9.906	0.042	tINS	FF	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/COUT
9.906	0.000	tNET	FF	2	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/CIN
10.323	0.417	tINS	FF	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n200_1_s/SUM
10.323	0.000	tNET	FF	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
40.129	-0.296	tSu		1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.070, 31.017%; route: 6.488, 65.551%; tC2Q: 0.340, 3.431%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path2

Path Summary:

Slack	29.848
Data Arrival Time	10.281
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
9.737	0.042	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
9.737	0.000	tNET	FF	2	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
9.779	0.042	tINS	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
9.779	0.000	tNET	FF	2	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
9.821	0.042	tINS	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
9.821	0.000	tNET	FF	2	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
9.863	0.042	tINS	FF	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/COUT
9.863	0.000	tNET	FF	2	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/CIN
10.281	0.417	tINS	FF	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n201_1_s/SUM
10.281	0.000	tNET	FF	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
40.129	-0.296	tSu		1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.028, 30.722%; route: 6.488, 65.832%; tC2Q: 0.340, 3.446%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack	29.891
Data Arrival Time	10.238
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
9.737	0.042	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
9.737	0.000	tNET	FF	2	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
9.779	0.042	tINS	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
9.779	0.000	tNET	FF	2	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
9.821	0.042	tINS	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/COUT
9.821	0.000	tNET	FF	2	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/CIN
10.238	0.417	tINS	FF	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n202_1_s/SUM
10.238	0.000	tNET	FF	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
40.129	-0.296	tSu		1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.985, 30.424%; route: 6.488, 66.115%; tC2Q: 0.340, 3.461%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	29.933
Data Arrival Time	10.196
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
9.737	0.042	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
9.737	0.000	tNET	FF	2	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
9.779	0.042	tINS	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/COUT
9.779	0.000	tNET	FF	2	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/CIN
10.196	0.417	tINS	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n203_1_s/SUM
10.196	0.000	tNET	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
40.129	-0.296	tSu		1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.943, 30.123%; route: 6.488, 66.401%; tC2Q: 0.340, 3.476%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path5

Path Summary:

Slack	29.975
Data Arrival Time	10.154
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
9.737	0.042	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/COUT
9.737	0.000	tNET	FF	2	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/CIN
10.154	0.417	tINS	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n204_1_s/SUM
10.154	0.000	tNET	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
40.129	-0.296	tSu		1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.901, 29.819%; route: 6.488, 66.689%; tC2Q: 0.340, 3.491%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path6

Path Summary:

Slack	30.017
Data Arrival Time	10.112
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
9.695	0.042	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/COUT
9.695	0.000	tNET	FF	2	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/CIN
10.112	0.417	tINS	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n205_1_s/SUM
10.112	0.000	tNET	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLK
40.129	-0.296	tSu		1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.859, 29.513%; route: 6.488, 66.980%; tC2Q: 0.340, 3.506%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack	30.059
Data Arrival Time	10.069
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
9.652	0.042	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/COUT
9.652	0.000	tNET	FF	2	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/CIN
10.069	0.417	tINS	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n206_1_s/SUM
10.069	0.000	tNET	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
40.129	-0.296	tSu		1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.817, 29.205%; route: 6.488, 67.274%; tC2Q: 0.340, 3.522%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack	30.102
Data Arrival Time	10.027
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.610	0.042	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/COUT
9.610	0.000	tNET	FF	2	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/CIN
10.027	0.417	tINS	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n207_1_s/SUM
10.027	0.000	tNET	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLK
40.129	-0.296	tSu		1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.774, 28.893%; route: 6.488, 67.570%; tC2Q: 0.340, 3.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path9

Path Summary:

Slack	30.144
Data Arrival Time	9.985
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.568	0.042	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/COUT
9.568	0.000	tNET	FF	2	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/CIN
9.985	0.417	tINS	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n208_1_s/SUM
9.985	0.000	tNET	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLK
40.129	-0.296	tSu		1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.732, 28.579%; route: 6.488, 67.868%; tC2Q: 0.340, 3.553%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	30.186
Data Arrival Time	9.943
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.526	0.042	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/COUT
9.526	0.000	tNET	FF	2	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/CIN
9.943	0.417	tINS	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n209_1_s/SUM
9.943	0.000	tNET	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLK
40.129	-0.296	tSu		1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.690, 28.262%; route: 6.488, 68.169%; tC2Q: 0.340, 3.568%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack	30.228
Data Arrival Time	9.901
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.483	0.042	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/COUT
9.483	0.000	tNET	FF	2	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/CIN
9.901	0.417	tINS	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n210_1_s/SUM
9.901	0.000	tNET	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
40.129	-0.296	tSu		1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.648, 27.942%; route: 6.488, 68.473%; tC2Q: 0.340, 3.584%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	30.271
Data Arrival Time	9.858
Data Required Time	40.129
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/CLK
0.765	0.340	tC2Q	RF	10	R7C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/in_sel_s0/Q
2.097	1.332	tNET	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/I2
2.911	0.814	tINS	FF	1	R4C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_wren_s0/F
3.507	0.596	tNET	FF	1	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/I3
4.117	0.609	tINS	FF	5	R3C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s1/F
5.331	1.215	tNET	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/I2
6.096	0.765	tINS	FF	1	R5C15[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n147_1_s1/F
9.441	3.345	tNET	FF	2	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/CIN
9.858	0.417	tINS	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n211_1_s/SUM
9.858	0.000	tNET	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLK
40.129	-0.296	tSu		1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.605, 27.620%; route: 6.488, 68.780%; tC2Q: 0.340, 3.600%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack	31.403
Data Arrival Time	8.884
Data Required Time	40.287
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C4[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/CLK
0.765	0.340	tC2Q	RF	1	R5C4[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/Q
1.608	0.843	tNET	FF	1	R5C14[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.072	0.464	tINS	FF	6	R5C14[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
2.689	0.617	tNET	FF	1	R6C15[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
3.152	0.463	tINS	FR	1	R6C15[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
3.462	0.310	tNET	RR	2	R6C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
3.870	0.408	tINS	RR	1	R6C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
3.870	0.000	tNET	RR	2	R6C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
3.912	0.042	tINS	RF	1	R6C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
3.912	0.000	tNET	FF	2	R6C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
3.954	0.042	tINS	FF	1	R6C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
3.954	0.000	tNET	FF	2	R6C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
3.997	0.042	tINS	FF	1	R6C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/COUT
3.997	0.000	tNET	FF	2	R6C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/CIN
4.039	0.042	tINS	FF	1	R6C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_4_s/COUT
4.039	0.000	tNET	FF	2	R6C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/CIN
4.081	0.042	tINS	FF	1	R6C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_5_s/COUT
4.081	0.000	tNET	FF	2	R6C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/CIN
4.123	0.042	tINS	FF	1	R6C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_6_s/COUT
4.123	0.000	tNET	FF	2	R6C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/CIN
4.166	0.042	tINS	FF	1	R6C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_7_s/COUT
4.166	0.000	tNET	FF	2	R6C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/CIN
4.208	0.042	tINS	FF	1	R6C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_8_s/COUT
4.208	0.000	tNET	FF	2	R6C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/CIN
4.250	0.042	tINS	FF	1	R6C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_9_s/COUT
4.250	0.000	tNET	FF	2	R6C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/CIN
4.292	0.042	tINS	FF	1	R6C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_10_s/COUT
4.292	0.000	tNET	FF	2	R6C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/CIN
4.709	0.417	tINS	FF	2	R6C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_11_s/SUM
5.559	0.850	tNET	FF	2	R5C17[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/I0
6.267	0.708	tINS	FR	2	R5C17[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
6.970	0.703	tNET	RR	1	R5C16[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/I2
7.757	0.786	tINS	RR	1	R5C16[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/F
8.884	1.128	tNET	RR	1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.287	-0.139	tSu		1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 3.669, 43.371%; route: 4.450, 52.614%; tC2Q: 0.340, 4.015%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack	31.929
Data Arrival Time	8.464
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_5_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.464	1.663	tNET	RR	1	R2C8[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C8[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_5_s1/CLK
40.393	-0.032	tSu		1	R2C8[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 31.128%; route: 5.197, 64.647%; tC2Q: 0.340, 4.225%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack	31.929
Data Arrival Time	8.464
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_6_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.464	1.663	tNET	RR	1	R2C8[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C8[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_6_s1/CLK
40.393	-0.032	tSu		1	R2C8[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 31.128%; route: 5.197, 64.647%; tC2Q: 0.340, 4.225%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path16

Path Summary:

Slack	31.929
Data Arrival Time	8.464
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_7_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.464	1.663	tNET	RR	1	R2C8[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C8[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_7_s1/CLK
40.393	-0.032	tSu		1	R2C8[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 31.128%; route: 5.197, 64.647%; tC2Q: 0.340, 4.225%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path17

Path Summary:

Slack	31.941
Data Arrival Time	8.452
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
7.109	0.848	tNET	FF	1	R2C9[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s2/I3
7.869	0.760	tINS	FR	1	R2C9[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s2/F
8.452	0.583	tNET	RR	1	R2C12[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C12[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s0/CLK
40.393	-0.032	tSu		1	R2C12[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/ERROR_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.389, 29.763%; route: 5.298, 66.006%; tC2Q: 0.340, 4.231%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path18

Path Summary:

Slack	32.207
Data Arrival Time	8.187
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_2_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.187	1.385	tNET	RR	1	R2C10[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C10[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_2_s1/CLK
40.393	-0.032	tSu		1	R2C10[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 32.242%; route: 4.919, 63.382%; tC2Q: 0.340, 4.376%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path19

Path Summary:

Slack	32.207
Data Arrival Time	8.187
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_3_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.187	1.385	tNET	RR	1	R2C10[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C10[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_3_s1/CLK
40.393	-0.032	tSu		1	R2C10[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 32.242%; route: 4.919, 63.382%; tC2Q: 0.340, 4.376%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack	32.210
Data Arrival Time	8.183
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_4_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/CLK
0.765	0.340	tC2Q	RF	7	R5C11[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_8_s0/Q
2.108	1.343	tNET	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/I0
2.572	0.464	tINS	FF	1	R4C13[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s4/F
3.180	0.608	tNET	FF	1	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/I3
3.644	0.464	tINS	FF	4	R4C11[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n491_s1/F
4.860	1.215	tNET	FF	1	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/I0
5.674	0.814	tINS	FF	2	R7C12[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s7/F
6.041	0.367	tNET	FF	1	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/I1
6.801	0.760	tINS	FR	16	R5C12[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n834_s0/F
8.183	1.382	tNET	RR	1	R3C8[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R3C8[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_4_s1/CLK
40.393	-0.032	tSu		1	R3C8[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/send_counter_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.502, 32.256%; route: 4.916, 63.366%; tC2Q: 0.340, 4.378%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path21

Path Summary:

Slack	32.344
Data Arrival Time	8.049
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
6.864	0.603	tNET	FF	1	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/I2
7.458	0.594	tINS	FR	8	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/F
8.049	0.591	tNET	RR	1	R5C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R5C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_0_s0/CLK
40.393	-0.032	tSu		1	R5C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.223, 29.159%; route: 5.061, 66.386%; tC2Q: 0.340, 4.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack	32.344
Data Arrival Time	8.049
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_4_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
6.864	0.603	tNET	FF	1	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/I2
7.458	0.594	tINS	FR	8	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/F
8.049	0.591	tNET	RR	1	R5C9[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R5C9[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_4_s0/CLK
40.393	-0.032	tSu		1	R5C9[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.223, 29.159%; route: 5.061, 66.386%; tC2Q: 0.340, 4.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack	32.344
Data Arrival Time	8.049
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_5_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
6.864	0.603	tNET	FF	1	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/I2
7.458	0.594	tINS	FR	8	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/F
8.049	0.591	tNET	RR	1	R5C9[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R5C9[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_5_s0/CLK
40.393	-0.032	tSu		1	R5C9[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.223, 29.159%; route: 5.061, 66.386%; tC2Q: 0.340, 4.455%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path24

Path Summary:

Slack	32.348
Data Arrival Time	8.046
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
6.864	0.603	tNET	FF	1	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/I2
7.458	0.594	tINS	FR	8	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/F
8.046	0.588	tNET	RR	1	R4C9[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C9[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_1_s0/CLK
40.393	-0.032	tSu		1	R4C9[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.223, 29.172%; route: 5.058, 66.371%; tC2Q: 0.340, 4.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	32.348
Data Arrival Time	8.046
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/CLK
0.765	0.340	tC2Q	RF	9	R3C5[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_4_s3/Q
4.383	3.618	tNET	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/I1
5.197	0.814	tINS	FF	1	R2C12[3][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s4/F
5.447	0.249	tNET	FF	1	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/I1
6.261	0.814	tINS	FF	3	R2C12[3][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s1/F
6.864	0.603	tNET	FF	1	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/I2
7.458	0.594	tINS	FR	8	R2C9[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/n1425_s0/F
8.046	0.588	tNET	RR	1	R4C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_6_s0/CLK
40.393	-0.032	tSu		1	R4C9[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/cmd_cache_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 2.223, 29.172%; route: 5.058, 66.371%; tC2Q: 0.340, 4.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/CLK
0.628	0.247	tC2Q	RR	2	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/Q
0.630	0.002	tNET	RR	1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/n47_s5/I1
0.906	0.276	tINS	RF	1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/n47_s5/F
0.906	0.000	tNET	FF	1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0/CLK
0.381	0.000	tHld		1	R9C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_RD_UFM/end_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/CLK
0.628	0.247	tC2Q	RR	3	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/Q
0.630	0.002	tNET	RR	1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n291_s3/I0
0.906	0.276	tINS	RF	1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n291_s3/F
0.906	0.000	tNET	FF	1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0/CLK
0.381	0.000	tHld		1	R12C14[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/wait_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/CLK
0.628	0.247	tC2Q	RR	3	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/Q
0.630	0.002	tNET	RR	1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n274_s3/I2
0.906	0.276	tINS	RF	1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n274_s3/F
0.906	0.000	tNET	FF	1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0/CLK
0.381	0.000	tHld		1	R13C17[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	2	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n273_s4/I0
0.906	0.276	tINS	RF	1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n273_s4/F
0.906	0.000	tNET	FF	1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0/CLK
0.381	0.000	tHld		1	R13C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvh_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/CLK
0.628	0.247	tC2Q	RR	3	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/Q
0.630	0.002	tNET	RR	1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n269_s3/I2
0.906	0.276	tINS	RF	1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n269_s3/F
0.906	0.000	tNET	FF	1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0/CLK
0.381	0.000	tHld		1	R14C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/CLK
0.628	0.247	tC2Q	RR	2	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/Q
0.630	0.002	tNET	RR	1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n264_s5/I2
0.906	0.276	tINS	RF	1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n264_s5/F
0.906	0.000	tNET	FF	1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0/CLK
0.381	0.000	tHld		1	R14C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/pgh_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/CLK
0.628	0.247	tC2Q	RR	3	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/Q
0.630	0.002	tNET	RR	1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n257_s3/I2
0.906	0.276	tINS	RF	1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n257_s3/F
0.906	0.000	tNET	FF	1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0/CLK
0.381	0.000	tHld		1	R13C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/prog_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/CLK
0.628	0.247	tC2Q	RR	4	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/Q
0.630	0.002	tNET	RR	1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n241_s6/I0
0.906	0.276	tINS	RF	1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n241_s6/F
0.906	0.000	tNET	FF	1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0/CLK
0.381	0.000	tHld		1	R13C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	2	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n238_s8/I0
0.906	0.276	tINS	RF	1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n238_s8/F
0.906	0.000	tNET	FF	1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0/CLK
0.381	0.000	tHld		1	R12C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/nvs_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/CLK
0.628	0.247	tC2Q	RR	2	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/Q
0.630	0.002	tNET	RR	1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n273_s6/I1
0.906	0.276	tINS	RF	1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n273_s6/F
0.906	0.000	tNET	FF	1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0/CLK
0.381	0.000	tHld		1	R17C17[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/end_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/CLK
0.628	0.247	tC2Q	RR	3	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/Q
0.630	0.002	tNET	RR	1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n266_s3/I0
0.906	0.276	tINS	RF	1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n266_s3/F
0.906	0.000	tNET	FF	1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0/CLK
0.381	0.000	tHld		1	R17C16[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	2	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n265_s3/I2
0.906	0.276	tINS	RF	1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n265_s3/F
0.906	0.000	tNET	FF	1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0/CLK
0.381	0.000	tHld		1	R17C16[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/rcv_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	2	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n256_s5/I2
0.906	0.276	tINS	RF	1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n256_s5/F
0.906	0.000	tNET	FF	1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0/CLK
0.381	0.000	tHld		1	R17C11[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/whd_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/CLK
0.628	0.247	tC2Q	RR	6	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/Q
0.630	0.002	tNET	RR	1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n255_s3/I0
0.906	0.276	tINS	RF	1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n255_s3/F
0.906	0.000	tNET	FF	1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0/CLK
0.381	0.000	tHld		1	R16C7[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/CLK
0.628	0.247	tC2Q	RR	5	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/Q
0.630	0.002	tNET	RR	1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n254_s3/I1
0.906	0.276	tINS	RF	1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n254_s3/F
0.906	0.000	tNET	FF	1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0/CLK
0.381	0.000	tHld		1	R16C8[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/CLK
0.628	0.247	tC2Q	RR	4	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/Q
0.630	0.002	tNET	RR	1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n253_s6/I0
0.906	0.276	tINS	RF	1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n253_s6/F
0.906	0.000	tNET	FF	1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0/CLK
0.381	0.000	tHld		1	R16C9[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	2	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n248_s5/I2
0.906	0.276	tINS	RF	1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n248_s5/F
0.906	0.000	tNET	FF	1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0/CLK
0.381	0.000	tHld		1	R16C8[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nhv_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/CLK
0.628	0.247	tC2Q	RR	3	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/Q
0.630	0.002	tNET	RR	1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n240_s3/I2
0.906	0.276	tINS	RF	1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n240_s3/F
0.906	0.000	tNET	FF	1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0/CLK
0.381	0.000	tHld		1	R17C12[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/CLK
0.628	0.247	tC2Q	RR	4	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/Q
0.630	0.002	tNET	RR	1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n235_s3/I2
0.906	0.276	tINS	RF	1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n235_s3/F
0.906	0.000	tNET	FF	1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0/CLK
0.381	0.000	tHld		1	R16C13[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/CLK
0.628	0.247	tC2Q	RR	4	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/Q
0.630	0.002	tNET	RR	1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n234_s3/I0
0.906	0.276	tINS	RF	1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n234_s3/F
0.906	0.000	tNET	FF	1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0/CLK
0.381	0.000	tHld		1	R16C14[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/CLK
0.628	0.247	tC2Q	RR	5	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/Q
0.630	0.002	tNET	RR	1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n233_s3/I0
0.906	0.276	tINS	RF	1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n233_s3/F
0.906	0.000	tNET	FF	1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0/CLK
0.381	0.000	tHld		1	R16C10[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.628	0.247	tC2Q	RR	4	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/Q
0.630	0.002	tNET	RR	1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n229_s3/I2
0.906	0.276	tINS	RF	1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n229_s3/F
0.906	0.000	tNET	FF	1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0/CLK
0.381	0.000	tHld		1	R16C11[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/CLK
0.628	0.247	tC2Q	RR	3	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/Q
0.630	0.002	tNET	RR	1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n226_s3/I2
0.906	0.276	tINS	RF	1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n226_s3/F
0.906	0.000	tNET	FF	1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0/CLK
0.381	0.000	tHld		1	R17C12[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/CLK
0.628	0.247	tC2Q	RR	6	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/Q
0.630	0.002	tNET	RR	1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n224_s5/I0
0.906	0.276	tINS	RF	1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n224_s5/F
0.906	0.000	tNET	FF	1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0/CLK
0.381	0.000	tHld		1	R17C6[0][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.906
Data Required Time	0.381
From	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0
To	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/CLK
0.628	0.247	tC2Q	RR	3	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/Q
0.630	0.002	tNET	RR	1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n219_s3/I2
0.906	0.276	tINS	RF	1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/n219_s3/F
0.906	0.000	tNET	FF	1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0/CLK
0.381	0.000	tHld		1	R17C6[1][A]	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/nvs_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	37.807
Data Arrival Time	2.467
Data Required Time	40.273
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	8	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.273	-0.152	tSu		1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path2

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLK
40.393	-0.032	tSu		1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
40.393	-0.032	tSu		1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLK
40.393	-0.032	tSu		1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path5

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLK
40.393	-0.032	tSu		1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path6

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLK
40.393	-0.032	tSu		1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
40.393	-0.032	tSu		1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLK
40.393	-0.032	tSu		1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path9

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
40.393	-0.032	tSu		1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
40.393	-0.032	tSu		1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
40.393	-0.032	tSu		1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
40.393	-0.032	tSu		1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
40.393	-0.032	tSu		1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
40.393	-0.032	tSu		1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLK
40.393	-0.032	tSu		1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path16

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLK
40.393	-0.032	tSu		1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path17

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLK
40.393	-0.032	tSu		1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path18

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
40.393	-0.032	tSu		1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path19

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLK
40.393	-0.032	tSu		1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
40.393	-0.032	tSu		1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path21

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLK
40.393	-0.032	tSu		1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLK
40.393	-0.032	tSu		1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLK
40.393	-0.032	tSu		1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path24

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLK
40.393	-0.032	tSu		1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	37.927
Data Arrival Time	2.467
Data Required Time	40.393
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.425	0.181	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.765	0.340	tC2Q	RF	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
2.467	1.702	tNET	FF	1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
40.425	0.181	tNET	RR	1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLK
40.393	-0.032	tSu		1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.702, 83.363%; tC2Q: 0.340, 16.637%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	8	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
0.391	0.009	tHld		1	BSRAM_R10[2]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1/CLK
0.391	0.009	tHld		1	R2C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1/CLK
0.391	0.009	tHld		1	R2C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1/CLK
0.391	0.009	tHld		1	R2C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1/CLK
0.391	0.009	tHld		1	R2C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1/CLK
0.391	0.009	tHld		1	R2C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
0.391	0.009	tHld		1	R2C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1/CLK
0.391	0.009	tHld		1	R2C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1/CLK
0.391	0.009	tHld		1	R2C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1/CLK
0.391	0.009	tHld		1	R2C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1/CLK
0.391	0.009	tHld		1	R2C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1/CLK
0.391	0.009	tHld		1	R2C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1/CLK
0.391	0.009	tHld		1	R2C16[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
0.391	0.009	tHld		1	R5C17[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0/CLK
0.391	0.009	tHld		1	R4C15[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0/CLK
0.391	0.009	tHld		1	R4C15[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0/CLK
0.391	0.009	tHld		1	R4C15[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0/CLK
0.391	0.009	tHld		1	R4C15[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0/CLK
0.391	0.009	tHld		1	R4C15[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0/CLK
0.391	0.009	tHld		1	R4C15[2][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0/CLK
0.391	0.009	tHld		1	R4C16[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0/CLK
0.391	0.009	tHld		1	R4C16[0][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0/CLK
0.391	0.009	tHld		1	R4C16[1][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0/CLK
0.391	0.009	tHld		1	R4C16[1][B]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	1.382
Data Arrival Time	1.773
Data Required Time	0.391
From	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/CLK
0.628	0.247	tC2Q	RR	194	R4C6[0][A]	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N_s0/Q
1.773	1.144	tNET	RR	1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.245	0.245	tCL	RR	685	BOTTOMSIDE[1]	inst_clk_25M/clkdiv_inst/CLKOUT
0.381	0.137	tNET	RR	1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0/CLK
0.391	0.009	tHld		1	R4C16[2][A]	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/wbin_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.144, 82.246%; tC2Q: 0.247, 17.754%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	led_cnt_30_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	led_cnt_30_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	led_cnt_30_s0/CLK

MPW2

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	led_cnt_28_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	led_cnt_28_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	led_cnt_28_s0/CLK

MPW3

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	led_cnt_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	led_cnt_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	led_cnt_24_s0/CLK

MPW4

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	led_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	led_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	led_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	led_cnt_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	led_cnt_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	led_cnt_0_s0/CLK

MPW6

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/mosi_shift_reg_4_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/mosi_shift_reg_4_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/mosi_shift_reg_4_s1/CLK

MPW7

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/data_counter_0_s0/CLK

MPW8

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	inst_bg_spi_usrflash/rd_data_reg_28_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	inst_bg_spi_usrflash/rd_data_reg_28_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	inst_bg_spi_usrflash/rd_data_reg_28_s0/CLK

MPW9

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_15_s0/CLK

MPW10

MPW Summary:

Slack:	19.016
Actual Width:	19.942
Required Width:	0.926
Type:	Low Pulse Width
Clock:	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
20.245	0.245	tCL	FF	inst_clk_25M/clkdiv_inst/CLKOUT
20.439	0.195	tNET	FF	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.245	0.245	tCL	RR	inst_clk_25M/clkdiv_inst/CLKOUT
40.381	0.137	tNET	RR	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_ER_UFM/erase_cnt_16_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
685	clk	29.806	0.195
194	inst_goConfig_SPI_Top/inst_GW_SPI/RST_N	36.532	2.061
49	inst_goConfig_SPI_Top/inst_GW_SPI/CS_reg	34.416	2.405
45	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/u_WR_UFM/n230_46	35.319	1.776
44	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/wdata_31_5	34.072	1.345
42	inst_bg_spi_usrflash/wr_data_reg_31_8	33.856	2.701
37	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/User_model_state[1]	34.114	2.314
35	f_start	34.891	2.058
35	u_Gowin_Flash_Controller_Top/u_Flash_Ctroller_96KA/n300_24	35.212	1.584
34	f_erase	35.446	1.581

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C13	100.00%
R3C15	100.00%
R4C2	100.00%
R7C11	100.00%
R7C13	100.00%
R14C9	100.00%
R14C12	100.00%
R14C6	100.00%
R14C8	100.00%
R13C17	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command