PnR Messages

Report Title PnR Report
Design File E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\ref_design\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\ref_design\project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.12 (64-bit)
Part Number GW1N-LV2LQ144XC7/I6
Device GW1N-2
Device Version C
Created Time Mon Aug 11 08:47:28 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.179s, Elapsed time = 0h 0m 0.179s Placement Phase 1: CPU time = 0h 0m 0.032s, Elapsed time = 0h 0m 0.031s Placement Phase 2: CPU time = 0h 0m 0.166s, Elapsed time = 0h 0m 0.167s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Running routing: Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Routing Phase 1: CPU time = 0h 0m 0.207s, Elapsed time = 0h 0m 0.207s Routing Phase 2: CPU time = 0h 0m 0.414s, Elapsed time = 0h 0m 0.414s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.622s, Elapsed time = 0h 0m 0.622s Generate output files: CPU time = 0h 0m 0.514s, Elapsed time = 0h 0m 0.515s
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 251MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1040/2304 46%
    --LUT,ALU,ROM16 1040(987 LUT, 53 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 683/2646 26%
    --Logic Register as Latch 0/2304 0%
    --Logic Register as FF 680/2016 34%
    --I/O Register as Latch 0/342 0%
    --I/O Register as FF 3/342 <1%
CLS 670/1152 59%
I/O Port 22/114 20%
I/O Buf 21 -
    --Input Buf 6 -
    --Output Buf 15 -
    --Inout Buf 0 -
BSRAM 1 SDPB
 25%
FLASH96KA 1/1 100%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 1/294%
bank 1 10/2836%
bank 2 6/2921%
bank 3 0/80%
bank 4 0/100%
bank 5 4/1040%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 2/8 25%
GCLK_PIN 1/8 13%
CLKDIV 1/8 13%

Global Clock Signals:

Signal Global Clock Location
clk PRIMARY LEFT RIGHT
rstn_d LW -
inst_goConfig_SPI_Top/inst_GW_SPI/RST_N LW -
clk_in_d HCLK

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
GW_BACKGROUND_EXT_SCLK - 105/1 Y in IOR2[A] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
GW_BACKGROUND_EXT_CS_N - 104/1 Y in IOR2[B] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
GW_BACKGROUND_EXT_MOSI - 106/1 Y in IOR1[B] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
GW_BACKGROUND_EXT_SEL - 83/1 Y in IOR15[B] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
clk_in - 55/2 Y in IOB9[A] GCLKT_3 LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
rstn - 78/1 N in IOR17[A] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
GW_BACKGROUND_EXT_MISO - 107/1 Y out IOR1[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
GW_BACKGROUND_RECONFIG_N - 119/0 Y out IOT16[B] RECONFIG_N LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
Test_LED - 38/2 Y out IOB2[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
jtag_test[0] - 12/5 Y out IOL8[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
jtag_test[1] - 11/5 Y out IOL8[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
jtag_test[2] - 10/5 Y out IOL7[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
jtag_test[3] - 9/5 Y out IOL7[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
spi_test[0] - 45/2 Y out IOB5[B] SO LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
spi_test[1] - 44/2 Y out IOB5[A] SCLK LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
spi_test[2] - 43/2 Y out IOB4[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
spi_test[3] - 42/2 Y out IOB4[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
test_pin[0] - 76/1 Y out IOR18[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
test_pin[1] - 75/1 Y out IOR18[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
test_pin[2] - 74/1 Y out IOR19[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
test_pin[3] - 73/1 Y out IOR19[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
143/0 - in IOT4[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
142/0 - in IOT4[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
141/0 - in IOT5[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
140/0 - in IOT5[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
139/0 - in IOT6[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
138/0 - in IOT6[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
137/0 - out IOT7[A] TDO LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
136/0 - in IOT7[B] TDI LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
133/0 - in IOT8[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
132/0 - in IOT8[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
131/0 - in IOT9[A] TCK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
130/0 - in IOT9[B] TMS LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
128/0 - in IOT11[A] GCLKT_0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
127/0 - in IOT11[B] GCLKC_0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
129/0 - in IOT12[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
122/0 - in IOT13[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
121/0 - in IOT13[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
126/0 - in IOT14[A] GCLKT_1/SCL LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
125/0 - in IOT14[B] GCLKC_1/SDA LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
117/0 - in IOT15[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
115/0 - in IOT15[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
120/0 - in IOT16[A] JTAGSEL_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
119/0 GW_BACKGROUND_RECONFIG_N out IOT16[B] RECONFIG_N LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
114/0 - in IOT17[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
113/0 - in IOT17[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
110/0 - in IOT18[A] READY LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
109/0 - in IOT18[B] DONE LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
112/0 - in IOT19[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
111/0 - in IOT19[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
38/2 Test_LED out IOB2[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
39/2 - in IOB2[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
40/2 - in IOB3[A] DIN/CLKHOLD_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
41/2 - in IOB3[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
42/2 spi_test[3] out IOB4[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
43/2 spi_test[2] out IOB4[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
44/2 spi_test[1] out IOB5[A] SCLK LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
45/2 spi_test[0] out IOB5[B] SO LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
47/2 - in IOB6[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
48/2 - in IOB6[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
49/2 - in IOB7[A] GCLKT_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
50/2 - in IOB7[B] GCLKC_4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
52/2 - in IOB8[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
54/2 - in IOB8[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
55/2 clk_in in IOB9[A] GCLKT_3 LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
56/2 - in IOB9[B] GCLKC_3 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
57/2 - in IOB11[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
58/2 - in IOB11[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
59/2 - in IOB12[A] FASTRD_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
60/2 - in IOB12[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
61/2 - in IOB13[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
62/2 - in IOB13[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
63/2 - in IOB14[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
65/2 - in IOB15[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
67/2 - in IOB15[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
68/2 - in IOB16[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
69/2 - in IOB16[B] DOUT/WE_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
70/2 - in IOB18[A] SSPI_CS_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
71/2 - in IOB18[B] SI LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
1/5 - in IOL4[A] LPLL_T_fb LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
2/5 - in IOL4[B] LPLL_C_fb LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/5 - in IOL5[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/5 - in IOL5[B] LPLL_C_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
5/5 - in IOL6[A] GCLKT_7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
6/5 - in IOL6[B] GCLKC_7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
9/5 jtag_test[3] out IOL7[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
10/5 jtag_test[2] out IOL7[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
11/5 jtag_test[1] out IOL8[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
12/5 jtag_test[0] out IOL8[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
13/4 - in IOL9[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/4 - in IOL9[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/4 - in IOL11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/4 - in IOL11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/4 - in IOL12[A] GCLKT_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/4 - in IOL12[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/4 - in IOL13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/4 - in IOL13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/4 - in IOL14[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/4 - in IOL14[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/3 - in IOL15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/3 - in IOL15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/3 - in IOL16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/3 - in IOL16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/3 - in IOL17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/3 - in IOL17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/3 - in IOL18[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/3 - in IOL18[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
107/1 GW_BACKGROUND_EXT_MISO out IOR1[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
106/1 GW_BACKGROUND_EXT_MOSI in IOR1[B] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
105/1 GW_BACKGROUND_EXT_SCLK in IOR2[A] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
104/1 GW_BACKGROUND_EXT_CS_N in IOR2[B] - LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
100/1 - in IOR3[A] D2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
99/1 - in IOR3[B] D3 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
98/1 - in IOR4[A] D0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
97/1 - in IOR4[B] D1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
96/1 - in IOR5[A] MI/D7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
95/1 - in IOR5[B] MO/D6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
94/1 - in IOR6[A] MCS_N/D5 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
93/1 - in IOR6[B] MCLK/D4 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
92/1 - in IOR11[A] GCLKT_2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
91/1 - in IOR11[B] GCLKC_2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
89/1 - in IOR13[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
87/1 - in IOR13[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
86/1 - in IOR14[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
85/1 - in IOR14[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
84/1 - in IOR15[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
83/1 GW_BACKGROUND_EXT_SEL in IOR15[B] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
82/1 - in IOR16[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
81/1 - in IOR16[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
78/1 rstn in IOR17[A] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
77/1 - in IOR17[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
76/1 test_pin[0] out IOR18[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
75/1 test_pin[1] out IOR18[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
74/1 test_pin[2] out IOR19[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
73/1 test_pin[3] out IOR19[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3