Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\pro\ip_user_flash\ref_design\fpga_project_1\src\goconfig_spi\goconfig_spi.v E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\pro\ip_user_flash\ref_design\fpga_project_1\src\top.v E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\pro\ip_user_flash\ref_design\fpga_project_1\src\ip_flash\bg_spi_usrflash.v E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\pro\ip_user_flash\ref_design\fpga_project_1\src\gowin_flash_controller\gowin_flash_controller.v E:\work_files\IP_A_new\GoConfig\00_2025\spi_jtag\pro\ip_user_flash\ref_design\fpga_project_1\src\gowin_clkdiv\gowin_clkdiv.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12 (64-bit)
Part Number	GW1N-LV2LQ144XC7/I6
Device	GW1N-2
Device Version	C
Created Time	Fri Aug 8 15:12:00 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	bg_flash_top
Synthesis Process	Running parser:     CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.26s, Peak memory usage = 244.180MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 244.180MB     Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 244.180MB     Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 244.180MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 244.180MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 244.180MB     Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 244.180MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 244.180MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 244.180MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 244.180MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 244.180MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.51s, Peak memory usage = 272.742MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 272.742MB Generate output files:     CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 272.742MB
Total Time and Memory Usage	CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 272.742MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	21
I/O Buf	21
IBUF	6
OBUF	15
Register	683
DFF	4
DFFE	4
DFFP	4
DFFPE	9
DFFC	368
DFFCE	294
LUT	981
LUT2	251
LUT3	182
LUT4	548
ALU	48
ALU	48
INV	8
INV	8
BSRAM	1
SDPB	1
CLOCK	1
CLKDIV	1
User Flash	1
FLASH96KA	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	1037(989 LUT, 48 ALU) / 2304	46%
Register	683 / 2646	26%
--Register as Latch	0 / 2646	0%
--Register as FF	683 / 2358	29%
BSRAM	1 / 4	25%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	Generated	40.000	25.000	0.000	20.000		DEFAULT_CLK	inst_clk_25M/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk	25.000(MHz)	103.935(MHz)	9	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	30.379
Data Arrival Time	10.402
Data Required Time	40.780
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
1.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/CLK
1.416	0.340	tC2Q	RF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/Q
2.128	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.942	0.814	tINS	FF	6	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.653	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.468	0.814	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
5.179	0.711	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.953	0.774	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.953	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.996	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.996	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
6.038	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
6.038	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
6.455	0.417	tINS	FF	3	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/SUM
7.166	0.711	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/I0
7.876	0.710	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/COUT
7.876	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/CIN
7.919	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/COUT
7.919	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/CIN
7.961	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/COUT
7.961	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/CIN
8.003	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/COUT
8.003	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/CIN
8.045	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
8.045	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
8.088	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
8.088	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
8.130	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
8.130	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
8.172	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
8.172	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
8.214	0.042	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.926	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/I0
9.690	0.765	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rempty_val_s1/F
10.402	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
40.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
41.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0/CLK
40.780	-0.296	tSu		1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Empty_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	40.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 4.717, 50.587%; route: 4.268, 45.771%; tC2Q: 0.340, 3.642%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:

Slack	30.880
Data Arrival Time	10.058
Data Required Time	40.938
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
1.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/CLK
1.416	0.340	tC2Q	RF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/rden_s0/Q
2.128	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/I1
2.942	0.814	tINS	FF	6	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/FIFO_rden_s0/F
3.653	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/I1
4.468	0.814	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n101_s0/F
5.179	0.711	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/I1
5.953	0.774	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_0_s/COUT
5.953	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/CIN
5.996	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_1_s/COUT
5.996	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/CIN
6.038	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_2_s/COUT
6.038	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/CIN
6.455	0.417	tINS	FF	3	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/rbin_next_3_s/SUM
7.166	0.711	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/I0
7.876	0.710	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n241_s0/COUT
7.876	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/CIN
7.919	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n242_s0/COUT
7.919	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/CIN
7.961	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n243_s0/COUT
7.961	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/CIN
8.003	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n244_s0/COUT
8.003	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/CIN
8.045	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n245_s0/COUT
8.045	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/CIN
8.088	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n246_s0/COUT
8.088	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/CIN
8.130	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n247_s0/COUT
8.130	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/CIN
8.172	0.042	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n248_s0/COUT
8.172	0.000	tNET	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/CIN
8.214	0.042	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n249_s0/COUT
8.926	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/I2
9.520	0.594	tINS	FR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n13_s0/F
10.058	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CEB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
40.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
41.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB
40.938	-0.139	tSu		1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/mem_mem_0_0_s

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	40.000
Logic Level:	9
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 4.547, 50.625%; route: 4.095, 45.593%; tC2Q: 0.340, 3.782%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:

Slack	31.424
Data Arrival Time	9.356
Data Required Time	40.780
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_0_s3
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
1.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
1.416	0.340	tC2Q	RF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
2.128	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.942	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.653	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
4.468	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
5.179	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/I0
5.944	0.765	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/F
6.655	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
7.470	0.814	tINS	FF	8	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
8.181	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n100_s6/I3
8.645	0.464	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n100_s6/F
9.356	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
40.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
41.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_0_s3/CLK
40.780	-0.296	tSu		1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_0_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	40.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:

Slack	31.424
Data Arrival Time	9.356
Data Required Time	40.780
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_1_s3
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
1.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
1.416	0.340	tC2Q	RF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
2.128	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.942	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.653	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
4.468	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
5.179	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/I0
5.944	0.765	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/F
6.655	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
7.470	0.814	tINS	FF	8	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
8.181	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n99_s6/I3
8.645	0.464	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n99_s6/F
9.356	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
40.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
41.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_1_s3/CLK
40.780	-0.296	tSu		1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_1_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	40.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:

Slack	31.424
Data Arrival Time	9.356
Data Required Time	40.780
From	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1
To	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_2_s3
Launch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]
Latch Clk	inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
0.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
1.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/CLK
1.416	0.340	tC2Q	RF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Wnum_5_s1/Q
2.128	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/I1
2.942	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/n7_s2/F
3.653	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/I1
4.468	0.814	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_jtag/u_fifo/fifo_sc_hs_inst/Full_d_s/F
5.179	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/I0
5.944	0.765	tINS	FF	2	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n139_s0/F
6.655	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/I1
7.470	0.814	tINS	FF	8	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_7_s5/F
8.181	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n98_s6/I3
8.645	0.464	tINS	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/n98_s6/F
9.356	0.711	tNET	FF	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_2_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
40.000	0.000				inst_clk_25M/clkdiv_inst/CLKOUT.default_gen_clk
40.539	0.539	tCL	RR	685	inst_clk_25M/clkdiv_inst/CLKOUT
41.077	0.538	tNET	RR	1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_2_s3/CLK
40.780	-0.296	tSu		1	inst_goConfig_SPI_Top/inst_GW_SPI/U_spi_slave/spi_data_2_s3

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	40.000
Logic Level:	6
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.672, 44.347%; route: 4.268, 51.551%; tC2Q: 0.340, 4.102%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%