Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FP_Nat_Log\data\FP_Natural_Logarithm_wrap.v C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FP_Nat_Log\data\FP_Natural_Logarithm.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Tue May 7 15:37:21 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FP_Natural_Logarithm_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.782s, Peak memory usage = 197.266MB Running netlist conversion: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 197.266MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.733s, Peak memory usage = 197.266MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 197.266MB Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 197.266MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 197.266MB Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 197.266MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 197.266MB Inferring Phase 3: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 197.266MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.968s, Elapsed time = 0h 0m 0.978s, Peak memory usage = 197.266MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 197.266MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 197.266MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 197.266MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.24s, Peak memory usage = 197.266MB Generate output files: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.637s, Peak memory usage = 214.922MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 214.922MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 69 |
| I/O Buf | 69 |
| IBUF | 35 |
| OBUF | 34 |
| Register | 4024 |
| DFFRE | 3655 |
| DFFCE | 369 |
| LUT | 941 |
| LUT2 | 62 |
| LUT3 | 640 |
| LUT4 | 239 |
| ALU | 4895 |
| ALU | 4895 |
| INV | 39 |
| INV | 39 |
| DSP | |
| MULTALU27X18 | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5875(980 LUT, 4895 ALU) / 23040 | 26% |
| Register | 4024 / 23685 | 17% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 4024 / 23685 | 17% |
| BSRAM | 0 / 56 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.000(MHz) | 93.189(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.731 |
| Data Arrival Time | 11.042 |
| Data Required Time | 10.311 |
| From | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| To | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_28_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 32 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
| 4.478 | 4.103 | tC2Q | RF | 2 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[3] |
| 4.828 | 0.350 | tNET | FF | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I0 |
| 5.355 | 0.526 | tINS | FR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 5.730 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 6.246 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 6.621 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 7.137 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 7.512 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 8.028 | 0.516 | tINS | RR | 9 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 8.403 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/I0 |
| 8.930 | 0.526 | tINS | RR | 3 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/F |
| 9.305 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/I2 |
| 9.766 | 0.461 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/F |
| 10.141 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n109_s1/I0 |
| 10.667 | 0.526 | tINS | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n109_s1/F |
| 11.042 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_28_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_28_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_28_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.589, 33.643%; route: 2.975, 27.890%; tC2Q: 4.103, 38.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | -0.731 |
| Data Arrival Time | 11.042 |
| Data Required Time | 10.311 |
| From | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| To | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 32 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
| 4.478 | 4.103 | tC2Q | RF | 2 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[3] |
| 4.828 | 0.350 | tNET | FF | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I0 |
| 5.355 | 0.526 | tINS | FR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 5.730 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 6.246 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 6.621 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 7.137 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 7.512 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 8.028 | 0.516 | tINS | RR | 9 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 8.403 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/I0 |
| 8.930 | 0.526 | tINS | RR | 3 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/F |
| 9.305 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/I2 |
| 9.766 | 0.461 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/F |
| 10.141 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s1/I0 |
| 10.667 | 0.526 | tINS | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s1/F |
| 11.042 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.589, 33.643%; route: 2.975, 27.890%; tC2Q: 4.103, 38.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | -0.721 |
| Data Arrival Time | 11.032 |
| Data Required Time | 10.311 |
| From | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| To | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 32 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
| 4.478 | 4.103 | tC2Q | RF | 2 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[3] |
| 4.828 | 0.350 | tNET | FF | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I0 |
| 5.355 | 0.526 | tINS | FR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 5.730 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 6.246 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 6.621 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 7.137 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 7.512 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 8.028 | 0.516 | tINS | RR | 9 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 8.403 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/I0 |
| 8.930 | 0.526 | tINS | RR | 3 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/F |
| 9.305 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/I2 |
| 9.766 | 0.461 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/F |
| 10.141 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n108_s1/I1 |
| 10.657 | 0.516 | tINS | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n108_s1/F |
| 11.032 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.579, 33.581%; route: 2.975, 27.916%; tC2Q: 4.103, 38.503% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | -0.666 |
| Data Arrival Time | 10.977 |
| Data Required Time | 10.311 |
| From | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| To | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_31_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 32 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
| 4.478 | 4.103 | tC2Q | RF | 2 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[3] |
| 4.828 | 0.350 | tNET | FF | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I0 |
| 5.355 | 0.526 | tINS | FR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 5.730 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 6.246 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 6.621 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 7.137 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 7.512 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 8.028 | 0.516 | tINS | RR | 9 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 8.403 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/I0 |
| 8.930 | 0.526 | tINS | RR | 3 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/F |
| 9.305 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/I2 |
| 9.766 | 0.461 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/F |
| 10.141 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n106_s2/I2 |
| 10.602 | 0.461 | tINS | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n106_s2/F |
| 10.977 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_31_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_31_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_31_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.524, 33.236%; route: 2.975, 28.061%; tC2Q: 4.103, 38.703% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | -0.532 |
| Data Arrival Time | 10.843 |
| Data Required Time | 10.311 |
| From | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| To | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_21_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 32 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
| 4.478 | 4.103 | tC2Q | RF | 2 | FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[3] |
| 4.828 | 0.350 | tNET | FF | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I0 |
| 5.355 | 0.526 | tINS | FR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 5.730 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 6.246 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 6.621 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 7.137 | 0.516 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 7.512 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 8.028 | 0.516 | tINS | RR | 9 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 8.403 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n117_s5/I0 |
| 8.930 | 0.526 | tINS | RR | 4 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n117_s5/F |
| 9.305 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n115_s5/I3 |
| 9.567 | 0.262 | tINS | RR | 2 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n115_s5/F |
| 9.942 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n116_s1/I0 |
| 10.468 | 0.526 | tINS | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n116_s1/F |
| 10.843 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_21_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 4025 | clk_ibuf/O |
| 10.375 | 0.375 | tNET | RR | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_21_s0/CLK |
| 10.311 | -0.064 | tSu | 1 | FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_21_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 3.390, 32.383%; route: 2.975, 28.419%; tC2Q: 4.103, 39.198% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |