Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.03\Gowin_FP_Natural_Logarithm\FP_Natural_Logarithm_RefDesign\proj\impl\gwsynthesis\Natural_Logarithm.vg |
| Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.9.03\Gowin_FP_Natural_Logarithm\FP_Natural_Logarithm_RefDesign\proj\src\Natural_Logarithm.cst |
| Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.9.03\Gowin_FP_Natural_Logarithm\FP_Natural_Logarithm_RefDesign\proj\src\Natural_Logarithm.sdc |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Tue May 7 15:58:45 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.855V 0C ES |
| Hold Delay Model | Fast 0.945V 85C ES |
| Numbers of Paths Analyzed | 13643 |
| Numbers of Endpoints Analyzed | 14080 |
| Numbers of Falling Endpoints | 3 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk | ||
| tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 79.556(MHz) | 9 | TOP |
| 2 | tck_pad_i | 20.000(MHz) | 110.178(MHz) | 6 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk | Setup | 0.000 | 0 |
| clk | Hold | 0.000 | 0 |
| tck_pad_i | Setup | 0.000 | 0 |
| tck_pad_i | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 7.430 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0/D | clk:[R] | clk:[R] | 20.000 | -0.040 | 12.546 |
| 2 | 7.926 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_16_s0/D | clk:[R] | clk:[R] | 20.000 | -0.047 | 12.058 |
| 3 | 7.935 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0/D | clk:[R] | clk:[R] | 20.000 | -0.047 | 12.049 |
| 4 | 8.050 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D | clk:[R] | clk:[R] | 20.000 | -0.031 | 11.917 |
| 5 | 8.062 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_17_s0/D | clk:[R] | clk:[R] | 20.000 | -0.040 | 11.915 |
| 6 | 8.093 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/D | clk:[R] | clk:[R] | 20.000 | -0.022 | 11.865 |
| 7 | 8.130 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/D | clk:[R] | clk:[R] | 20.000 | -0.031 | 11.838 |
| 8 | 8.206 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D | clk:[R] | clk:[R] | 20.000 | -0.033 | 11.764 |
| 9 | 8.340 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_49_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.596 |
| 10 | 8.352 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_50_s0/D | clk:[R] | clk:[R] | 20.000 | -0.009 | 11.594 |
| 11 | 8.436 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D | clk:[R] | clk:[R] | 20.000 | -0.031 | 11.531 |
| 12 | 8.442 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_48_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.494 |
| 13 | 8.449 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/D | clk:[R] | clk:[R] | 20.000 | -0.046 | 11.532 |
| 14 | 8.457 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_47_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.479 |
| 15 | 8.509 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_50_s0/D | clk:[R] | clk:[R] | 20.000 | 0.010 | 11.417 |
| 16 | 8.518 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/D | clk:[R] | clk:[R] | 20.000 | -0.024 | 11.443 |
| 17 | 8.519 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_19_s0/D | clk:[R] | clk:[R] | 20.000 | -0.038 | 11.455 |
| 18 | 8.523 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/D | clk:[R] | clk:[R] | 20.000 | -0.022 | 11.435 |
| 19 | 8.560 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_46_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.376 |
| 20 | 8.613 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/D | clk:[R] | clk:[R] | 20.000 | -0.047 | 11.371 |
| 21 | 8.618 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_45_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.318 |
| 22 | 8.651 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_49_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.285 |
| 23 | 8.709 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_43_s0/D | clk:[R] | clk:[R] | 20.000 | 0.010 | 11.218 |
| 24 | 8.719 | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[29].Iteration_pos_inst/data_r_out_2_s0/Q | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0/D | clk:[R] | clk:[R] | 20.000 | 0.053 | 11.165 |
| 25 | 8.721 | mem_data_in_mem_data_in_0_0_s/DO[0] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_44_s0/D | clk:[R] | clk:[R] | 20.000 | 0.000 | 11.215 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.008 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] | clk:[R] | clk:[R] | 0.000 | 0.014 | 0.243 |
| 2 | 0.008 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] | clk:[R] | clk:[R] | 0.000 | 0.014 | 0.243 |
| 3 | 0.013 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3] | clk:[R] | clk:[R] | 0.000 | 0.017 | 0.245 |
| 4 | 0.013 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] | clk:[R] | clk:[R] | 0.000 | 0.017 | 0.245 |
| 5 | 0.021 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15] | clk:[R] | clk:[R] | 0.000 | 0.025 | 0.245 |
| 6 | 0.083 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] | clk:[R] | clk:[R] | 0.000 | 0.014 | 0.318 |
| 7 | 0.092 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] | clk:[R] | clk:[R] | 0.000 | 0.021 | 0.320 |
| 8 | 0.092 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.021 | 0.320 |
| 9 | 0.094 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.333 |
| 10 | 0.096 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] | clk:[R] | clk:[R] | 0.000 | 0.025 | 0.320 |
| 11 | 0.100 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.339 |
| 12 | 0.100 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.339 |
| 13 | 0.100 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.339 |
| 14 | 0.105 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8] | clk:[R] | clk:[R] | 0.000 | 0.013 | 0.341 |
| 15 | 0.107 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7] | clk:[R] | clk:[R] | 0.000 | 0.021 | 0.335 |
| 16 | 0.117 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6] | clk:[R] | clk:[R] | 0.000 | 0.025 | 0.341 |
| 17 | 0.158 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[4] | clk:[R] | clk:[R] | 0.000 | 0.017 | 0.390 |
| 18 | 0.159 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.027 | 0.381 |
| 19 | 0.167 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[10] | clk:[R] | clk:[R] | 0.000 | 0.017 | 0.399 |
| 20 | 0.175 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] | clk:[R] | clk:[R] | 0.000 | 0.010 | 0.414 |
| 21 | 0.184 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6] | clk:[R] | clk:[R] | 0.000 | 0.013 | 0.420 |
| 22 | 0.184 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5] | clk:[R] | clk:[R] | 0.000 | 0.013 | 0.420 |
| 23 | 0.194 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] | clk:[R] | clk:[R] | 0.000 | 0.005 | 0.438 |
| 24 | 0.200 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] | clk:[R] | clk:[R] | 0.000 | 0.014 | 0.435 |
| 25 | 0.200 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2] | clk:[R] | clk:[R] | 0.000 | 0.014 | 0.435 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 7.427 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.035 | 2.191 |
| 2 | 7.427 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.035 | 2.191 |
| 3 | 7.427 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.035 | 2.191 |
| 4 | 7.600 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.054 | 1.998 |
| 5 | 7.600 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.054 | 1.998 |
| 6 | 7.610 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.998 |
| 7 | 7.637 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET | clk:[F] | clk:[R] | 10.000 | 0.035 | 1.981 |
| 8 | 7.637 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.035 | 1.981 |
| 9 | 7.820 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.788 |
| 10 | 7.820 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.788 |
| 11 | 7.820 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.788 |
| 12 | 7.820 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.788 |
| 13 | 7.820 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.045 | 1.788 |
| 14 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 15 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 16 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 17 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 18 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 19 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 20 | 8.047 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.061 | 1.544 |
| 21 | 8.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.052 | 1.544 |
| 22 | 8.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.052 | 1.544 |
| 23 | 8.056 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.052 | 1.544 |
| 24 | 8.240 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.002 | 1.411 |
| 25 | 8.240 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR | clk:[F] | clk:[R] | 10.000 | 0.002 | 1.411 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 10.412 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.004 | 0.355 |
| 2 | 10.421 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.361 |
| 3 | 10.423 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.361 |
| 4 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 5 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 6 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 7 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 8 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 9 | 10.424 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.010 | 0.361 |
| 10 | 10.428 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.014 | 0.361 |
| 11 | 10.434 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.014 | 0.367 |
| 12 | 10.434 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.014 | 0.367 |
| 13 | 10.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.465 |
| 14 | 10.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.465 |
| 15 | 10.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.465 |
| 16 | 10.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.465 |
| 17 | 10.527 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.009 | 0.465 |
| 18 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 19 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 20 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 21 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 22 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 23 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 24 | 10.625 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.007 | 0.565 |
| 25 | 10.703 | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR | clk:[F] | clk:[R] | -10.000 | 0.037 | 0.613 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 8.156 | 9.156 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| 2 | 8.156 | 9.156 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
| 3 | 8.157 | 9.157 | 1.000 | Low Pulse Width | clk | mem_data_in_mem_data_in_0_0_s |
| 4 | 8.161 | 9.161 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| 5 | 8.161 | 9.161 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| 6 | 8.164 | 9.164 | 1.000 | Low Pulse Width | clk | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
| 7 | 8.167 | 9.167 | 1.000 | High Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| 8 | 8.167 | 9.167 | 1.000 | High Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
| 9 | 8.167 | 9.167 | 1.000 | Low Pulse Width | clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| 10 | 8.168 | 9.168 | 1.000 | High Pulse Width | clk | mem_data_in_mem_data_in_0_0_s |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 7.430 |
| Data Arrival Time | 14.525 |
| Data Required Time | 21.955 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.551 | 1.107 | tNET | RR | 1 | R9C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s10/I2 |
| 8.814 | 0.262 | tINS | RR | 3 | R9C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s10/F |
| 8.976 | 0.162 | tNET | RR | 1 | R8C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s7/I0 |
| 9.438 | 0.461 | tINS | RR | 3 | R8C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s7/F |
| 10.305 | 0.868 | tNET | RR | 1 | R5C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s1/I1 |
| 10.826 | 0.521 | tINS | RR | 1 | R5C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s1/F |
| 10.829 | 0.003 | tNET | RR | 1 | R5C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s/I1 |
| 11.244 | 0.415 | tINS | RR | 2 | R5C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s/F |
| 14.525 | 3.281 | tNET | RR | 1 | R8C61[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.019 | 1.337 | tNET | RR | 1 | R8C61[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0/CLK |
| 21.955 | -0.064 | tSu | 1 | R8C61[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_18_s0 |
Path Statistics:
| Clock Skew | 0.040 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.471, 27.668%; route: 8.693, 69.284%; tC2Q: 0.382, 3.049% |
| Required Clock Path Delay | cell: 0.683, 33.803%; route: 1.337, 66.197% |
Path2
Path Summary:
| Slack | 7.926 |
| Data Arrival Time | 14.036 |
| Data Required Time | 21.962 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_16_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.416 | 0.973 | tNET | RR | 1 | R9C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s12/I2 |
| 8.932 | 0.516 | tINS | RR | 2 | R9C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s12/F |
| 9.092 | 0.160 | tNET | RR | 1 | R8C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s39/I1 |
| 9.609 | 0.516 | tINS | RR | 3 | R8C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s39/F |
| 9.771 | 0.162 | tNET | RR | 1 | R8C15[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_14_s1/I1 |
| 10.186 | 0.415 | tINS | RR | 1 | R8C15[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_14_s1/F |
| 10.534 | 0.347 | tNET | RR | 1 | R7C17[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_14_s/I1 |
| 10.949 | 0.415 | tINS | RR | 2 | R7C17[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_14_s/F |
| 14.036 | 3.088 | tNET | RR | 1 | R7C61[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.026 | 1.344 | tNET | RR | 1 | R7C61[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_16_s0/CLK |
| 21.962 | -0.064 | tSu | 1 | R7C61[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_16_s0 |
Path Statistics:
| Clock Skew | 0.047 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.674, 30.469%; route: 8.001, 66.359%; tC2Q: 0.382, 3.172% |
| Required Clock Path Delay | cell: 0.683, 33.683%; route: 1.344, 66.317% |
Path3
Path Summary:
| Slack | 7.935 |
| Data Arrival Time | 14.027 |
| Data Required Time | 21.962 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.416 | 0.973 | tNET | RR | 1 | R9C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s7/I2 |
| 8.938 | 0.521 | tINS | RR | 3 | R9C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s7/F |
| 9.480 | 0.542 | tNET | RR | 1 | R7C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s2/I0 |
| 10.006 | 0.526 | tINS | RR | 1 | R7C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s2/F |
| 10.354 | 0.347 | tNET | RR | 1 | R6C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s0/I2 |
| 10.616 | 0.262 | tINS | RR | 1 | R6C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s0/F |
| 10.619 | 0.003 | tNET | RR | 1 | R6C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s/I0 |
| 11.080 | 0.461 | tINS | RR | 2 | R6C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_12_s/F |
| 14.027 | 2.948 | tNET | RR | 1 | R7C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.026 | 1.344 | tNET | RR | 1 | R7C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0/CLK |
| 21.962 | -0.064 | tSu | 1 | R7C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_14_s0 |
Path Statistics:
| Clock Skew | 0.047 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.582, 29.733%; route: 8.084, 67.092%; tC2Q: 0.382, 3.175% |
| Required Clock Path Delay | cell: 0.683, 33.683%; route: 1.344, 66.317% |
Path4
Path Summary:
| Slack | 8.050 |
| Data Arrival Time | 13.896 |
| Data Required Time | 21.946 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.341 | 0.897 | tNET | RR | 1 | R7C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s14/I2 |
| 8.631 | 0.290 | tINS | RF | 3 | R7C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s14/F |
| 8.971 | 0.340 | tNET | FF | 1 | R7C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_18_s6/I3 |
| 9.433 | 0.461 | tINS | FR | 2 | R7C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_18_s6/F |
| 9.818 | 0.385 | tNET | RR | 1 | R7C17[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_2_s0/I2 |
| 10.334 | 0.516 | tINS | RR | 1 | R7C17[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_2_s0/F |
| 10.491 | 0.157 | tNET | RR | 1 | R7C18[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_2_s/I1 |
| 10.906 | 0.415 | tINS | RR | 2 | R7C18[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_2_s/F |
| 13.896 | 2.990 | tNET | RR | 1 | R8C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.010 | 1.327 | tNET | RR | 1 | R8C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/CLK |
| 21.946 | -0.064 | tSu | 1 | R8C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.494, 29.316%; route: 8.041, 67.474%; tC2Q: 0.382, 3.210% |
| Required Clock Path Delay | cell: 0.683, 33.961%; route: 1.327, 66.040% |
Path5
Path Summary:
| Slack | 8.062 |
| Data Arrival Time | 13.894 |
| Data Required Time | 21.955 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_17_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.006 | 0.563 | tNET | RR | 1 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/I2 |
| 8.523 | 0.516 | tINS | RR | 2 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/F |
| 9.063 | 0.540 | tNET | RR | 1 | R5C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s8/I1 |
| 9.589 | 0.526 | tINS | RR | 2 | R5C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s8/F |
| 9.749 | 0.160 | tNET | RR | 1 | R5C15[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s0/I0 |
| 10.275 | 0.526 | tINS | RR | 1 | R5C15[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s0/F |
| 10.277 | 0.003 | tNET | RR | 1 | R5C15[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s/I0 |
| 10.542 | 0.265 | tINS | RR | 2 | R5C15[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s/F |
| 13.894 | 3.351 | tNET | RR | 1 | R8C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.019 | 1.337 | tNET | RR | 1 | R8C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_17_s0/CLK |
| 21.955 | -0.064 | tSu | 1 | R8C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_17_s0 |
Path Statistics:
| Clock Skew | 0.040 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.645, 30.592%; route: 7.888, 66.198%; tC2Q: 0.382, 3.210% |
| Required Clock Path Delay | cell: 0.683, 33.803%; route: 1.337, 66.197% |
Path6
Path Summary:
| Slack | 8.093 |
| Data Arrival Time | 13.844 |
| Data Required Time | 21.937 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.006 | 0.563 | tNET | RR | 1 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/I2 |
| 8.523 | 0.516 | tINS | RR | 2 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/F |
| 9.063 | 0.540 | tNET | RR | 1 | R5C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s8/I1 |
| 9.589 | 0.526 | tINS | RR | 2 | R5C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_15_s8/F |
| 9.939 | 0.350 | tNET | RR | 1 | R5C14[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_7_s1/I1 |
| 10.460 | 0.521 | tINS | RR | 1 | R5C14[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_7_s1/F |
| 10.462 | 0.003 | tNET | RR | 1 | R5C14[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_7_s/I1 |
| 10.877 | 0.415 | tINS | RR | 2 | R5C14[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_7_s/F |
| 13.844 | 2.966 | tNET | RR | 1 | R8C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.000 | 1.318 | tNET | RR | 1 | R8C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0/CLK |
| 21.937 | -0.064 | tSu | 1 | R8C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_9_s0 |
Path Statistics:
| Clock Skew | 0.022 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.790, 31.943%; route: 7.693, 64.834%; tC2Q: 0.382, 3.224% |
| Required Clock Path Delay | cell: 0.683, 34.120%; route: 1.318, 65.880% |
Path7
Path Summary:
| Slack | 8.130 |
| Data Arrival Time | 13.816 |
| Data Required Time | 21.946 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.214 | 0.770 | tNET | RR | 1 | R8C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s12/I2 |
| 8.711 | 0.498 | tINS | RR | 2 | R8C16[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s12/F |
| 9.421 | 0.710 | tNET | RR | 1 | R6C15[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s17/I1 |
| 9.684 | 0.262 | tINS | RR | 2 | R6C15[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s17/F |
| 9.844 | 0.160 | tNET | RR | 1 | R6C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s1/I0 |
| 10.370 | 0.526 | tINS | RR | 1 | R6C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s1/F |
| 10.718 | 0.347 | tNET | RR | 1 | R7C15[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s/I1 |
| 11.179 | 0.461 | tINS | RR | 2 | R7C15[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s/F |
| 13.816 | 2.638 | tNET | RR | 1 | R8C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.010 | 1.327 | tNET | RR | 1 | R8C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0/CLK |
| 21.946 | -0.064 | tSu | 1 | R8C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_22_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.559, 30.063%; route: 7.896, 66.705%; tC2Q: 0.382, 3.231% |
| Required Clock Path Delay | cell: 0.683, 33.961%; route: 1.327, 66.040% |
Path8
Path Summary:
| Slack | 8.206 |
| Data Arrival Time | 13.742 |
| Data Required Time | 21.948 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.551 | 1.107 | tNET | RR | 1 | R9C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s10/I2 |
| 8.814 | 0.262 | tINS | RR | 3 | R9C16[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_20_s10/F |
| 8.976 | 0.162 | tNET | RR | 1 | R8C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s7/I0 |
| 9.438 | 0.461 | tINS | RR | 3 | R8C16[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_16_s7/F |
| 9.788 | 0.350 | tNET | RR | 1 | R7C17[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_0_s0/I0 |
| 10.314 | 0.526 | tINS | RR | 1 | R7C17[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_0_s0/F |
| 10.661 | 0.347 | tNET | RR | 1 | R8C18[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_0_s/I0 |
| 11.159 | 0.498 | tINS | RR | 2 | R8C18[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_0_s/F |
| 13.743 | 2.584 | tNET | RR | 1 | R9C61[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.012 | 1.329 | tNET | RR | 1 | R9C61[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK |
| 21.948 | -0.064 | tSu | 1 | R9C61[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0 |
Path Statistics:
| Clock Skew | 0.033 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.559, 30.252%; route: 7.822, 66.497%; tC2Q: 0.382, 3.252% |
| Required Clock Path Delay | cell: 0.683, 33.924%; route: 1.329, 66.076% |
Path9
Path Summary:
| Slack | 8.340 |
| Data Arrival Time | 13.592 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_49_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 10.103 | 0.522 | tNET | RR | 1 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/I1 |
| 10.365 | 0.262 | tINS | RR | 3 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/F |
| 11.103 | 0.737 | tNET | RR | 2 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/I0 |
| 11.659 | 0.556 | tINS | RF | 1 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/COUT |
| 11.659 | 0.000 | tNET | FF | 2 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/CIN |
| 11.709 | 0.050 | tINS | FR | 1 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/COUT |
| 11.709 | 0.000 | tNET | RR | 2 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/CIN |
| 11.759 | 0.050 | tINS | RR | 1 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/COUT |
| 11.759 | 0.000 | tNET | RR | 2 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/CIN |
| 12.055 | 0.296 | tINS | RR | 1 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/SUM |
| 12.753 | 0.697 | tNET | RR | 2 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/I1 |
| 13.245 | 0.493 | tINS | RR | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/COUT |
| 13.245 | 0.000 | tNET | RR | 2 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s2/CIN |
| 13.295 | 0.050 | tINS | RR | 1 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s2/COUT |
| 13.295 | 0.000 | tNET | RR | 2 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s2/CIN |
| 13.592 | 0.296 | tINS | RR | 1 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s2/SUM |
| 13.592 | 0.000 | tNET | RR | 1 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_49_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_49_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_49_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.431, 46.836%; route: 3.905, 33.675%; tC2Q: 2.260, 19.489% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path10
Path Summary:
| Slack | 8.352 |
| Data Arrival Time | 13.589 |
| Data Required Time | 21.941 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_50_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 10.103 | 0.522 | tNET | RR | 1 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/I1 |
| 10.365 | 0.262 | tINS | RR | 3 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/F |
| 11.103 | 0.737 | tNET | RR | 2 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/I0 |
| 11.659 | 0.556 | tINS | RF | 1 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/COUT |
| 11.659 | 0.000 | tNET | FF | 2 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/CIN |
| 11.709 | 0.050 | tINS | FR | 1 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/COUT |
| 11.709 | 0.000 | tNET | RR | 2 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/CIN |
| 11.759 | 0.050 | tINS | RR | 1 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/COUT |
| 11.759 | 0.000 | tNET | RR | 2 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/CIN |
| 11.809 | 0.050 | tINS | RR | 1 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/COUT |
| 11.809 | 0.000 | tNET | RR | 2 | R18C19[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s1/CIN |
| 11.859 | 0.050 | tINS | RR | 1 | R18C19[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s1/COUT |
| 11.859 | 0.000 | tNET | RR | 2 | R18C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s1/CIN |
| 12.155 | 0.296 | tINS | RR | 1 | R18C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s1/SUM |
| 12.853 | 0.697 | tNET | RR | 2 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s2/I1 |
| 13.345 | 0.493 | tINS | RR | 1 | R18C24[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n163_s2/COUT |
| 13.345 | 0.000 | tNET | RR | 2 | R18C25[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n162_s2/CIN |
| 13.589 | 0.244 | tINS | RR | 1 | R18C25[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n162_s2/SUM |
| 13.589 | 0.000 | tNET | RR | 1 | R18C25[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_50_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.004 | 1.322 | tNET | RR | 1 | R18C25[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_50_s0/CLK |
| 21.941 | -0.064 | tSu | 1 | R18C25[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_50_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.429, 46.825%; route: 3.905, 33.682%; tC2Q: 2.260, 19.493% |
| Required Clock Path Delay | cell: 0.683, 34.051%; route: 1.322, 65.949% |
Path11
Path Summary:
| Slack | 8.436 |
| Data Arrival Time | 13.510 |
| Data Required Time | 21.946 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 7.118 | 1.010 | tNET | RR | 1 | R6C18[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s9/I3 |
| 7.644 | 0.526 | tINS | RR | 38 | R6C18[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s9/F |
| 7.806 | 0.162 | tNET | RR | 1 | R7C18[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s6/I1 |
| 8.096 | 0.290 | tINS | RF | 31 | R7C18[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s6/F |
| 8.731 | 0.635 | tNET | FF | 1 | R6C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s7/I2 |
| 9.021 | 0.290 | tINS | FF | 2 | R6C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s7/F |
| 9.169 | 0.147 | tNET | FF | 1 | R6C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_1_s0/I2 |
| 9.630 | 0.461 | tINS | FR | 1 | R6C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_1_s0/F |
| 10.038 | 0.407 | tNET | RR | 1 | R6C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_1_s/I1 |
| 10.554 | 0.516 | tINS | RR | 2 | R6C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_1_s/F |
| 13.510 | 2.956 | tNET | RR | 1 | R8C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.010 | 1.327 | tNET | RR | 1 | R8C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK |
| 21.946 | -0.064 | tSu | 1 | R8C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0 |
Path Statistics:
| Clock Skew | 0.031 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.379, 29.301%; route: 7.770, 67.382%; tC2Q: 0.382, 3.317% |
| Required Clock Path Delay | cell: 0.683, 33.961%; route: 1.327, 66.040% |
Path12
Path Summary:
| Slack | 8.442 |
| Data Arrival Time | 13.489 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_48_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 10.103 | 0.522 | tNET | RR | 1 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/I1 |
| 10.365 | 0.262 | tINS | RR | 3 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/F |
| 11.103 | 0.737 | tNET | RR | 2 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/I0 |
| 11.659 | 0.556 | tINS | RF | 1 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/COUT |
| 11.659 | 0.000 | tNET | FF | 2 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/CIN |
| 11.709 | 0.050 | tINS | FR | 1 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/COUT |
| 11.709 | 0.000 | tNET | RR | 2 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/CIN |
| 11.759 | 0.050 | tINS | RR | 1 | R18C19[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s1/COUT |
| 11.759 | 0.000 | tNET | RR | 2 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/CIN |
| 12.055 | 0.296 | tINS | RR | 1 | R18C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s1/SUM |
| 12.753 | 0.697 | tNET | RR | 2 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/I1 |
| 13.245 | 0.493 | tINS | RR | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/COUT |
| 13.245 | 0.000 | tNET | RR | 2 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s2/CIN |
| 13.489 | 0.244 | tINS | RR | 1 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n164_s2/SUM |
| 13.489 | 0.000 | tNET | RR | 1 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_48_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_48_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_48_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.329, 46.362%; route: 3.905, 33.975%; tC2Q: 2.260, 19.663% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path13
Path Summary:
| Slack | 8.449 |
| Data Arrival Time | 13.511 |
| Data Required Time | 21.961 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.006 | 0.563 | tNET | RR | 1 | R7C17[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_21_s10/I2 |
| 8.523 | 0.516 | tINS | RR | 2 | R7C17[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_21_s10/F |
| 8.682 | 0.160 | tNET | RR | 1 | R6C17[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s6/I0 |
| 9.180 | 0.498 | tINS | RR | 3 | R6C17[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s6/F |
| 9.858 | 0.677 | tNET | RR | 1 | R5C15[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_9_s0/I0 |
| 10.374 | 0.516 | tINS | RR | 1 | R5C15[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_9_s0/F |
| 10.756 | 0.382 | tNET | RR | 1 | R5C18[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_9_s/I0 |
| 11.217 | 0.461 | tINS | RR | 2 | R5C18[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_9_s/F |
| 13.511 | 2.294 | tNET | RR | 1 | R4C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.024 | 1.342 | tNET | RR | 1 | R4C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0/CLK |
| 21.961 | -0.064 | tSu | 1 | R4C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_11_s0 |
Path Statistics:
| Clock Skew | 0.046 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.803, 32.972%; route: 7.348, 63.711%; tC2Q: 0.382, 3.317% |
| Required Clock Path Delay | cell: 0.683, 33.714%; route: 1.342, 66.286% |
Path14
Path Summary:
| Slack | 8.457 |
| Data Arrival Time | 13.474 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_47_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 10.103 | 0.522 | tNET | RR | 1 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/I1 |
| 10.365 | 0.262 | tINS | RR | 3 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/F |
| 11.103 | 0.737 | tNET | RR | 2 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/I0 |
| 11.659 | 0.556 | tINS | RF | 1 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/COUT |
| 11.659 | 0.000 | tNET | FF | 2 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/CIN |
| 11.955 | 0.296 | tINS | FR | 1 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/SUM |
| 12.635 | 0.680 | tNET | RR | 2 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/I1 |
| 13.128 | 0.493 | tINS | RR | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/COUT |
| 13.128 | 0.000 | tNET | RR | 2 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s2/CIN |
| 13.178 | 0.050 | tINS | RR | 1 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s2/COUT |
| 13.178 | 0.000 | tNET | RR | 2 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/CIN |
| 13.474 | 0.296 | tINS | RR | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n165_s2/SUM |
| 13.474 | 0.000 | tNET | RR | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_47_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_47_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_47_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.331, 46.445%; route: 3.888, 33.867%; tC2Q: 2.260, 19.689% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path15
Path Summary:
| Slack | 8.509 |
| Data Arrival Time | 13.413 |
| Data Required Time | 21.922 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_50_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 9.720 | 0.140 | tNET | RR | 1 | R17C26[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_45_s1/I1 |
| 10.247 | 0.526 | tINS | RR | 3 | R17C26[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_45_s1/F |
| 10.958 | 0.711 | tNET | RR | 2 | R17C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n373_s/I1 |
| 11.450 | 0.493 | tINS | RR | 1 | R17C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n373_s/COUT |
| 11.450 | 0.000 | tNET | RR | 2 | R17C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n372_s/CIN |
| 11.500 | 0.050 | tINS | RR | 1 | R17C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n372_s/COUT |
| 11.500 | 0.000 | tNET | RR | 2 | R17C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s/CIN |
| 11.550 | 0.050 | tINS | RR | 1 | R17C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s/COUT |
| 11.550 | 0.000 | tNET | RR | 2 | R17C21[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n370_s/CIN |
| 11.600 | 0.050 | tINS | RR | 1 | R17C21[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n370_s/COUT |
| 11.600 | 0.000 | tNET | RR | 2 | R17C21[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s/CIN |
| 11.897 | 0.296 | tINS | RR | 1 | R17C21[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s/SUM |
| 12.677 | 0.780 | tNET | RR | 2 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s0/I1 |
| 13.169 | 0.493 | tINS | RR | 1 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s0/COUT |
| 13.169 | 0.000 | tNET | RR | 2 | R18C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n368_s0/CIN |
| 13.413 | 0.244 | tINS | RR | 1 | R18C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n368_s0/SUM |
| 13.413 | 0.000 | tNET | RR | 1 | R18C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_50_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.986 | 1.303 | tNET | RR | 1 | R18C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_50_s0/CLK |
| 21.922 | -0.064 | tSu | 1 | R18C15[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_50_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.579, 48.861%; route: 3.579, 31.344%; tC2Q: 2.260, 19.794% |
| Required Clock Path Delay | cell: 0.683, 34.372%; route: 1.303, 65.628% |
Path16
Path Summary:
| Slack | 8.518 |
| Data Arrival Time | 13.421 |
| Data Required Time | 21.939 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.006 | 0.563 | tNET | RR | 1 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/I2 |
| 8.523 | 0.516 | tINS | RR | 2 | R7C17[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s7/F |
| 8.873 | 0.350 | tNET | RR | 1 | R5C17[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s15/I0 |
| 9.399 | 0.526 | tINS | RR | 3 | R5C17[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_19_s15/F |
| 9.561 | 0.162 | tNET | RR | 1 | R6C17[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_3_s0/I1 |
| 10.078 | 0.516 | tINS | RR | 1 | R6C17[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_3_s0/F |
| 10.235 | 0.157 | tNET | RR | 1 | R7C17[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_3_s/I0 |
| 10.498 | 0.262 | tINS | RR | 2 | R7C17[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_3_s/F |
| 13.421 | 2.924 | tNET | RR | 1 | R9C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.003 | 1.320 | tNET | RR | 1 | R9C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0/CLK |
| 21.939 | -0.064 | tSu | 1 | R9C60[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_5_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.633, 31.746%; route: 7.427, 64.912%; tC2Q: 0.382, 3.343% |
| Required Clock Path Delay | cell: 0.683, 34.082%; route: 1.320, 65.918% |
Path17
Path Summary:
| Slack | 8.519 |
| Data Arrival Time | 13.434 |
| Data Required Time | 21.953 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_19_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 7.999 | 0.555 | tNET | RR | 1 | R5C17[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_21_s12/I2 |
| 8.515 | 0.516 | tINS | RR | 2 | R5C17[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_21_s12/F |
| 8.710 | 0.195 | tNET | RR | 1 | R5C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s9/I0 |
| 9.226 | 0.516 | tINS | RR | 2 | R5C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s9/F |
| 9.386 | 0.160 | tNET | RR | 1 | R6C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s0/I0 |
| 9.902 | 0.516 | tINS | RR | 1 | R6C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s0/F |
| 9.905 | 0.003 | tNET | RR | 1 | R6C15[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s/I0 |
| 10.431 | 0.526 | tINS | RR | 2 | R6C15[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_17_s/F |
| 13.434 | 3.003 | tNET | RR | 1 | R7C60[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_19_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.017 | 1.334 | tNET | RR | 1 | R7C60[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_19_s0/CLK |
| 21.953 | -0.064 | tSu | 1 | R7C60[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_19_s0 |
Path Statistics:
| Clock Skew | 0.038 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.886, 33.926%; route: 7.186, 62.735%; tC2Q: 0.382, 3.339% |
| Required Clock Path Delay | cell: 0.683, 33.839%; route: 1.334, 66.161% |
Path18
Path Summary:
| Slack | 8.523 |
| Data Arrival Time | 13.414 |
| Data Required Time | 21.937 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.416 | 0.973 | tNET | RR | 1 | R9C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s12/I2 |
| 8.932 | 0.516 | tINS | RR | 2 | R9C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s12/F |
| 9.092 | 0.160 | tNET | RR | 1 | R8C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s39/I1 |
| 9.609 | 0.516 | tINS | RR | 3 | R8C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s39/F |
| 9.771 | 0.162 | tNET | RR | 1 | R7C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_6_s0/I0 |
| 10.287 | 0.516 | tINS | RR | 1 | R7C16[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_6_s0/F |
| 10.445 | 0.157 | tNET | RR | 1 | R8C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_6_s/I0 |
| 10.966 | 0.521 | tINS | RR | 2 | R8C16[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_6_s/F |
| 13.414 | 2.448 | tNET | RR | 1 | R8C59[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.000 | 1.318 | tNET | RR | 1 | R8C59[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0/CLK |
| 21.937 | -0.064 | tSu | 1 | R8C59[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_8_s0 |
Path Statistics:
| Clock Skew | 0.022 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.881, 33.942%; route: 7.171, 62.713%; tC2Q: 0.382, 3.345% |
| Required Clock Path Delay | cell: 0.683, 34.120%; route: 1.318, 65.880% |
Path19
Path Summary:
| Slack | 8.560 |
| Data Arrival Time | 13.372 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_46_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 10.103 | 0.522 | tNET | RR | 1 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/I1 |
| 10.365 | 0.262 | tINS | RR | 3 | R17C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_44_s1/F |
| 11.103 | 0.737 | tNET | RR | 2 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/I0 |
| 11.659 | 0.556 | tINS | RF | 1 | R18C19[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s1/COUT |
| 11.659 | 0.000 | tNET | FF | 2 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/CIN |
| 11.955 | 0.296 | tINS | FR | 1 | R18C19[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s1/SUM |
| 12.635 | 0.680 | tNET | RR | 2 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/I1 |
| 13.128 | 0.493 | tINS | RR | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/COUT |
| 13.128 | 0.000 | tNET | RR | 2 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s2/CIN |
| 13.372 | 0.244 | tINS | RR | 1 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n166_s2/SUM |
| 13.372 | 0.000 | tNET | RR | 1 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_46_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_46_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_46_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.229, 45.962%; route: 3.888, 34.172%; tC2Q: 2.260, 19.866% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path20
Path Summary:
| Slack | 8.613 |
| Data Arrival Time | 13.350 |
| Data Required Time | 21.962 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.979 | 1.296 | tNET | RR | 1 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/CLK |
| 2.361 | 0.382 | tC2Q | RR | 4 | R11C19[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_29_s0/Q |
| 3.579 | 1.218 | tNET | RR | 1 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/I2 |
| 4.095 | 0.516 | tINS | RR | 7 | R9C14[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s2/F |
| 4.809 | 0.714 | tNET | RR | 1 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/I0 |
| 5.325 | 0.516 | tINS | RR | 3 | R9C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_30_s0/F |
| 5.845 | 0.520 | tNET | RR | 1 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/I2 |
| 6.108 | 0.262 | tINS | RR | 3 | R9C15[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_24_s1/F |
| 6.928 | 0.820 | tNET | RR | 1 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/I3 |
| 7.444 | 0.516 | tINS | RR | 34 | R6C19[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s21/F |
| 8.351 | 0.907 | tNET | RR | 1 | R8C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s11/I2 |
| 8.868 | 0.516 | tINS | RR | 2 | R8C16[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_22_s11/F |
| 9.028 | 0.160 | tNET | RR | 1 | R8C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_18_s9/I1 |
| 9.525 | 0.498 | tINS | RR | 2 | R8C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_18_s9/F |
| 9.875 | 0.350 | tNET | RR | 1 | R7C14[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_10_s0/I1 |
| 10.396 | 0.521 | tINS | RR | 1 | R7C14[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_10_s0/F |
| 10.399 | 0.003 | tNET | RR | 1 | R7C14[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_10_s/I0 |
| 10.860 | 0.461 | tINS | RR | 2 | R7C14[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/result_d_10_s/F |
| 13.350 | 2.490 | tNET | RR | 1 | R7C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.026 | 1.344 | tNET | RR | 1 | R7C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0/CLK |
| 21.962 | -0.064 | tSu | 1 | R7C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_12_s0 |
Path Statistics:
| Clock Skew | 0.047 |
| Setup Relationship | 20.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
| Arrival Data Path Delay | cell: 3.808, 33.484%; route: 7.181, 63.153%; tC2Q: 0.382, 3.364% |
| Required Clock Path Delay | cell: 0.683, 33.683%; route: 1.344, 66.317% |
Path21
Path Summary:
| Slack | 8.618 |
| Data Arrival Time | 13.313 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_45_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.680 | 0.162 | tNET | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/I1 |
| 9.197 | 0.516 | tINS | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/F |
| 9.199 | 0.003 | tNET | RR | 1 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/I1 |
| 9.660 | 0.461 | tINS | RR | 3 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/F |
| 10.875 | 1.215 | tNET | RR | 2 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/I0 |
| 11.607 | 0.731 | tINS | RR | 1 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/SUM |
| 12.304 | 0.697 | tNET | RR | 2 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/I0 |
| 12.867 | 0.563 | tINS | RF | 1 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/COUT |
| 12.867 | 0.000 | tNET | FF | 2 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/CIN |
| 12.917 | 0.050 | tINS | FR | 1 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/COUT |
| 12.917 | 0.000 | tNET | RR | 2 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/CIN |
| 12.967 | 0.050 | tINS | RR | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/COUT |
| 12.967 | 0.000 | tNET | RR | 2 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s2/CIN |
| 13.017 | 0.050 | tINS | RR | 1 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s2/COUT |
| 13.017 | 0.000 | tNET | RR | 2 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/CIN |
| 13.313 | 0.296 | tINS | RR | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n167_s2/SUM |
| 13.313 | 0.000 | tNET | RR | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_45_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_45_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_45_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 12 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.043, 44.555%; route: 4.015, 35.476%; tC2Q: 2.260, 19.969% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path22
Path Summary:
| Slack | 8.651 |
| Data Arrival Time | 13.280 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_49_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.523 | 0.005 | tNET | RR | 1 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/I3 |
| 9.049 | 0.526 | tINS | RR | 4 | R17C26[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_42_s2/F |
| 9.054 | 0.005 | tNET | RR | 1 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/I1 |
| 9.580 | 0.526 | tINS | RR | 3 | R17C26[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_46_s3/F |
| 9.720 | 0.140 | tNET | RR | 1 | R17C26[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_45_s1/I1 |
| 10.247 | 0.526 | tINS | RR | 3 | R17C26[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_45_s1/F |
| 10.958 | 0.711 | tNET | RR | 2 | R17C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n373_s/I1 |
| 11.450 | 0.493 | tINS | RR | 1 | R17C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n373_s/COUT |
| 11.450 | 0.000 | tNET | RR | 2 | R17C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n372_s/CIN |
| 11.500 | 0.050 | tINS | RR | 1 | R17C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n372_s/COUT |
| 11.500 | 0.000 | tNET | RR | 2 | R17C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s/CIN |
| 11.797 | 0.296 | tINS | RR | 1 | R17C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s/SUM |
| 12.442 | 0.645 | tNET | RR | 2 | R18C14[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s0/I1 |
| 12.934 | 0.493 | tINS | RR | 1 | R18C14[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n371_s0/COUT |
| 12.934 | 0.000 | tNET | RR | 2 | R18C14[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n370_s0/CIN |
| 12.984 | 0.050 | tINS | RR | 1 | R18C14[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n370_s0/COUT |
| 12.984 | 0.000 | tNET | RR | 2 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s0/CIN |
| 13.280 | 0.296 | tINS | RR | 1 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n369_s0/SUM |
| 13.280 | 0.000 | tNET | RR | 1 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_49_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_49_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C14[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_y_out_49_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 5.581, 49.457%; route: 3.444, 30.516%; tC2Q: 2.260, 20.027% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Path23
Path Summary:
| Slack | 8.709 |
| Data Arrival Time | 13.213 |
| Data Required Time | 21.922 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_43_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.680 | 0.162 | tNET | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/I1 |
| 9.197 | 0.516 | tINS | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/F |
| 9.199 | 0.003 | tNET | RR | 1 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/I1 |
| 9.660 | 0.461 | tINS | RR | 3 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/F |
| 10.875 | 1.215 | tNET | RR | 2 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/I0 |
| 11.607 | 0.731 | tINS | RR | 1 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/SUM |
| 12.304 | 0.697 | tNET | RR | 2 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/I0 |
| 12.867 | 0.563 | tINS | RF | 1 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/COUT |
| 12.867 | 0.000 | tNET | FF | 2 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/CIN |
| 12.917 | 0.050 | tINS | FR | 1 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/COUT |
| 12.917 | 0.000 | tNET | RR | 2 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/CIN |
| 13.213 | 0.296 | tINS | RR | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/SUM |
| 13.213 | 0.000 | tNET | RR | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_43_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.986 | 1.303 | tNET | RR | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_43_s0/CLK |
| 21.922 | -0.064 | tSu | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_43_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Setup Relationship | 20.000 |
| Logic Level | 12 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 4.943, 44.061%; route: 4.015, 35.792%; tC2Q: 2.260, 20.147% |
| Required Clock Path Delay | cell: 0.683, 34.372%; route: 1.303, 65.628% |
Path24
Path Summary:
| Slack | 8.719 |
| Data Arrival Time | 13.196 |
| Data Required Time | 21.915 |
| From | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[29].Iteration_pos_inst/data_r_out_2_s0 |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 2.031 | 1.349 | tNET | RR | 1 | R5C29[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[29].Iteration_pos_inst/data_r_out_2_s0/CLK |
| 2.414 | 0.382 | tC2Q | RR | 1 | R5C29[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[29].Iteration_pos_inst/data_r_out_2_s0/Q |
| 3.662 | 1.249 | tNET | RR | 2 | R11C20[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/add_1226_s2/I0 |
| 4.225 | 0.563 | tINS | RF | 1 | R11C20[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/add_1226_s2/COUT |
| 4.225 | 0.000 | tNET | FF | 2 | R11C20[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/add_1226_s3/CIN |
| 4.275 | 0.050 | tINS | FR | 1 | R11C20[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/add_1226_s3/COUT |
| 4.275 | 0.000 | tNET | RR | 2 | R11C20[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_0_s/CIN |
| 4.325 | 0.050 | tINS | RR | 1 | R11C20[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_0_s/COUT |
| 4.325 | 0.000 | tNET | RR | 2 | R11C20[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_1_s/CIN |
| 4.375 | 0.050 | tINS | RR | 1 | R11C20[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_1_s/COUT |
| 4.375 | 0.000 | tNET | RR | 2 | R11C20[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_2_s/CIN |
| 4.425 | 0.050 | tINS | RR | 1 | R11C20[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_2_s/COUT |
| 4.425 | 0.000 | tNET | RR | 2 | R11C20[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_3_s/CIN |
| 4.475 | 0.050 | tINS | RR | 1 | R11C20[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_3_s/COUT |
| 4.475 | 0.000 | tNET | RR | 2 | R11C21[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_4_s/CIN |
| 4.525 | 0.050 | tINS | RR | 1 | R11C21[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_4_s/COUT |
| 4.525 | 0.000 | tNET | RR | 2 | R11C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_5_s/CIN |
| 4.575 | 0.050 | tINS | RR | 1 | R11C21[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_5_s/COUT |
| 4.575 | 0.000 | tNET | RR | 2 | R11C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_6_s/CIN |
| 4.625 | 0.050 | tINS | RR | 1 | R11C21[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_6_s/COUT |
| 4.625 | 0.000 | tNET | RR | 2 | R11C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_7_s/CIN |
| 4.675 | 0.050 | tINS | RR | 1 | R11C21[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_7_s/COUT |
| 4.675 | 0.000 | tNET | RR | 2 | R11C21[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_8_s/CIN |
| 4.725 | 0.050 | tINS | RR | 1 | R11C21[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_8_s/COUT |
| 4.725 | 0.000 | tNET | RR | 2 | R11C21[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_9_s/CIN |
| 4.775 | 0.050 | tINS | RR | 1 | R11C21[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_9_s/COUT |
| 4.775 | 0.000 | tNET | RR | 2 | R11C22[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_10_s/CIN |
| 4.825 | 0.050 | tINS | RR | 1 | R11C22[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_10_s/COUT |
| 4.825 | 0.000 | tNET | RR | 2 | R11C22[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_11_s/CIN |
| 4.875 | 0.050 | tINS | RR | 1 | R11C22[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_11_s/COUT |
| 4.875 | 0.000 | tNET | RR | 2 | R11C22[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_12_s/CIN |
| 4.925 | 0.050 | tINS | RR | 1 | R11C22[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_12_s/COUT |
| 4.925 | 0.000 | tNET | RR | 2 | R11C22[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_13_s/CIN |
| 4.975 | 0.050 | tINS | RR | 1 | R11C22[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_13_s/COUT |
| 4.975 | 0.000 | tNET | RR | 2 | R11C22[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_14_s/CIN |
| 5.025 | 0.050 | tINS | RR | 1 | R11C22[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_14_s/COUT |
| 5.025 | 0.000 | tNET | RR | 2 | R11C22[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_15_s/CIN |
| 5.075 | 0.050 | tINS | RR | 1 | R11C22[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_15_s/COUT |
| 5.075 | 0.000 | tNET | RR | 2 | R11C23[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_16_s/CIN |
| 5.125 | 0.050 | tINS | RR | 1 | R11C23[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_16_s/COUT |
| 5.125 | 0.000 | tNET | RR | 2 | R11C23[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_17_s/CIN |
| 5.175 | 0.050 | tINS | RR | 1 | R11C23[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_17_s/COUT |
| 5.175 | 0.000 | tNET | RR | 2 | R11C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_18_s/CIN |
| 5.225 | 0.050 | tINS | RR | 1 | R11C23[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_18_s/COUT |
| 5.225 | 0.000 | tNET | RR | 2 | R11C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_19_s/CIN |
| 5.275 | 0.050 | tINS | RR | 1 | R11C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_19_s/COUT |
| 5.275 | 0.000 | tNET | RR | 2 | R11C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_20_s/CIN |
| 5.325 | 0.050 | tINS | RR | 1 | R11C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_20_s/COUT |
| 5.325 | 0.000 | tNET | RR | 2 | R11C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_21_s/CIN |
| 5.375 | 0.050 | tINS | RR | 1 | R11C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_21_s/COUT |
| 5.375 | 0.000 | tNET | RR | 2 | R11C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_22_s/CIN |
| 5.425 | 0.050 | tINS | RR | 1 | R11C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_22_s/COUT |
| 5.425 | 0.000 | tNET | RR | 2 | R11C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_23_s/CIN |
| 5.475 | 0.050 | tINS | RR | 1 | R11C24[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_23_s/COUT |
| 5.475 | 0.000 | tNET | RR | 2 | R11C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_24_s/CIN |
| 5.719 | 0.244 | tINS | RR | 1 | R11C24[1][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_mantissa_in_24_s/SUM |
| 6.753 | 1.034 | tNET | RR | 32 | DSP_R19[6] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/C[24] |
| 6.983 | 0.230 | tINS | RR | 4 | DSP_R19[6] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/DOUT[1] |
| 8.483 | 1.500 | tNET | RR | 1 | R11C20[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/I2 |
| 9.004 | 0.521 | tINS | RR | 4 | R11C20[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n131_s2/F |
| 9.419 | 0.415 | tNET | RR | 1 | R11C16[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/I1 |
| 9.945 | 0.526 | tINS | RR | 4 | R11C16[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n128_s6/F |
| 10.105 | 0.160 | tNET | RR | 1 | R11C17[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/I1 |
| 10.566 | 0.461 | tINS | RR | 4 | R11C17[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n125_s6/F |
| 10.576 | 0.010 | tNET | RR | 1 | R11C17[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/I1 |
| 11.074 | 0.498 | tINS | RR | 9 | R11C17[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n122_s6/F |
| 11.439 | 0.365 | tNET | RR | 1 | R11C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/I0 |
| 11.729 | 0.290 | tINS | RF | 3 | R11C15[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n112_s2/F |
| 12.115 | 0.386 | tNET | FF | 1 | R11C19[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/I2 |
| 12.530 | 0.415 | tINS | FR | 4 | R11C19[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s2/F |
| 12.675 | 0.145 | tNET | RR | 1 | R11C19[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s1/I0 |
| 13.196 | 0.521 | tINS | RR | 1 | R11C19[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/n107_s1/F |
| 13.196 | 0.000 | tNET | RR | 1 | R11C19[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.979 | 1.296 | tNET | RR | 1 | R11C19[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0/CLK |
| 21.915 | -0.064 | tSu | 1 | R11C19[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/Fixed_to_Float_inst/tempfixed_30_s0 |
Path Statistics:
| Clock Skew | -0.053 |
| Setup Relationship | 20.000 |
| Logic Level | 13 |
| Arrival Clock Path Delay | cell: 0.683, 33.600%; route: 1.349, 66.400% |
| Arrival Data Path Delay | cell: 5.519, 49.429%; route: 5.264, 47.145%; tC2Q: 0.382, 3.426% |
| Required Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
Path25
Path Summary:
| Slack | 8.721 |
| Data Arrival Time | 13.210 |
| Data Required Time | 21.931 |
| From | mem_data_in_mem_data_in_0_0_s |
| To | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_44_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | 32 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/CLK |
| 4.255 | 2.260 | tC2Q | RR | 14 | BSRAM_R10[10] | mem_data_in_mem_data_in_0_0_s/DO[0] |
| 6.005 | 1.750 | tNET | RR | 1 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/I0 |
| 6.532 | 0.526 | tINS | RR | 6 | R17C27[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n34_s4/F |
| 6.542 | 0.010 | tNET | RR | 1 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/I3 |
| 7.068 | 0.526 | tINS | RR | 5 | R17C27[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/n31_s4/F |
| 7.230 | 0.162 | tNET | RR | 1 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/I1 |
| 7.520 | 0.290 | tINS | RF | 3 | R17C26[3][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_35_s3/F |
| 7.530 | 0.010 | tNET | FF | 1 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/I1 |
| 7.992 | 0.461 | tINS | FR | 3 | R17C26[0][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_38_s2/F |
| 7.997 | 0.005 | tNET | RR | 1 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/I1 |
| 8.518 | 0.521 | tINS | RR | 4 | R17C26[3][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_39_s3/F |
| 8.680 | 0.162 | tNET | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/I1 |
| 9.197 | 0.516 | tINS | RR | 1 | R17C25[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s2/F |
| 9.199 | 0.003 | tNET | RR | 1 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/I1 |
| 9.660 | 0.461 | tINS | RR | 3 | R17C25[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/data_x_in_41_s1/F |
| 10.875 | 1.215 | tNET | RR | 2 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/I0 |
| 11.607 | 0.731 | tINS | RR | 1 | R18C18[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s1/SUM |
| 12.304 | 0.697 | tNET | RR | 2 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/I0 |
| 12.867 | 0.563 | tINS | RF | 1 | R18C23[1][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n171_s2/COUT |
| 12.867 | 0.000 | tNET | FF | 2 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/CIN |
| 12.917 | 0.050 | tINS | FR | 1 | R18C23[2][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n170_s2/COUT |
| 12.917 | 0.000 | tNET | RR | 2 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/CIN |
| 12.967 | 0.050 | tINS | RR | 1 | R18C23[2][B] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n169_s2/COUT |
| 12.967 | 0.000 | tNET | RR | 2 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s2/CIN |
| 13.210 | 0.244 | tINS | RR | 1 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/n168_s2/SUM |
| 13.210 | 0.000 | tNET | RR | 1 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_44_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.995 | 1.313 | tNET | RR | 1 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_44_s0/CLK |
| 21.931 | -0.064 | tSu | 1 | R18C24[0][A] | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/gen_iteration[0].Iteration_neg_inst/data_x_out_44_s0 |
Path Statistics:
| Clock Skew | -0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 12 |
| Arrival Clock Path Delay | cell: 0.683, 34.205%; route: 1.313, 65.795% |
| Arrival Data Path Delay | cell: 4.940, 44.048%; route: 4.015, 35.800%; tC2Q: 2.260, 20.152% |
| Required Clock Path Delay | cell: 0.683, 34.211%; route: 1.313, 65.789% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.008 |
| Data Arrival Time | 1.418 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.174 | 0.499 | tNET | RR | 1 | R8C57[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK |
| 1.319 | 0.144 | tC2Q | RR | 1 | R8C57[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q |
| 1.418 | 0.099 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.514%; route: 0.499, 42.486% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path2
Path Summary:
| Slack | 0.008 |
| Data Arrival Time | 1.418 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.174 | 0.499 | tNET | RR | 1 | R8C57[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/CLK |
| 1.319 | 0.144 | tC2Q | RR | 1 | R8C57[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q |
| 1.418 | 0.099 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.514%; route: 0.499, 42.486% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.099, 40.741%; tC2Q: 0.144, 59.259% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path3
Path Summary:
| Slack | 0.013 |
| Data Arrival Time | 1.422 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C60[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q |
| 1.422 | 0.101 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.017 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path4
Path Summary:
| Slack | 0.013 |
| Data Arrival Time | 1.422 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C60[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C60[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q |
| 1.422 | 0.101 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.017 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path5
Path Summary:
| Slack | 0.021 |
| Data Arrival Time | 1.426 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_47_s0/Q |
| 1.426 | 0.101 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.025 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path6
Path Summary:
| Slack | 0.083 |
| Data Arrival Time | 1.493 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.174 | 0.499 | tNET | RR | 1 | R8C57[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK |
| 1.319 | 0.144 | tC2Q | RR | 1 | R8C57[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q |
| 1.493 | 0.174 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.514%; route: 0.499, 42.486% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path7
Path Summary:
| Slack | 0.092 |
| Data Arrival Time | 1.501 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C61[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C61[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q |
| 1.501 | 0.176 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.021 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path8
Path Summary:
| Slack | 0.092 |
| Data Arrival Time | 1.501 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_48_s0/Q |
| 1.501 | 0.176 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.021 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path9
Path Summary:
| Slack | 0.094 |
| Data Arrival Time | 1.504 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C56[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q |
| 1.504 | 0.189 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path10
Path Summary:
| Slack | 0.096 |
| Data Arrival Time | 1.501 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C57[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C57[3][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q |
| 1.501 | 0.176 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.025 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.176, 55.000%; tC2Q: 0.144, 45.000% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path11
Path Summary:
| Slack | 0.100 |
| Data Arrival Time | 1.510 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q |
| 1.510 | 0.195 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path12
Path Summary:
| Slack | 0.100 |
| Data Arrival Time | 1.510 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q |
| 1.510 | 0.195 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path13
Path Summary:
| Slack | 0.100 |
| Data Arrival Time | 1.510 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q |
| 1.510 | 0.195 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path14
Path Summary:
| Slack | 0.105 |
| Data Arrival Time | 1.514 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.173 | 0.498 | tNET | RR | 1 | R6C59[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/CLK |
| 1.317 | 0.144 | tC2Q | RR | 1 | R6C59[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q |
| 1.514 | 0.197 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.575%; route: 0.498, 42.425% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path15
Path Summary:
| Slack | 0.107 |
| Data Arrival Time | 1.512 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q |
| 1.512 | 0.191 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.021 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.191, 57.015%; tC2Q: 0.144, 42.985% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path16
Path Summary:
| Slack | 0.117 |
| Data Arrival Time | 1.522 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C57[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C57[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q |
| 1.522 | 0.197 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.025 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.197, 57.771%; tC2Q: 0.144, 42.229% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path17
Path Summary:
| Slack | 0.158 |
| Data Arrival Time | 1.567 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q |
| 1.567 | 0.246 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[19] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Path Statistics:
| Clock Skew | -0.017 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.246, 63.077%; tC2Q: 0.144, 36.923% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path18
Path Summary:
| Slack | 0.159 |
| Data Arrival Time | 1.564 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.183 | 0.508 | tNET | RR | 1 | R5C61[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK |
| 1.327 | 0.144 | tC2Q | RR | 1 | R5C61[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q |
| 1.564 | 0.237 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.027 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.101%; route: 0.508, 42.899% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.237, 62.205%; tC2Q: 0.144, 37.795% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path19
Path Summary:
| Slack | 0.167 |
| Data Arrival Time | 1.580 |
| Data Required Time | 1.413 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.506 | tNET | RR | 1 | R6C57[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/CLK |
| 1.325 | 0.144 | tC2Q | RR | 1 | R6C57[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q |
| 1.580 | 0.255 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.164 | 0.489 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
| 1.413 | 0.249 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
| Clock Skew | -0.017 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.185%; route: 0.506, 42.815% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.255, 63.910%; tC2Q: 0.144, 36.090% |
| Required Clock Path Delay | cell: 0.675, 58.008%; route: 0.489, 41.992% |
Path20
Path Summary:
| Slack | 0.175 |
| Data Arrival Time | 1.585 |
| Data Required Time | 1.410 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C58[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C58[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q |
| 1.585 | 0.270 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.161 | 0.485 | tNET | RR | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 1.410 | 0.249 | tHld | 1 | BSRAM_R10[17] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.270, 65.217%; tC2Q: 0.144, 34.783% |
| Required Clock Path Delay | cell: 0.675, 58.208%; route: 0.485, 41.792% |
Path21
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 1.597 |
| Data Required Time | 1.413 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q |
| 1.597 | 0.276 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.164 | 0.489 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
| 1.413 | 0.249 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
| Clock Skew | -0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.276, 65.714%; tC2Q: 0.144, 34.286% |
| Required Clock Path Delay | cell: 0.675, 58.008%; route: 0.489, 41.992% |
Path22
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 1.597 |
| Data Required Time | 1.413 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R6C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK |
| 1.321 | 0.144 | tC2Q | RR | 1 | R6C58[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q |
| 1.597 | 0.276 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.164 | 0.489 | tNET | RR | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
| 1.413 | 0.249 | tHld | 1 | BSRAM_R10[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Path Statistics:
| Clock Skew | -0.013 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.276, 65.714%; tC2Q: 0.144, 34.286% |
| Required Clock Path Delay | cell: 0.675, 58.008%; route: 0.489, 41.992% |
Path23
Path Summary:
| Slack | 0.194 |
| Data Arrival Time | 1.608 |
| Data Required Time | 1.413 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.169 | 0.494 | tNET | RR | 1 | R9C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK |
| 1.313 | 0.144 | tC2Q | RR | 1 | R9C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q |
| 1.607 | 0.294 | tNET | RR | 1 | BSRAM_R10[16] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.164 | 0.489 | tNET | RR | 1 | BSRAM_R10[16] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 1.413 | 0.249 | tHld | 1 | BSRAM_R10[16] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.760%; route: 0.494, 42.240% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.294, 67.123%; tC2Q: 0.144, 32.877% |
| Required Clock Path Delay | cell: 0.675, 58.008%; route: 0.489, 41.992% |
Path24
Path Summary:
| Slack | 0.200 |
| Data Arrival Time | 1.606 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_35_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C56[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C56[3][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_35_s0/Q |
| 1.606 | 0.291 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Path25
Path Summary:
| Slack | 0.200 |
| Data Arrival Time | 1.606 |
| Data Required Time | 1.405 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.171 | 0.495 | tNET | RR | 1 | R8C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/CLK |
| 1.315 | 0.144 | tC2Q | RR | 1 | R8C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_34_s0/Q |
| 1.606 | 0.291 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.156 | 0.481 | tNET | RR | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 1.405 | 0.249 | tHld | 1 | BSRAM_R10[18] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 57.710%; route: 0.495, 42.290% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.291, 66.897%; tC2Q: 0.144, 33.103% |
| Required Clock Path Delay | cell: 0.675, 58.409%; route: 0.481, 41.591% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 7.427 |
| Data Arrival Time | 14.223 |
| Data Required Time | 21.650 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.223 | 1.748 | tNET | FF | 1 | R11C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.997 | 1.315 | tNET | RR | 1 | R11C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK |
| 21.650 | -0.347 | tSu | 1 | R11C61[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1 |
Path Statistics:
| Clock Skew | -0.035 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.748, 79.800%; tC2Q: 0.442, 20.200% |
| Required Clock Path Delay | cell: 0.683, 34.168%; route: 1.315, 65.832% |
Path2
Path Summary:
| Slack | 7.427 |
| Data Arrival Time | 14.223 |
| Data Required Time | 21.650 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.223 | 1.748 | tNET | FF | 1 | R11C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.997 | 1.315 | tNET | RR | 1 | R11C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
| 21.650 | -0.347 | tSu | 1 | R11C61[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
| Clock Skew | -0.035 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.748, 79.800%; tC2Q: 0.442, 20.200% |
| Required Clock Path Delay | cell: 0.683, 34.168%; route: 1.315, 65.832% |
Path3
Path Summary:
| Slack | 7.427 |
| Data Arrival Time | 14.223 |
| Data Required Time | 21.650 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.223 | 1.748 | tNET | FF | 1 | R11C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.997 | 1.315 | tNET | RR | 1 | R11C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 21.650 | -0.347 | tSu | 1 | R11C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
Path Statistics:
| Clock Skew | -0.035 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.748, 79.800%; tC2Q: 0.442, 20.200% |
| Required Clock Path Delay | cell: 0.683, 34.168%; route: 1.315, 65.832% |
Path4
Path Summary:
| Slack | 7.600 |
| Data Arrival Time | 14.031 |
| Data Required Time | 21.631 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.031 | 1.556 | tNET | FF | 1 | R11C59[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.979 | 1.296 | tNET | RR | 1 | R11C59[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK |
| 21.631 | -0.347 | tSu | 1 | R11C59[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1 |
Path Statistics:
| Clock Skew | -0.054 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.556, 77.854%; tC2Q: 0.442, 22.146% |
| Required Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
Path5
Path Summary:
| Slack | 7.600 |
| Data Arrival Time | 14.031 |
| Data Required Time | 21.631 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.031 | 1.556 | tNET | FF | 1 | R11C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.979 | 1.296 | tNET | RR | 1 | R11C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
| 21.631 | -0.347 | tSu | 1 | R11C59[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
| Clock Skew | -0.054 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.556, 77.854%; tC2Q: 0.442, 22.146% |
| Required Clock Path Delay | cell: 0.683, 34.491%; route: 1.296, 65.509% |
Path6
Path Summary:
| Slack | 7.610 |
| Data Arrival Time | 14.031 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.031 | 1.556 | tNET | FF | 1 | R11C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C60[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.556, 77.854%; tC2Q: 0.442, 22.146% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path7
Path Summary:
| Slack | 7.637 |
| Data Arrival Time | 14.013 |
| Data Required Time | 21.650 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.013 | 1.538 | tNET | FF | 1 | R11C57[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.997 | 1.315 | tNET | RR | 1 | R11C57[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK |
| 21.650 | -0.347 | tSu | 1 | R11C57[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1 |
Path Statistics:
| Clock Skew | -0.035 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.538, 77.659%; tC2Q: 0.442, 22.341% |
| Required Clock Path Delay | cell: 0.683, 34.168%; route: 1.315, 65.832% |
Path8
Path Summary:
| Slack | 7.637 |
| Data Arrival Time | 14.013 |
| Data Required Time | 21.650 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 14.013 | 1.538 | tNET | FF | 1 | R11C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.997 | 1.315 | tNET | RR | 1 | R11C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
| 21.650 | -0.347 | tSu | 1 | R11C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
| Clock Skew | -0.035 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.538, 77.659%; tC2Q: 0.442, 22.341% |
| Required Clock Path Delay | cell: 0.683, 34.168%; route: 1.315, 65.832% |
Path9
Path Summary:
| Slack | 7.820 |
| Data Arrival Time | 13.821 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.821 | 1.346 | tNET | FF | 1 | R11C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.346, 75.253%; tC2Q: 0.442, 24.747% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path10
Path Summary:
| Slack | 7.820 |
| Data Arrival Time | 13.821 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.821 | 1.346 | tNET | FF | 1 | R11C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.346, 75.253%; tC2Q: 0.442, 24.747% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path11
Path Summary:
| Slack | 7.820 |
| Data Arrival Time | 13.821 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.821 | 1.346 | tNET | FF | 1 | R11C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C56[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.346, 75.253%; tC2Q: 0.442, 24.747% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path12
Path Summary:
| Slack | 7.820 |
| Data Arrival Time | 13.821 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.821 | 1.346 | tNET | FF | 1 | R11C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.346, 75.253%; tC2Q: 0.442, 24.747% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path13
Path Summary:
| Slack | 7.820 |
| Data Arrival Time | 13.821 |
| Data Required Time | 21.641 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.821 | 1.346 | tNET | FF | 1 | R11C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.988 | 1.306 | tNET | RR | 1 | R11C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK |
| 21.641 | -0.347 | tSu | 1 | R11C58[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1 |
Path Statistics:
| Clock Skew | -0.045 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.346, 75.253%; tC2Q: 0.442, 24.747% |
| Required Clock Path Delay | cell: 0.683, 34.329%; route: 1.306, 65.671% |
Path14
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C56[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path15
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C56[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path16
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C58[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path17
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C58[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path18
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C58[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path19
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C58[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path20
Path Summary:
| Slack | 8.047 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.624 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.972 | 1.289 | tNET | RR | 1 | R12C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
| 21.624 | -0.347 | tSu | 1 | R12C56[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
| Clock Skew | -0.061 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.617%; route: 1.289, 65.383% |
Path21
Path Summary:
| Slack | 8.056 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.633 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.981 | 1.298 | tNET | RR | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
| 21.633 | -0.347 | tSu | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
| Clock Skew | -0.052 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.453%; route: 1.298, 65.547% |
Path22
Path Summary:
| Slack | 8.056 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.633 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C57[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.981 | 1.298 | tNET | RR | 1 | R12C57[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK |
| 21.633 | -0.347 | tSu | 1 | R12C57[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1 |
Path Statistics:
| Clock Skew | -0.052 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.453%; route: 1.298, 65.547% |
Path23
Path Summary:
| Slack | 8.056 |
| Data Arrival Time | 13.577 |
| Data Required Time | 21.633 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.577 | 1.102 | tNET | FF | 1 | R12C57[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 21.981 | 1.298 | tNET | RR | 1 | R12C57[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
| 21.633 | -0.347 | tSu | 1 | R12C57[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
| Clock Skew | -0.052 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.102, 71.348%; tC2Q: 0.442, 28.652% |
| Required Clock Path Delay | cell: 0.683, 34.453%; route: 1.298, 65.547% |
Path24
Path Summary:
| Slack | 8.240 |
| Data Arrival Time | 13.444 |
| Data Required Time | 21.684 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.444 | 0.969 | tNET | FF | 1 | R23C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.031 | 1.349 | tNET | RR | 1 | R23C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK |
| 21.684 | -0.347 | tSu | 1 | R23C61[2][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355% |
| Required Clock Path Delay | cell: 0.683, 33.600%; route: 1.349, 66.400% |
Path25
Path Summary:
| Slack | 8.240 |
| Data Arrival Time | 13.444 |
| Data Required Time | 21.684 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 12.033 | 1.345 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 12.475 | 0.442 | tC2Q | FF | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 13.444 | 0.969 | tNET | FF | 1 | R23C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 20.683 | 0.683 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 22.031 | 1.349 | tNET | RR | 1 | R23C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK |
| 21.684 | -0.347 | tSu | 1 | R23C61[0][A] | gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Setup Relationship | 10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.688, 33.820%; route: 1.345, 66.180% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.969, 68.645%; tC2Q: 0.442, 31.355% |
| Required Clock Path Delay | cell: 0.683, 33.600%; route: 1.349, 66.400% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 10.412 |
| Data Arrival Time | 11.542 |
| Data Required Time | 1.130 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.542 | 0.197 | tNET | RR | 1 | R23C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.183 | 0.508 | tNET | RR | 1 | R23C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK |
| 1.130 | -0.053 | tHld | 1 | R23C57[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.197, 55.493%; tC2Q: 0.158, 44.507% |
| Required Clock Path Delay | cell: 0.675, 57.101%; route: 0.508, 42.899% |
Path2
Path Summary:
| Slack | 10.421 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R22C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C56[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path3
Path Summary:
| Slack | 10.423 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R23C56[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C56[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C56[2][B] | gw_gao_inst_0/u_la0_top/capture_end_dly_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path4
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path5
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[2][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path6
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[2][B] | gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path7
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/triger_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[0][A] | gw_gao_inst_0/u_la0_top/triger_s0/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[0][A] | gw_gao_inst_0/u_la0_top/triger_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path8
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/start_reg_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[0][B] | gw_gao_inst_0/u_la0_top/start_reg_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path9
Path Summary:
| Slack | 10.424 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.124 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C58[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.177 | 0.502 | tNET | RR | 1 | R24C58[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK |
| 1.124 | -0.053 | tHld | 1 | R24C58[1][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.379%; route: 0.502, 42.621% |
Path10
Path Summary:
| Slack | 10.428 |
| Data Arrival Time | 11.549 |
| Data Required Time | 1.120 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.549 | 0.203 | tNET | RR | 1 | R24C59[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.173 | 0.498 | tNET | RR | 1 | R24C59[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK |
| 1.120 | -0.053 | tHld | 1 | R24C59[1][A] | gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1 |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.203, 56.233%; tC2Q: 0.158, 43.767% |
| Required Clock Path Delay | cell: 0.675, 57.575%; route: 0.498, 42.425% |
Path11
Path Summary:
| Slack | 10.434 |
| Data Arrival Time | 11.555 |
| Data Required Time | 1.120 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.554 | 0.209 | tNET | RR | 1 | R24C55[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.173 | 0.498 | tNET | RR | 1 | R24C55[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK |
| 1.120 | -0.053 | tHld | 1 | R24C55[0][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0 |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052% |
| Required Clock Path Delay | cell: 0.675, 57.575%; route: 0.498, 42.425% |
Path12
Path Summary:
| Slack | 10.434 |
| Data Arrival Time | 11.555 |
| Data Required Time | 1.120 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.554 | 0.209 | tNET | RR | 1 | R24C55[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.173 | 0.498 | tNET | RR | 1 | R24C55[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK |
| 1.120 | -0.053 | tHld | 1 | R24C55[0][A] | gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0 |
Path Statistics:
| Clock Skew | -0.014 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052% |
| Required Clock Path Delay | cell: 0.675, 57.575%; route: 0.498, 42.425% |
Path13
Path Summary:
| Slack | 10.527 |
| Data Arrival Time | 11.653 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.653 | 0.307 | tNET | RR | 1 | R23C58[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C58[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C58[2][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 66.021%; tC2Q: 0.158, 33.978% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path14
Path Summary:
| Slack | 10.527 |
| Data Arrival Time | 11.653 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.653 | 0.307 | tNET | RR | 1 | R23C58[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C58[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C58[3][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 66.021%; tC2Q: 0.158, 33.978% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path15
Path Summary:
| Slack | 10.527 |
| Data Arrival Time | 11.653 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.653 | 0.307 | tNET | RR | 1 | R23C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 66.021%; tC2Q: 0.158, 33.978% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path16
Path Summary:
| Slack | 10.527 |
| Data Arrival Time | 11.653 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.653 | 0.307 | tNET | RR | 1 | R23C58[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C58[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C58[2][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 66.021%; tC2Q: 0.158, 33.978% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path17
Path Summary:
| Slack | 10.527 |
| Data Arrival Time | 11.653 |
| Data Required Time | 1.126 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.653 | 0.307 | tNET | RR | 1 | R23C58[0][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.179 | 0.503 | tNET | RR | 1 | R23C58[0][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK |
| 1.126 | -0.053 | tHld | 1 | R23C58[0][A] | gw_gao_inst_0/u_la0_top/trigger_seq_start_s1 |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.307, 66.021%; tC2Q: 0.158, 33.978% |
| Required Clock Path Delay | cell: 0.675, 57.294%; route: 0.503, 42.706% |
Path18
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[0][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path19
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[1][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path20
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[1][B] | gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path21
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[0][A] | gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path22
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[2][B] | gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path23
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[3][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path24
Path Summary:
| Slack | 10.625 |
| Data Arrival Time | 11.753 |
| Data Required Time | 1.128 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.752 | 0.407 | tNET | RR | 1 | R22C58[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.181 | 0.505 | tNET | RR | 1 | R22C58[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK |
| 1.128 | -0.053 | tHld | 1 | R22C58[2][A] | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.407, 72.035%; tC2Q: 0.158, 27.965% |
| Required Clock Path Delay | cell: 0.675, 57.209%; route: 0.505, 42.791% |
Path25
Path Summary:
| Slack | 10.703 |
| Data Arrival Time | 11.800 |
| Data Required Time | 1.098 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
| Launch Clk | clk:[F] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | ||||
| 10.000 | 0.000 | clk | ||||
| 10.000 | 0.000 | tCL | FF | 1 | IOB29[A] | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | 4263 | IOB29[A] | clk_ibuf/O |
| 11.188 | 0.510 | tNET | FF | 1 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 11.345 | 0.158 | tC2Q | FR | 53 | R24C57[0][A] | gw_gao_inst_0/u_la0_top/rst_ao_s0/Q |
| 11.800 | 0.455 | tNET | RR | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOB29[A] | clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 4263 | IOB29[A] | clk_ibuf/O |
| 1.151 | 0.475 | tNET | RR | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK |
| 1.098 | -0.053 | tHld | 1 | R12C57[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1 |
Path Statistics:
| Clock Skew | -0.037 |
| Hold Relationship | -10.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.678, 57.053%; route: 0.510, 42.947% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.455, 74.225%; tC2Q: 0.158, 25.775% |
| Required Clock Path Delay | cell: 0.675, 58.714%; route: 0.475, 41.286% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 8.156 |
| Actual Width: | 9.156 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 12.008 | 1.321 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.164 | 0.489 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
| Slack: | 8.156 |
| Actual Width: | 9.156 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 12.008 | 1.321 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.164 | 0.489 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
MPW3
MPW Summary:
| Slack: | 8.157 |
| Actual Width: | 9.157 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | mem_data_in_mem_data_in_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 11.999 | 1.312 | tNET | FF | mem_data_in_mem_data_in_0_0_s/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.156 | 0.481 | tNET | RR | mem_data_in_mem_data_in_0_0_s/CLK |
MPW4
MPW Summary:
| Slack: | 8.161 |
| Actual Width: | 9.161 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 11.999 | 1.312 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.160 | 0.485 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
MPW5
MPW Summary:
| Slack: | 8.161 |
| Actual Width: | 9.161 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 11.999 | 1.312 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.160 | 0.485 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA |
MPW6
MPW Summary:
| Slack: | 8.164 |
| Actual Width: | 9.164 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 11.999 | 1.312 | tNET | FF | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.163 | 0.488 | tNET | RR | Natural_Logarithm_inst/FP_Natural_Logarithm_inst/fixed_exponent_in_31_s0/CLK[0] |
MPW7
MPW Summary:
| Slack: | 8.167 |
| Actual Width: | 9.167 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | clk | ||
| 0.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | clk_ibuf/O |
| 2.005 | 1.322 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | clk_ibuf/O |
| 11.171 | 0.494 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW8
MPW Summary:
| Slack: | 8.167 |
| Actual Width: | 9.167 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | clk | ||
| 0.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | clk_ibuf/O |
| 2.005 | 1.322 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | clk_ibuf/O |
| 11.171 | 0.494 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA |
MPW9
MPW Summary:
| Slack: | 8.167 |
| Actual Width: | 9.167 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.688 | 0.688 | tINS | FF | clk_ibuf/O |
| 11.990 | 1.302 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | clk | ||
| 20.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 20.676 | 0.675 | tINS | RR | clk_ibuf/O |
| 21.156 | 0.481 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
MPW10
MPW Summary:
| Slack: | 8.168 |
| Actual Width: | 9.168 |
| Required Width: | 1.000 |
| Type: | High Pulse Width |
| Clock: | clk |
| Objects: | mem_data_in_mem_data_in_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | clk | ||
| 0.000 | 0.000 | tCL | RR | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | clk_ibuf/O |
| 1.995 | 1.313 | tNET | RR | mem_data_in_mem_data_in_0_0_s/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | clk | ||
| 10.000 | 0.000 | tCL | FF | clk_ibuf/I |
| 10.677 | 0.678 | tINS | FF | clk_ibuf/O |
| 11.163 | 0.486 | tNET | FF | mem_data_in_mem_data_in_0_0_s/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 4263 | clk_d | 7.430 | 1.366 |
| 4071 | ce | 12.145 | 2.684 |
| 340 | control0[0] | 40.924 | 2.385 |
| 158 | data_y_out_25[50] | 13.374 | 3.515 |
| 157 | data_y_out_24[50] | 14.237 | 3.037 |
| 156 | data_y_out_23[50] | 14.381 | 3.102 |
| 155 | data_y_out_22[50] | 13.636 | 3.438 |
| 154 | data_y_out_21[50] | 13.076 | 2.930 |
| 153 | data_y_out_20[50] | 12.847 | 4.920 |
| 152 | data_y_out_19[50] | 12.864 | 3.491 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R21C48 | 69.44% |
| R16C48 | 65.28% |
| R16C50 | 63.89% |
| R20C47 | 63.89% |
| R21C46 | 63.89% |
| R5C48 | 62.50% |
| R33C46 | 62.50% |
| R26C49 | 62.50% |
| R20C48 | 61.11% |
| R3C52 | 59.72% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}] |
| TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk}] -group [get_clocks {tck_pad_i}] |