Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\gowin_pll\gowin_pll.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\gowin_pll\gowin_pll_mod.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\pll_init.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\top.sv D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\USB30_Device_Controller_Top.sv D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\transfer_in_mem.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\transfer_in_mem_ping_pong.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\transfer_out_mem.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\transfer_out_mem_ping_pong.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb30_device_controller.sv D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_TxHp.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_TxLcmd.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_const.vh D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_crc.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_descramble.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_ep.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_ep0.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_ep0in_ram.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_lfsr.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_link.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_ltssm_device.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_macro_define.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_pipe.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_protocol.sv D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_device_controller\usb3_scramble.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_user_layer\ControlTransfer.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_user_layer\EP1_loopback.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_user_layer\EP2_INT.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_user_layer\UserLayer_top.sv D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\usb30_user_layer\usb_descrip_define.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\serdes\usb3_0_phy\usb3_0_phy.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\serdes\upar_arbiter\upar_arbiter.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\src\serdes\serdes.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Gowin\Gowin_V1.9.12.03_x64\IDE\data\ipcores\gw_jtag.v D:\MXY\project_202607\USB3.x ref design\Gowin_USB30_CDC_BULK_RefDeign_15K_2\prj\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5ART-LV15MG132PC1/I0
Device	GW5ART-15
Device Version	A
Created Time	Mon Jul 27 10:37:46 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	top
Synthesis Process	Running parser:     CPU time = 0h 0m 2s, Elapsed time = 0h 0m 1s, Peak memory usage = 383.105MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 383.105MB     Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 383.105MB     Optimizing Phase 2: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 383.105MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 383.105MB     Inferring Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 383.105MB     Inferring Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.154s, Peak memory usage = 383.105MB     Inferring Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 383.105MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 383.105MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 0.972s, Peak memory usage = 383.105MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.884s, Peak memory usage = 383.105MB     Tech-Mapping Phase 3: CPU time = 0h 1m 59s, Elapsed time = 0h 1m 59s, Peak memory usage = 383.105MB     Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 383.105MB Generate output files:     CPU time = 0h 0m 0.765s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 399.699MB
Total Time and Memory Usage	CPU time = 0h 2m 24s, Elapsed time = 0h 2m 22s, Peak memory usage = 399.699MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	5
I/O Buf	5
IBUF	4
OBUF	1
Register	6290
DFFSE	89
DFFRE	2044
DFFPE	137
DFFCE	4020
LUT	12147
LUT2	1693
LUT3	3696
LUT4	6758
ALU	352
ALU	352
SSRAM	34
RAM16SDP1	2
RAM16SDP2	1
RAM16SDP4	31
ROM16	60
ROM16	60
INV	108
INV	108
DSP
MULTALU27X18	1
BSRAM	14
SDPB	8
SDPX9B	6
CLOCK	1
PLLA	1
Black Box	3
GW_JTAG	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	12871(12255 LUT, 352 ALU, 60 ROM16, 34 RAM16) / 15120	86%
Register	6290 / 15231	42%
--Register as Latch	0 / 15231	0%
--Register as FF	6290 / 15231	42%
BSRAM	14 / 35	40%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	fclk	Base	20.000	50.000	0.000	10.000			fclk_ibuf/I
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			gw_gao_inst_0/tck_ibuf/I
3	gw_gao_inst_0/u_la0_top/n15_6	Base	10.000	100.000	0.000	5.000			gw_gao_inst_0/u_la0_top/n15_s2/F
4	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	8.000	125.000	0.000	4.000	fclk_ibuf/I	fclk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	fclk	50.000(MHz)	164.092(MHz)	8	TOP
2	tck_pad_i	20.000(MHz)	157.270(MHz)	8	TOP
3	gw_gao_inst_0/u_la0_top/n15_6	100.000(MHz)	1352.951(MHz)	1	TOP
4	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	125.000(MHz)	386.978(MHz)	3	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_0_s1
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_0_s1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_0_s1/CLK
24.640	-0.035	tUnc			cnt0_0_s1
24.305	-0.335	tSu		1	cnt0_0_s1

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 2

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	phy_resetn2_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	phy_resetn2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	phy_resetn2_s0/CLK
24.640	-0.035	tUnc			phy_resetn2_s0
24.305	-0.335	tSu		1	phy_resetn2_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 3

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	phy_resetn_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	phy_resetn_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	phy_resetn_s0/CLK
24.640	-0.035	tUnc			phy_resetn_s0
24.305	-0.335	tSu		1	phy_resetn_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 4

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_0_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_0_s0/CLK
24.640	-0.035	tUnc			cnt1_0_s0
24.305	-0.335	tSu		1	cnt1_0_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 5

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_1_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_1_s0/CLK
24.640	-0.035	tUnc			cnt1_1_s0
24.305	-0.335	tSu		1	cnt1_1_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 6

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_2_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_2_s0/CLK
24.640	-0.035	tUnc			cnt1_2_s0
24.305	-0.335	tSu		1	cnt1_2_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 7

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_3_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_3_s0/CLK
24.640	-0.035	tUnc			cnt1_3_s0
24.305	-0.335	tSu		1	cnt1_3_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 8

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_4_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_4_s0/CLK
24.640	-0.035	tUnc			cnt1_4_s0
24.305	-0.335	tSu		1	cnt1_4_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 9

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_5_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_5_s0/CLK
24.640	-0.035	tUnc			cnt1_5_s0
24.305	-0.335	tSu		1	cnt1_5_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 10

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_6_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_6_s0/CLK
24.640	-0.035	tUnc			cnt1_6_s0
24.305	-0.335	tSu		1	cnt1_6_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 11

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_7_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_7_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_7_s0/CLK
24.640	-0.035	tUnc			cnt1_7_s0
24.305	-0.335	tSu		1	cnt1_7_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 12

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_8_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_8_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_8_s0/CLK
24.640	-0.035	tUnc			cnt1_8_s0
24.305	-0.335	tSu		1	cnt1_8_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 13

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_9_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_9_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_9_s0/CLK
24.640	-0.035	tUnc			cnt1_9_s0
24.305	-0.335	tSu		1	cnt1_9_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 14

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_10_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_10_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_10_s0/CLK
24.640	-0.035	tUnc			cnt1_10_s0
24.305	-0.335	tSu		1	cnt1_10_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 15

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_11_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_11_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_11_s0/CLK
24.640	-0.035	tUnc			cnt1_11_s0
24.305	-0.335	tSu		1	cnt1_11_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 16

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_12_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_12_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_12_s0/CLK
24.640	-0.035	tUnc			cnt1_12_s0
24.305	-0.335	tSu		1	cnt1_12_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 17

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_13_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_13_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_13_s0/CLK
24.640	-0.035	tUnc			cnt1_13_s0
24.305	-0.335	tSu		1	cnt1_13_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 18

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_14_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_14_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_14_s0/CLK
24.640	-0.035	tUnc			cnt1_14_s0
24.305	-0.335	tSu		1	cnt1_14_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 19

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt1_15_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt1_15_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt1_15_s0/CLK
24.640	-0.035	tUnc			cnt1_15_s0
24.305	-0.335	tSu		1	cnt1_15_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 20

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_1_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_1_s0/CLK
24.640	-0.035	tUnc			cnt0_1_s0
24.305	-0.335	tSu		1	cnt0_1_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 21

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_2_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_2_s0/CLK
24.640	-0.035	tUnc			cnt0_2_s0
24.305	-0.335	tSu		1	cnt0_2_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 22

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_3_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_3_s0/CLK
24.640	-0.035	tUnc			cnt0_3_s0
24.305	-0.335	tSu		1	cnt0_3_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 23

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_4_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_4_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_4_s0/CLK
24.640	-0.035	tUnc			cnt0_4_s0
24.305	-0.335	tSu		1	cnt0_4_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 24

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_5_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_5_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_5_s0/CLK
24.640	-0.035	tUnc			cnt0_5_s0
24.305	-0.335	tSu		1	cnt0_5_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%

Path 25

Path Summary:

Slack	3.286
Data Arrival Time	21.019
Data Required Time	24.305
From	Inst_Gowin_PLL/u_pll_init/rLockOut_s0
To	cnt0_6_s0
Launch Clk	fclk[R]
Latch Clk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				fclk
20.000	0.000	tCL	RR	1	fclk_ibuf/I
20.000	0.000	tINS	RR	123	fclk_ibuf/O
20.337	0.337	tNET	RR	1	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/CLK
20.682	0.344	tC2Q	RR	26	Inst_Gowin_PLL/u_pll_init/rLockOut_s0/Q
21.019	0.337	tNET	RR	1	cnt0_6_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
24.000	24.000				active clock edge time
24.000	0.000				Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk
24.337	0.337	tCL	RR	26	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
24.675	0.337	tNET	RR	1	cnt0_6_s0/CLK
24.640	-0.035	tUnc			cnt0_6_s0
24.305	-0.335	tSu		1	cnt0_6_s0

Path Statistics:

Clock Skew:	0.337
Setup Relationship:	4.000
Logic Level:	1
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%
Arrival Data Path Delay:	cell: 0.000, 0.000%; route: 0.337, 49.505%; tC2Q: 0.344, 50.495%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.337, 100.000%