Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.03_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy_top.v
D:\Gowin\Gowin_V1.9.12.03_x64\IDE\ipcore\SERDES_IP\IPlib\USB30PHY\data\usb3_0_phy.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.03 (64-bit)
Part Number GW5ART-LV15MG132PC1/I0
Device GW5ART-15
Device Version A
Created Time Mon Jul 27 10:34:06 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB3_0_PHY_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.257s, Peak memory usage = 86.223MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 86.223MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 86.223MB
    Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.082s, Peak memory usage = 86.223MB
    Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 86.223MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 86.223MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 86.223MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 86.223MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 86.223MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.298s, Peak memory usage = 86.223MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 86.223MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 86.223MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 117.984MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.277s, Peak memory usage = 117.984MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.118s, Peak memory usage = 117.984MB
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 117.984MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 395
I/O Buf 330
    IBUF 133
    OBUF 197
Register 995
    DFFSE 6
    DFFRE 151
    DFFPE 23
    DFFCE 815
LUT 2015
    LUT2 196
    LUT3 595
    LUT4 1224
ALU 25
    ALU 25
INV 6
    INV 6
BSRAM 1
    SDPX9B 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2046(2021 LUT, 25 ALU) / 15120 14%
Register 995 / 15231 7%
  --Register as Latch 0 / 15231 0%
  --Register as FF 995 / 15231 7%
BSRAM 1 / 35 3%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 serdes_upar_clk_i Base 10.000 100.000 0.000 5.000 serdes_upar_clk_i_ibuf/I
2 serdes_pcs_tx_clk_i Base 10.000 100.000 0.000 5.000 serdes_pcs_tx_clk_i_ibuf/I
3 serdes_pcs_rx_clk_i Base 10.000 100.000 0.000 5.000 serdes_pcs_rx_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_upar_clk_i 100.000(MHz) 199.140(MHz) 7 TOP
2 serdes_pcs_tx_clk_i 100.000(MHz) 149.347(MHz) 9 TOP
3 serdes_pcs_rx_clk_i 100.000(MHz) 153.425(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 2

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 3

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_8_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_8_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_8_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 4

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_11_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_11_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_11_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 5

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_13_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_13_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_13_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 6

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_16_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 7

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_18_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_18_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_18_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_18_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 8

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_19_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_19_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_19_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_19_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 9

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_20_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_20_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_20_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_20_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 10

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_22_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_22_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_22_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_22_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 11

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_25_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_25_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_25_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_25_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 12

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_28_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 13

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_29_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_29_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_29_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_29_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 14

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_30_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 15

Path Summary:
Slack 3.304
Data Arrival Time 6.748
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/I1
6.441 0.422 tINS RR 15 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s4/F
6.748 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_31_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.367, 52.270%; route: 2.761, 42.871%; tC2Q: 0.313, 4.859%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 16

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 17

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 18

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 19

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 20

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 21

Path Summary:
Slack 3.394
Data Arrival Time 6.658
Data Required Time 10.052
From Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0
To Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/CLK
0.620 0.313 tC2Q RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_21_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s21/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s16/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/I2
2.779 0.377 tINS RR 2 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s12/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I2
3.463 0.377 tINS RR 5 Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
3.770 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/I0
4.200 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s24/F
4.507 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/I1
4.930 0.422 tINS RR 3 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s10/F
5.236 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/I2
5.614 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s4/F
5.921 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I0
6.351 0.431 tINS RR 7 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
6.658 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CLK
10.052 -0.255 tSu 1 Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.277, 51.594%; route: 2.761, 43.478%; tC2Q: 0.313, 4.928%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 22

Path Summary:
Slack 3.482
Data Arrival Time 6.772
Data Required Time 10.255
From Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_0_s0
To Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1
Launch Clk serdes_pcs_rx_clk_i[R]
Latch Clk serdes_pcs_rx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_rx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
0.000 0.000 tINS RR 517 serdes_pcs_rx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_0_s0/CLK
0.620 0.313 tC2Q RR 12 Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_0_s0/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s19/I0
1.357 0.431 tINS RR 2 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s19/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s72/I2
2.041 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s72/F
2.348 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s46/I0
2.779 0.431 tINS RR 3 Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s46/F
3.086 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s24/I0
3.516 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s24/F
3.823 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s15/I0
4.254 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s15/F
4.560 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s8/I0
4.991 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s8/F
5.298 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s4/I0
5.728 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s4/F
6.035 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s3/I0
6.466 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_word_alignment/n762_s3/F
6.772 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_rx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
10.000 0.000 tINS RR 517 serdes_pcs_rx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CLK
10.255 -0.052 tSu 1 Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.391, 52.452%; route: 2.761, 42.708%; tC2Q: 0.313, 4.840%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 23

Path Summary:
Slack 3.499
Data Arrival Time 6.756
Data Required Time 10.255
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_1_s3
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n270_s4/I0
6.449 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n270_s4/F
6.756 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_1_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_1_s3/CLK
10.255 -0.052 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_1_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.375, 52.331%; route: 2.761, 42.816%; tC2Q: 0.313, 4.853%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 24

Path Summary:
Slack 3.499
Data Arrival Time 6.756
Data Required Time 10.255
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_3_s3
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n268_s5/I0
6.449 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n268_s5/F
6.756 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_3_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_3_s3/CLK
10.255 -0.052 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_3_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.375, 52.331%; route: 2.761, 42.816%; tC2Q: 0.313, 4.853%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 25

Path Summary:
Slack 3.499
Data Arrival Time 6.756
Data Required Time 10.255
From Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3
To Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_4_s3
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
0.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/CLK
0.620 0.313 tC2Q RR 6 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_0_s3/Q
0.927 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/I0
1.357 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s106/F
1.664 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/I0
2.095 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s105/F
2.401 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/I1
2.824 0.422 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s104/F
3.131 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/I2
3.508 0.377 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s102/F
3.815 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/I0
4.245 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s99/F
4.552 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/I0
4.983 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s97/F
5.290 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/I1
5.712 0.422 tINS RR 19 Inst_usb3_0_phy/Inst_usb_pipe_interface/n204_s96/F
6.019 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n267_s5/I0
6.449 0.431 tINS RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/n267_s5/F
6.756 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_4_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 412 serdes_pcs_tx_clk_i_ibuf/O
10.307 0.307 tNET RR 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_4_s3/CLK
10.255 -0.052 tSu 1 Inst_usb3_0_phy/Inst_usb_pipe_interface/cnt_timeout_4_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 3.375, 52.331%; route: 2.761, 42.816%; tC2Q: 0.313, 4.853%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%