Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.03_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter.v
D:\Gowin\Gowin_V1.9.12.03_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.03 (64-bit)
Part Number GW5ART-LV15MG132PC1/I0
Device GW5ART-15
Device Version A
Created Time Mon Jul 27 10:34:07 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module \~upar_arbiter_wrap.SerDes_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.166s, Peak memory usage = 76.910MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 76.910MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 76.910MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 76.910MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 76.910MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 76.910MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.910MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.910MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 76.910MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 76.910MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 76.910MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.910MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 100.633MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 100.633MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 100.633MB
Total Time and Memory Usage CPU time = 0h 0m 0.54s, Elapsed time = 0h 0m 0.566s, Peak memory usage = 100.633MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 511
I/O Buf 511
    IBUF 299
    OBUF 212
Register 282
    DFFPE 4
    DFFCE 278
LUT 369
    LUT2 132
    LUT3 165
    LUT4 72
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 370(370 LUT, 0 ALU) / 15120 3%
Register 282 / 15231 2%
  --Register as Latch 0 / 15231 0%
  --Register as FF 282 / 15231 2%
BSRAM 0 / 35 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 upar_clk_i Base 10.000 100.000 0.000 5.000 upar_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 upar_clk_i 100.000(MHz) 353.243(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.169
Data Arrival Time 3.086
Data Required Time 10.255
From u_upar_arbiter/cur_grant_3_s0
To u_upar_arbiter/drp_num_1_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/CLK
0.620 0.313 tC2Q RR 2 u_upar_arbiter/cur_grant_3_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n341_s2/I2
1.304 0.377 tINS RR 4 u_upar_arbiter/n341_s2/F
1.611 0.307 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_1_s1/I0
2.041 0.431 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_1_s1/F
2.348 0.307 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_1_s0/I0
2.779 0.431 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_1_s0/F
3.086 0.307 tNET RR 1 u_upar_arbiter/drp_num_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/drp_num_1_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/drp_num_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 1.239, 44.572%; route: 1.227, 44.166%; tC2Q: 0.313, 11.262%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 2

Path Summary:
Slack 7.222
Data Arrival Time 3.032
Data Required Time 10.255
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/cur_state_0_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/next_state_0_s7/I2
2.041 0.377 tINS RR 1 u_upar_arbiter/next_state_0_s7/F
2.348 0.307 tNET RR 1 u_upar_arbiter/next_state_0_s5/I2
2.726 0.377 tINS RR 1 u_upar_arbiter/next_state_0_s5/F
3.032 0.307 tNET RR 1 u_upar_arbiter/cur_state_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/cur_state_0_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/cur_state_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 1.185, 43.490%; route: 1.227, 45.028%; tC2Q: 0.313, 11.482%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 3

Path Summary:
Slack 7.275
Data Arrival Time 2.979
Data Required Time 10.255
From u_upar_arbiter/cur_grant_2_s0
To u_upar_arbiter/drp_num_0_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/CLK
0.620 0.313 tC2Q RR 1 u_upar_arbiter/cur_grant_2_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n341_s3/I2
1.304 0.377 tINS RR 6 u_upar_arbiter/n341_s3/F
1.611 0.307 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_0_s1/I2
1.988 0.377 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_0_s1/F
2.295 0.307 tNET RR 1 u_upar_arbiter/drp_num_pre[3]_0_s0/I2
2.672 0.377 tINS RR 1 u_upar_arbiter/drp_num_pre[3]_0_s0/F
2.979 0.307 tNET RR 1 u_upar_arbiter/drp_num_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/drp_num_0_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/drp_num_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 1.132, 42.365%; route: 1.227, 45.924%; tC2Q: 0.313, 11.711%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 4

Path Summary:
Slack 7.275
Data Arrival Time 2.979
Data Required Time 10.255
From u_upar_arbiter/cur_grant_2_s0
To u_upar_arbiter/cur_grant_1_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/CLK
0.620 0.313 tC2Q RR 1 u_upar_arbiter/cur_grant_2_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n341_s3/I2
1.304 0.377 tINS RR 6 u_upar_arbiter/n341_s3/F
1.611 0.307 tNET RR 1 u_upar_arbiter/n343_s1/I2
1.988 0.377 tINS RR 1 u_upar_arbiter/n343_s1/F
2.295 0.307 tNET RR 1 u_upar_arbiter/n343_s0/I2
2.672 0.377 tINS RR 1 u_upar_arbiter/n343_s0/F
2.979 0.307 tNET RR 1 u_upar_arbiter/cur_grant_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_1_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/cur_grant_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 1.132, 42.365%; route: 1.227, 45.924%; tC2Q: 0.313, 11.711%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 5

Path Summary:
Slack 7.601
Data Arrival Time 2.654
Data Required Time 10.255
From u_upar_arbiter/cur_grant_0_s0
To u_upar_arbiter/cur_grant_3_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_0_s0/CLK
0.620 0.313 tC2Q RR 3 u_upar_arbiter/cur_grant_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n341_s6/I2
1.304 0.377 tINS RR 2 u_upar_arbiter/n341_s6/F
1.611 0.307 tNET RR 1 u_upar_arbiter/n341_s7/I3
1.826 0.215 tINS RR 3 u_upar_arbiter/n341_s7/F
2.132 0.307 tNET RR 1 u_upar_arbiter/n341_s0/I3
2.347 0.215 tINS RR 1 u_upar_arbiter/n341_s0/F
2.654 0.307 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_3_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/cur_grant_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.807, 34.379%; route: 1.227, 52.288%; tC2Q: 0.313, 13.333%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 6

Path Summary:
Slack 7.601
Data Arrival Time 2.654
Data Required Time 10.255
From u_upar_arbiter/cur_grant_0_s0
To u_upar_arbiter/cur_grant_2_s0
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_0_s0/CLK
0.620 0.313 tC2Q RR 3 u_upar_arbiter/cur_grant_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n341_s6/I2
1.304 0.377 tINS RR 2 u_upar_arbiter/n341_s6/F
1.611 0.307 tNET RR 1 u_upar_arbiter/n341_s7/I3
1.826 0.215 tINS RR 3 u_upar_arbiter/n341_s7/F
2.132 0.307 tNET RR 1 u_upar_arbiter/n342_s0/I3
2.347 0.215 tINS RR 1 u_upar_arbiter/n342_s0/F
2.654 0.307 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/cur_grant_2_s0/CLK
10.255 -0.052 tSu 1 u_upar_arbiter/cur_grant_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.807, 34.379%; route: 1.227, 52.288%; tC2Q: 0.313, 13.333%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 7

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_0_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_0_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 8

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_1_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_1_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 9

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_2_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_2_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 10

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_3_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_3_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 11

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_4_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_4_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 12

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_5_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_5_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_5_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_5_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 13

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_6_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_6_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_6_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 14

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_7_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_7_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_7_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 15

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_8_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_8_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_8_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 16

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_9_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_9_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_9_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 17

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_10_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_10_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_10_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 18

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_11_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_11_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_11_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 19

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_12_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_12_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_12_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_12_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 20

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_13_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_13_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_13_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 21

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_14_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_14_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_14_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 22

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_15_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_15_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_15_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_15_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 23

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_16_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_16_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_16_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_16_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 24

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_17_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_17_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_17_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_17_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%

Path 25

Path Summary:
Slack 7.651
Data Arrival Time 2.401
Data Required Time 10.052
From u_upar_arbiter/judg_addr_state_cnt_0_s0
To u_upar_arbiter/upar_addr_o_18_s1
Launch Clk upar_clk_i[R]
Latch Clk upar_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 upar_clk_i
0.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
0.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
0.307 0.307 tNET RR 1 u_upar_arbiter/judg_addr_state_cnt_0_s0/CLK
0.620 0.313 tC2Q RR 72 u_upar_arbiter/judg_addr_state_cnt_0_s0/Q
0.927 0.307 tNET RR 1 u_upar_arbiter/n689_s2/I0
1.357 0.431 tINS RR 2 u_upar_arbiter/n689_s2/F
1.664 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_23_s4/I0
2.095 0.431 tINS RR 24 u_upar_arbiter/upar_addr_o_23_s4/F
2.401 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_18_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 upar_clk_i
10.000 0.000 tCL RR 1 upar_clk_i_ibuf/I
10.000 0.000 tINS RR 282 upar_clk_i_ibuf/O
10.307 0.307 tNET RR 1 u_upar_arbiter/upar_addr_o_18_s1/CLK
10.052 -0.255 tSu 1 u_upar_arbiter/upar_addr_o_18_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%
Arrival Data Path Delay: cell: 0.861, 41.113%; route: 0.920, 43.946%; tC2Q: 0.313, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.307, 100.000%