Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12.04\Gowin_USB3.0\Gowin_USB3.0_CDC_BULK_RefDesign\prj\impl\gwsynthesis\prj.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12.04\Gowin_USB3.0\Gowin_USB3.0_CDC_BULK_RefDesign\prj\src\top.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.12.04\Gowin_USB3.0\Gowin_USB3.0_CDC_BULK_RefDesign\prj\src\top.sdc
Tool Version	V1.9.12.03 (64-bit)
Part Number	GW5ART-LV15MG132PC1/I0
Device	GW5ART-15
Device Version	A
Created Time	Mon Aug 10 16:30:07 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.873V 0C C1/I0
Hold Delay Model	Fast 0.927V 85C C1/I0
Numbers of Paths Analyzed	15562
Numbers of Endpoints Analyzed	21381
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
1	pclk	Base	8.000	125.000	4.000			pclk
2	drp_clk_o	Base	10.000	100.000	5.000			SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[2]
3	fabric_rx_clk	Base	8.000	125.000	4.000			SerDes_Top_inst/q0_lane2_fabric_rx_clk
4	tck_pad_i	Base	50.000	20.000	25.000			tck_pad_i
5	fclk	Base	20.000	50.000	10.000			fclk_ibuf/I
6	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	8.000	125.000	4.000	fclk_ibuf/I	fclk	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	pclk	125.000(MHz)	126.550(MHz)	7	TOP
2	drp_clk_o	100.000(MHz)	164.520(MHz)	3	TOP
3	fabric_rx_clk	125.000(MHz)	148.631(MHz)	9	TOP
4	tck_pad_i	20.000(MHz)	124.346(MHz)	7	TOP
5	fclk	50.000(MHz)	200.256(MHz)	8	TOP
6	Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	125.000(MHz)	418.793(MHz)	3	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
pclk	Setup	0.000	0
pclk	Hold	0.000	0
drp_clk_o	Setup	0.000	0
drp_clk_o	Hold	0.000	0
fabric_rx_clk	Setup	0.000	0
fabric_rx_clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
fclk	Setup	0.000	0
fclk	Hold	0.000	0
Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Setup	0.000	0
Inst_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.098	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/swap32_in_9_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/dpp_crc_good_s0/D	pclk:[R]	pclk:[R]	8.000	0.003	7.841
2	0.190	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CE	pclk:[R]	pclk:[R]	8.000	0.010	7.520
3	0.190	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1/CE	pclk:[R]	pclk:[R]	8.000	0.010	7.520
4	0.190	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1/CE	pclk:[R]	pclk:[R]	8.000	0.010	7.520
5	0.190	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CE	pclk:[R]	pclk:[R]	8.000	0.010	7.520
6	0.663	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1/CE	pclk:[R]	pclk:[R]	8.000	0.005	7.052
7	0.663	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1/CE	pclk:[R]	pclk:[R]	8.000	0.005	7.052
8	0.790	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/D	pclk:[R]	pclk:[R]	8.000	0.002	7.151
9	0.826	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_0_s2/D	pclk:[R]	pclk:[R]	8.000	-0.003	7.119
10	0.876	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_3_s2/D	pclk:[R]	pclk:[R]	8.000	-0.003	7.069
11	1.147	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_1_s2/D	pclk:[R]	pclk:[R]	8.000	-0.003	6.798
12	1.221	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_2_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.022	6.520
13	1.239	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.003	6.484
14	1.259	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_43_s1/CE	pclk:[R]	pclk:[R]	8.000	0.026	6.435
15	1.259	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s1/CE	pclk:[R]	pclk:[R]	8.000	0.026	6.435
16	1.272	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_20_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/D	fabric_rx_clk:[R]	fabric_rx_clk:[R]	8.000	-0.006	6.677
17	1.294	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/D	pclk:[R]	pclk:[R]	8.000	0.010	6.639
18	1.296	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_18_s1/CE	pclk:[R]	pclk:[R]	8.000	0.024	6.400
19	1.307	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_41_s1/CE	pclk:[R]	pclk:[R]	8.000	0.021	6.391
20	1.307	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s1/CE	pclk:[R]	pclk:[R]	8.000	0.021	6.391
21	1.326	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_0_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.008	6.402
22	1.326	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_1_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.008	6.402
23	1.357	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/D	pclk:[R]	pclk:[R]	8.000	0.017	6.569
24	1.377	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_last_86_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.022	6.365
25	1.377	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s1/CE	pclk:[R]	pclk:[R]	8.000	-0.022	6.365

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.165	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[2]	pclk:[R]	pclk:[R]	-0.004	0.213
2	0.165	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[1]	pclk:[R]	pclk:[R]	-0.004	0.213
3	0.165	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_0_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[0]	pclk:[R]	pclk:[R]	-0.004	0.213
4	0.167	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/WAD[1]	pclk:[R]	pclk:[R]	-0.004	0.216
5	0.169	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	-0.004	0.218
6	0.170	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	-0.004	0.219
7	0.170	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	-0.004	0.219
8	0.172	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/WAD[1]	pclk:[R]	pclk:[R]	-0.004	0.220
9	0.173	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	-0.001	0.219
10	0.173	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[1]	pclk:[R]	pclk:[R]	-0.004	0.221
11	0.174	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_0_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[0]	pclk:[R]	pclk:[R]	-0.004	0.222
12	0.175	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	0.004	0.216
13	0.175	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_2_s/WAD[1]	pclk:[R]	pclk:[R]	-0.013	0.233
14	0.175	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[1]	pclk:[R]	pclk:[R]	-0.001	0.221
15	0.177	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_2_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/WAD[2]	pclk:[R]	pclk:[R]	0.004	0.219
16	0.179	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_0_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[0]	pclk:[R]	pclk:[R]	0.004	0.220
17	0.180	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_0_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/WAD[0]	pclk:[R]	pclk:[R]	0.004	0.221
18	0.180	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[1]	pclk:[R]	pclk:[R]	0.004	0.221
19	0.184	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_6_s2/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/DI[16]	fabric_rx_clk:[R]	fabric_rx_clk:[R]	0.001	0.216
20	0.184	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_3_s/WAD[1]	pclk:[R]	pclk:[R]	0.004	0.226
21	0.185	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_12_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/DI[6]	fabric_rx_clk:[R]	fabric_rx_clk:[R]	0.005	0.213
22	0.185	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]	pclk:[R]	pclk:[R]	0.005	0.213
23	0.187	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_24_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/DI[2]	pclk:[R]	pclk:[R]	0.000	0.232
24	0.187	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_23_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/DI[1]	pclk:[R]	pclk:[R]	0.000	0.232
25	0.188	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]	pclk:[R]	pclk:[R]	0.008	0.213

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.267
2	2.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.267
3	2.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.267
4	2.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.267
5	2.410	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.267
6	2.431	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.245
7	2.431	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.245
8	2.431	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.245
9	2.435	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.002	1.250
10	2.435	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.002	1.250
11	2.435	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.002	1.250
12	2.541	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.045	1.101
13	2.541	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.045	1.101
14	2.541	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.045	1.101
15	2.541	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.045	1.101
16	2.547	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	pclk:[F]	pclk:[R]	4.000	0.039	1.101
17	2.554	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.019	1.115
18	2.554	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.019	1.115
19	2.554	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.019	1.115
20	2.554	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.019	1.115
21	2.554	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.019	1.115
22	2.584	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.092
23	2.584	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.092
24	2.584	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.010	1.092
25	2.633	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	pclk:[F]	pclk:[R]	4.000	0.025	1.029

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Clock Skew	Data Delay
1	0.280	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_0_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.000	0.232
2	0.284	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_1_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.004	0.232
3	0.284	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_1_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.004	0.232
4	0.284	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_2_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.004	0.232
5	0.359	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_0_s0/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.000	0.311
6	0.359	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.000	0.311
7	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_1_s1/CLEAR	pclk:[R]	pclk:[R]	-0.012	0.326
8	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_2_s1/CLEAR	pclk:[R]	pclk:[R]	-0.012	0.326
9	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_4_s1/CLEAR	pclk:[R]	pclk:[R]	-0.012	0.326
10	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/ep_rst_n_s0/CLEAR	pclk:[R]	pclk:[R]	-0.012	0.326
11	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/PRESET	pclk:[R]	pclk:[R]	-0.001	0.315
12	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/PRESET	pclk:[R]	pclk:[R]	-0.001	0.315
13	0.362	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/PRESET	pclk:[R]	pclk:[R]	-0.001	0.315
14	0.365	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_0_s1/CLEAR	pclk:[R]	pclk:[R]	-0.007	0.324
15	0.365	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_3_s1/CLEAR	pclk:[R]	pclk:[R]	-0.007	0.324
16	0.365	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_0_s0/CLEAR	pclk:[R]	pclk:[R]	-0.007	0.324
17	0.365	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_3_s0/CLEAR	pclk:[R]	pclk:[R]	-0.007	0.324
18	0.365	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_1_s0/CLEAR	pclk:[R]	pclk:[R]	-0.008	0.326
19	0.366	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/burst_in_act_s2/CLEAR	pclk:[R]	pclk:[R]	-0.004	0.322
20	0.367	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_10_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.002	0.317
21	0.367	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_11_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.002	0.317
22	0.367	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d2_s0/PRESET	drp_clk_o:[R]	drp_clk_o:[R]	0.002	0.317
23	0.367	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d1_s0/PRESET	drp_clk_o:[R]	drp_clk_o:[R]	0.002	0.317
24	0.368	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_1_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.003	0.317
25	0.368	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_2_s1/CLEAR	drp_clk_o:[R]	drp_clk_o:[R]	0.003	0.317

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_0_res_mem_0_0_0_s
2	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_0_s
3	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/mem0_mem0_0_0_s
4	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/mem0_mem0_0_0_s
5	2.116	3.016	0.900	Low Pulse Width	pclk	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
6	2.116	3.016	0.900	Low Pulse Width	fabric_rx_clk	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
7	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_1_res_mem_1_0_0_s
8	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_3_res_mem_3_0_0_s
9	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s
10	2.116	3.016	0.900	Low Pulse Width	pclk	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_out_ep_ping_pong[1].transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.098
Data Arrival Time	9.434
Data Required Time	9.532
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/swap32_in_9_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/dpp_crc_good_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R18C24[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/swap32_in_9_s0/CLK
1.937	0.344	tC2Q	RR	22	R18C24[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/swap32_in_9_s0/Q
3.168	1.231	tNET	RR	1	R16C21[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s319/I3
3.583	0.415	tINS	RR	2	R16C21[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s319/F
4.692	1.109	tNET	RR	1	R16C22[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s186/I3
5.166	0.474	tINS	RR	1	R16C22[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s186/F
5.998	0.833	tNET	RR	1	R13C22[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s66/I0
6.414	0.415	tINS	RR	1	R13C22[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s66/F
6.848	0.434	tNET	RR	1	R14C21[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s18/I1
7.321	0.474	tINS	RR	1	R14C21[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s18/F
7.666	0.344	tNET	RR	1	R16C23[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s5/I1
8.113	0.448	tINS	RR	1	R16C23[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s5/F
8.961	0.847	tNET	RR	1	R16C26[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s1/I3
9.434	0.474	tINS	RR	1	R16C26[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n11891_s1/F
9.434	0.000	tNET	RR	1	R16C26[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/dpp_crc_good_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.590	1.590	tNET	RR	1	R16C26[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/dpp_crc_good_s0/CLK
9.532	-0.057	tSu		1	R16C26[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/dpp_crc_good_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 2.699, 34.419%; route: 4.798, 61.191%; tC2Q: 0.344, 4.390%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.590, 100.000%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	9.113
Data Required Time	9.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
9.113	0.907	tNET	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CLK
9.302	-0.280	tSu		1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 40.844%; route: 4.104, 54.578%; tC2Q: 0.344, 4.578%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	9.113
Data Required Time	9.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
9.113	0.907	tNET	RR	1	R32C12[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1/CLK
9.302	-0.280	tSu		1	R32C12[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_3_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 40.844%; route: 4.104, 54.578%; tC2Q: 0.344, 4.578%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path4

Path Summary:

Slack	0.190
Data Arrival Time	9.113
Data Required Time	9.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
9.113	0.907	tNET	RR	1	R32C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1/CLK
9.302	-0.280	tSu		1	R32C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_4_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 40.844%; route: 4.104, 54.578%; tC2Q: 0.344, 4.578%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path5

Path Summary:

Slack	0.190
Data Arrival Time	9.113
Data Required Time	9.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
9.113	0.907	tNET	RR	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CLK
9.302	-0.280	tSu		1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 40.844%; route: 4.104, 54.578%; tC2Q: 0.344, 4.578%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path6

Path Summary:

Slack	0.663
Data Arrival Time	8.645
Data Required Time	9.308
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
8.645	0.439	tNET	RR	1	R33C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.588	1.588	tNET	RR	1	R33C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1/CLK
9.308	-0.280	tSu		1	R33C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_1_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 43.555%; route: 3.636, 51.563%; tC2Q: 0.344, 4.882%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.588, 100.000%

Path7

Path Summary:

Slack	0.663
Data Arrival Time	8.645
Data Required Time	9.308
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
8.645	0.439	tNET	RR	1	R33C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.588	1.588	tNET	RR	1	R33C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1/CLK
9.308	-0.280	tSu		1	R33C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_2_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 43.555%; route: 3.636, 51.563%; tC2Q: 0.344, 4.882%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.588, 100.000%

Path8

Path Summary:

Slack	0.790
Data Arrival Time	8.744
Data Required Time	9.534
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/I3
8.206	0.448	tINS	FR	7	R32C12[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s3/F
8.744	0.538	tNET	RR	1	R32C13[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.591	1.591	tNET	RR	1	R32C13[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0/CLK
9.534	-0.057	tSu		1	R32C13[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/lfps_detect1_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.071, 42.952%; route: 3.735, 52.234%; tC2Q: 0.344, 4.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.591, 100.000%

Path9

Path Summary:

Slack	0.826
Data Arrival Time	8.714
Data Required Time	9.540
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_0_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.595	1.595	tNET	RR	1	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/CLK
1.926	0.331	tC2Q	RF	103	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q
3.368	1.442	tNET	FF	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/I2
3.837	0.469	tINS	FR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/F
3.837	0.000	tNET	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/I1
3.960	0.123	tINS	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/O
3.960	0.000	tNET	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/I0
4.038	0.078	tINS	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/O
4.038	0.000	tNET	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/I0
4.115	0.078	tINS	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/O
4.115	0.000	tNET	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/I1
4.193	0.078	tINS	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/O
4.885	0.692	tNET	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/I0
5.358	0.474	tINS	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/F
5.361	0.002	tNET	RR	1	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/I2
5.825	0.465	tINS	RR	3	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/F
6.165	0.340	tNET	RR	1	R25C46[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2287_s3/I1
6.401	0.236	tINS	RR	3	R25C46[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2287_s3/F
6.718	0.317	tNET	RR	1	R24C45[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s27/I3
7.166	0.448	tINS	RR	1	R24C45[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s27/F
7.290	0.124	tNET	RR	1	R24C45[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s24/I1
7.764	0.474	tINS	RR	2	R24C45[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s24/F
8.250	0.486	tNET	RR	1	R26C43[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2450_s22/I1
8.714	0.465	tINS	RR	1	R26C43[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2450_s22/F
8.714	0.000	tNET	RR	1	R26C43[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R26C43[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_0_s2/CLK
9.540	-0.057	tSu		1	R26C43[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_0_s2

Path Statistics:

Clock Skew	0.003
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.595, 100.000%
Arrival Data Path Delay	cell: 3.385, 47.551%; route: 3.403, 47.803%; tC2Q: 0.331, 4.646%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path10

Path Summary:

Slack	0.876
Data Arrival Time	8.665
Data Required Time	9.540
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_3_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.595	1.595	tNET	RR	1	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/CLK
1.926	0.331	tC2Q	RF	103	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q
3.368	1.442	tNET	FF	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/I2
3.837	0.469	tINS	FR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/F
3.837	0.000	tNET	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/I1
3.960	0.123	tINS	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/O
3.960	0.000	tNET	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/I0
4.038	0.078	tINS	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/O
4.038	0.000	tNET	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/I0
4.115	0.078	tINS	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/O
4.115	0.000	tNET	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/I1
4.193	0.078	tINS	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/O
4.885	0.692	tNET	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/I0
5.358	0.474	tINS	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/F
5.361	0.002	tNET	RR	1	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/I2
5.825	0.465	tINS	RR	3	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/F
6.165	0.340	tNET	RR	1	R25C46[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2287_s3/I1
6.401	0.236	tINS	RR	3	R25C46[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2287_s3/F
6.718	0.317	tNET	RR	1	R24C45[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s27/I3
7.166	0.448	tINS	RR	1	R24C45[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s27/F
7.290	0.124	tNET	RR	1	R24C45[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s24/I1
7.764	0.474	tINS	RR	2	R24C45[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s24/F
8.250	0.486	tNET	RR	1	R26C43[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s23/I0
8.665	0.415	tINS	RR	1	R26C43[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2442_s23/F
8.665	0.000	tNET	RR	1	R26C43[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R26C43[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_3_s2/CLK
9.540	-0.057	tSu		1	R26C43[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_3_s2

Path Statistics:

Clock Skew	0.003
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.595, 100.000%
Arrival Data Path Delay	cell: 3.336, 47.183%; route: 3.403, 48.138%; tC2Q: 0.331, 4.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path11

Path Summary:

Slack	1.147
Data Arrival Time	8.394
Data Required Time	9.540
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_1_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.595	1.595	tNET	RR	1	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/CLK
1.926	0.331	tC2Q	RF	103	R29C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_send_pt_0_s1/Q
3.368	1.442	tNET	FF	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/I2
3.837	0.469	tINS	FR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s289/F
3.837	0.000	tNET	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/I1
3.960	0.123	tINS	RR	1	R30C50[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s252/O
3.960	0.000	tNET	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/I0
4.038	0.078	tINS	RR	1	R30C50[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s234/O
4.038	0.000	tNET	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/I0
4.115	0.078	tINS	RR	1	R30C50[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s225/O
4.115	0.000	tNET	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/I1
4.193	0.078	tINS	RR	1	R30C50[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/transfer_in_pkt_ready_s220/O
4.885	0.692	tNET	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/I0
5.358	0.474	tINS	RR	1	R26C48[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s4/F
5.361	0.002	tNET	RR	1	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/I2
5.825	0.465	tINS	RR	3	R26C48[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2289_s3/F
6.334	0.508	tNET	RR	1	R24C45[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s29/I0
6.749	0.415	tINS	RR	1	R24C45[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s29/F
6.751	0.002	tNET	RR	1	R24C45[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s26/I2
6.987	0.236	tINS	RR	2	R24C45[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s26/F
7.163	0.175	tNET	RR	1	R24C43[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s24/I2
7.424	0.261	tINS	RF	3	R24C43[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2445_s24/F
7.557	0.133	tNET	FF	1	R25C43[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2447_s29/I1
7.818	0.261	tINS	FF	1	R25C43[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2447_s29/F
7.946	0.128	tNET	FF	1	R26C43[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2447_s28/I0
8.394	0.448	tINS	FR	1	R26C43[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n2447_s28/F
8.394	0.000	tNET	RR	1	R26C43[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R26C43[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_1_s2/CLK
9.540	-0.057	tSu		1	R26C43[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/tx_state_1_s2

Path Statistics:

Clock Skew	0.003
Setup Relationship	8.000
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.595, 100.000%
Arrival Data Path Delay	cell: 3.384, 49.777%; route: 3.084, 45.358%; tC2Q: 0.331, 4.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path12

Path Summary:

Slack	1.221
Data Arrival Time	8.112
Data Required Time	9.333
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_2_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.591	1.591	tNET	RR	1	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/CLK
1.936	0.344	tC2Q	RR	2	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q
2.766	0.830	tNET	RR	1	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/I2
3.230	0.465	tINS	RR	2	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/F
4.445	1.215	tNET	RR	1	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/I0
4.915	0.469	tINS	RR	2	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/F
6.076	1.161	tNET	RR	1	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/I1
6.491	0.415	tINS	RR	5	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/F
7.232	0.741	tNET	RR	1	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/I2
7.606	0.373	tINS	RR	3	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/F
8.112	0.506	tNET	RR	1	R21C35[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.613	1.613	tNET	RR	1	R21C35[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_2_s1/CLK
9.333	-0.280	tSu		1	R21C35[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_2_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.591, 100.000%
Arrival Data Path Delay	cell: 1.722, 26.415%; route: 4.454, 68.306%; tC2Q: 0.344, 5.280%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.613, 100.000%

Path13

Path Summary:

Slack	1.239
Data Arrival Time	8.078
Data Required Time	9.316
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R18C42[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/CLK
1.924	0.331	tC2Q	RF	34	R18C42[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/Q
2.329	0.405	tNET	FF	1	R17C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n6922_s4/I3
2.793	0.465	tINS	FR	21	R17C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n6922_s4/F
3.706	0.912	tNET	RR	1	R22C48[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n412_s2/I2
4.050	0.344	tINS	RF	81	R22C48[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n412_s2/F
4.992	0.942	tNET	FF	1	R15C42[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1759_s2/I2
5.228	0.236	tINS	FR	5	R15C42[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1759_s2/F
5.527	0.299	tNET	RR	1	R15C44[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1675_s0/I2
6.001	0.474	tINS	RR	2	R15C44[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1675_s0/F
7.013	1.013	tNET	RR	1	R20C49[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s4/I0
7.487	0.474	tINS	RR	2	R20C49[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s4/F
8.078	0.591	tNET	RR	1	R15C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.596	1.596	tNET	RR	1	R15C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s1/CLK
9.316	-0.280	tSu		1	R15C49[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 1.992, 30.725%; route: 4.161, 64.174%; tC2Q: 0.331, 5.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.596, 100.000%

Path14

Path Summary:

Slack	1.259
Data Arrival Time	8.035
Data Required Time	9.294
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_43_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.600	1.600	tNET	RR	1	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/CLK
1.931	0.331	tC2Q	RF	53	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q
2.307	0.377	tNET	FF	1	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/I2
2.722	0.415	tINS	FR	8	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/F
3.280	0.558	tNET	RR	1	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/I2
3.754	0.474	tINS	RR	71	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/F
4.516	0.762	tNET	RR	1	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/I0
4.889	0.373	tINS	RR	19	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/F
5.395	0.506	tNET	RR	1	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/I3
5.860	0.465	tINS	RR	9	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/F
6.344	0.484	tNET	RR	1	R27C50[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3798_s1/I3
6.759	0.415	tINS	RR	5	R27C50[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3798_s1/F
7.496	0.737	tNET	RR	1	R32C51[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s4/I0
7.911	0.415	tINS	RR	2	R32C51[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s4/F
8.035	0.124	tNET	RR	1	R32C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_43_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.574	1.574	tNET	RR	1	R32C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_43_s1/CLK
9.294	-0.280	tSu		1	R32C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_43_s1

Path Statistics:

Clock Skew	-0.026
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%
Arrival Data Path Delay	cell: 2.557, 39.738%; route: 3.547, 55.122%; tC2Q: 0.331, 5.140%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.574, 100.000%

Path15

Path Summary:

Slack	1.259
Data Arrival Time	8.035
Data Required Time	9.294
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.600	1.600	tNET	RR	1	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/CLK
1.931	0.331	tC2Q	RF	53	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q
2.307	0.377	tNET	FF	1	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/I2
2.722	0.415	tINS	FR	8	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/F
3.280	0.558	tNET	RR	1	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/I2
3.754	0.474	tINS	RR	71	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/F
4.516	0.762	tNET	RR	1	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/I0
4.889	0.373	tINS	RR	19	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/F
5.395	0.506	tNET	RR	1	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/I3
5.860	0.465	tINS	RR	9	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/F
6.344	0.484	tNET	RR	1	R27C50[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3798_s1/I3
6.759	0.415	tINS	RR	5	R27C50[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3798_s1/F
7.496	0.737	tNET	RR	1	R32C51[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s4/I0
7.911	0.415	tINS	RR	2	R32C51[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s4/F
8.035	0.124	tNET	RR	1	R32C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.574	1.574	tNET	RR	1	R32C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s1/CLK
9.294	-0.280	tSu		1	R32C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_43_s1

Path Statistics:

Clock Skew	-0.026
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%
Arrival Data Path Delay	cell: 2.557, 39.738%; route: 3.547, 55.122%; tC2Q: 0.331, 5.140%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.574, 100.000%

Path16

Path Summary:

Slack	1.272
Data Arrival Time	8.264
Data Required Time	9.536
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_20_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1
Launch Clk	fabric_rx_clk:[R]
Latch Clk	fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					fabric_rx_clk
0.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
1.587	1.587	tNET	RR	1	R38C13[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_20_s0/CLK
1.931	0.344	tC2Q	RR	12	R38C13[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/data_in_r0_20_s0/Q
2.567	0.636	tNET	RR	1	R36C10[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s30/I1
2.982	0.415	tINS	RR	2	R36C10[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s30/F
3.297	0.315	tNET	RR	1	R36C9[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s11/I3
3.761	0.465	tINS	RR	1	R36C9[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s11/F
4.425	0.664	tNET	RR	1	R36C8[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s5/I0
4.799	0.373	tINS	RR	4	R36C8[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_3_s5/F
5.191	0.393	tNET	RR	1	R39C8[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n751_s11/I2
5.665	0.474	tINS	RR	2	R39C8[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n751_s11/F
5.669	0.005	tNET	RR	1	R39C8[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s15/I3
6.134	0.465	tINS	RR	1	R39C8[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s15/F
6.520	0.386	tNET	RR	1	R36C8[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s8/I0
6.935	0.415	tINS	RR	1	R36C8[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s8/F
7.525	0.590	tNET	RR	1	R36C5[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s4/I0
7.786	0.261	tINS	RF	1	R36C5[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s4/F
7.790	0.005	tNET	FF	1	R36C5[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s3/I0
8.264	0.474	tINS	FR	1	R36C5[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/n762_s3/F
8.264	0.000	tNET	RR	1	R36C5[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					fabric_rx_clk
8.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
9.593	1.593	tNET	RR	1	R36C5[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1/CLK
9.536	-0.057	tSu		1	R36C5[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_word_alignment/cnt0_1_s1

Path Statistics:

Clock Skew	0.006
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.587, 100.000%
Arrival Data Path Delay	cell: 3.341, 50.042%; route: 2.991, 44.802%; tC2Q: 0.344, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%

Path17

Path Summary:

Slack	1.294
Data Arrival Time	8.232
Data Required Time	9.525
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/CLK
1.937	0.344	tC2Q	RR	1	R36C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[1]_34_s0/Q
2.529	0.592	tNET	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/I1
2.998	0.469	tINS	RR	1	R36C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s19/F
3.415	0.417	tNET	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/I3
3.652	0.236	tINS	RR	1	R38C12[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s14/F
3.654	0.002	tNET	RR	1	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/I3
4.128	0.474	tINS	RR	2	R38C12[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s11/F
4.272	0.144	tNET	RR	1	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/I1
4.745	0.474	tINS	RR	5	R38C13[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1173_s8/F
5.172	0.426	tNET	RR	1	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/I2
5.408	0.236	tINS	RR	14	R35C13[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s34/F
5.968	0.560	tNET	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/I1
6.442	0.474	tINS	RR	1	R38C14[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s16/F
7.030	0.588	tNET	RR	1	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/I0
7.291	0.261	tINS	RF	2	R35C13[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s7/F
7.758	0.467	tNET	FF	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1003_s2/I3
8.232	0.474	tINS	FR	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1003_s2/F
8.232	0.000	tNET	RR	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1/CLK
9.525	-0.057	tSu		1	R32C12[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 3.097, 46.653%; route: 3.197, 48.161%; tC2Q: 0.344, 5.186%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path18

Path Summary:

Slack	1.296
Data Arrival Time	7.993
Data Required Time	9.289
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_18_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.593	1.593	tNET	RR	1	R18C42[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/CLK
1.924	0.331	tC2Q	RF	34	R18C42[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_1_s1/Q
2.329	0.405	tNET	FF	1	R17C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n6922_s4/I3
2.793	0.465	tINS	FR	21	R17C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n6922_s4/F
3.706	0.912	tNET	RR	1	R22C48[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n412_s2/I2
4.050	0.344	tINS	RF	81	R22C48[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n412_s2/F
4.992	0.942	tNET	FF	1	R15C42[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1759_s2/I2
5.228	0.236	tINS	FR	5	R15C42[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1759_s2/F
5.527	0.299	tNET	RR	1	R15C44[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1675_s0/I2
6.001	0.474	tINS	RR	2	R15C44[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n1675_s0/F
7.013	1.013	tNET	RR	1	R20C49[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s4/I0
7.487	0.474	tINS	RR	2	R20C49[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_18_s4/F
7.993	0.506	tNET	RR	1	R13C47[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_18_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.569	1.569	tNET	RR	1	R13C47[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_18_s1/CLK
9.289	-0.280	tSu		1	R13C47[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_18_s1

Path Statistics:

Clock Skew	-0.024
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.593, 100.000%
Arrival Data Path Delay	cell: 1.992, 31.130%; route: 4.077, 63.702%; tC2Q: 0.331, 5.168%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.569, 100.000%

Path19

Path Summary:

Slack	1.307
Data Arrival Time	7.991
Data Required Time	9.298
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_41_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.600	1.600	tNET	RR	1	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/CLK
1.931	0.331	tC2Q	RF	53	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q
2.307	0.377	tNET	FF	1	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/I2
2.722	0.415	tINS	FR	8	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/F
3.280	0.558	tNET	RR	1	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/I2
3.754	0.474	tINS	RR	71	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/F
4.516	0.762	tNET	RR	1	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/I0
4.889	0.373	tINS	RR	19	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/F
5.395	0.506	tNET	RR	1	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/I3
5.860	0.465	tINS	RR	9	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/F
6.191	0.331	tNET	RR	1	R26C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3628_s0/I2
6.606	0.415	tINS	RR	3	R26C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3628_s0/F
7.393	0.787	tNET	RR	1	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s4/I0
7.867	0.474	tINS	RR	2	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s4/F
7.991	0.124	tNET	RR	1	R29C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_41_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.578	1.578	tNET	RR	1	R29C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_41_s1/CLK
9.298	-0.280	tSu		1	R29C51[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_last_41_s1

Path Statistics:

Clock Skew	-0.021
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%
Arrival Data Path Delay	cell: 2.616, 40.926%; route: 3.445, 53.899%; tC2Q: 0.331, 5.175%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.578, 100.000%

Path20

Path Summary:

Slack	1.307
Data Arrival Time	7.991
Data Required Time	9.298
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.600	1.600	tNET	RR	1	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/CLK
1.931	0.331	tC2Q	RF	53	R27C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_num_4_s1/Q
2.307	0.377	tNET	FF	1	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/I2
2.722	0.415	tINS	FR	8	R26C55[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3119_s2/F
3.280	0.558	tNET	RR	1	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/I2
3.754	0.474	tINS	RR	71	R33C55[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n246_s2/F
4.516	0.762	tNET	RR	1	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/I0
4.889	0.373	tINS	RR	19	R27C55[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n5604_s0/F
5.395	0.506	tNET	RR	1	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/I3
5.860	0.465	tINS	RR	9	R25C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n4228_s3/F
6.191	0.331	tNET	RR	1	R26C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3628_s0/I2
6.606	0.415	tINS	RR	3	R26C54[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/n3628_s0/F
7.393	0.787	tNET	RR	1	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s4/I0
7.867	0.474	tINS	RR	2	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s4/F
7.991	0.124	tNET	RR	1	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.578	1.578	tNET	RR	1	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s1/CLK
9.298	-0.280	tSu		1	R29C51[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/pkt_ready_41_s1

Path Statistics:

Clock Skew	-0.021
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%
Arrival Data Path Delay	cell: 2.616, 40.926%; route: 3.445, 53.899%; tC2Q: 0.331, 5.175%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.578, 100.000%

Path21

Path Summary:

Slack	1.326
Data Arrival Time	7.994
Data Required Time	9.320
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.591	1.591	tNET	RR	1	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/CLK
1.936	0.344	tC2Q	RR	2	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q
2.766	0.830	tNET	RR	1	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/I2
3.230	0.465	tINS	RR	2	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/F
4.445	1.215	tNET	RR	1	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/I0
4.915	0.469	tINS	RR	2	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/F
6.076	1.161	tNET	RR	1	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/I1
6.491	0.415	tINS	RR	5	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/F
7.232	0.741	tNET	RR	1	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/I2
7.606	0.373	tINS	RR	3	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/F
7.994	0.388	tNET	RR	1	R27C34[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.600	1.600	tNET	RR	1	R27C34[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_0_s1/CLK
9.320	-0.280	tSu		1	R27C34[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_0_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	8.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.591, 100.000%
Arrival Data Path Delay	cell: 1.722, 26.902%; route: 4.336, 67.721%; tC2Q: 0.344, 5.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%

Path22

Path Summary:

Slack	1.326
Data Arrival Time	7.994
Data Required Time	9.320
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.591	1.591	tNET	RR	1	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/CLK
1.936	0.344	tC2Q	RR	2	R17C34[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/in_header_cw_9_s0/Q
2.766	0.830	tNET	RR	1	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/I2
3.230	0.465	tINS	RR	2	R17C34[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s9/F
4.445	1.215	tNET	RR	1	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/I0
4.915	0.469	tINS	RR	2	R17C35[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/err_lbad_s33/F
6.076	1.161	tNET	RR	1	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/I1
6.491	0.415	tINS	RR	5	R18C34[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s4/F
7.232	0.741	tNET	RR	1	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/I2
7.606	0.373	tINS	RR	3	R30C34[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/n12502_s0/F
7.994	0.388	tNET	RR	1	R27C34[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.600	1.600	tNET	RR	1	R27C34[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_1_s1/CLK
9.320	-0.280	tSu		1	R27C34[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_hdr_seq_num_1_s1

Path Statistics:

Clock Skew	0.008
Setup Relationship	8.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.591, 100.000%
Arrival Data Path Delay	cell: 1.722, 26.902%; route: 4.336, 67.721%; tC2Q: 0.344, 5.377%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%

Path23

Path Summary:

Slack	1.357
Data Arrival Time	8.169
Data Required Time	9.525
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.600	1.600	tNET	RR	1	R35C13[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/CLK
1.944	0.344	tC2Q	RR	6	R35C13[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/rx_data_r[0]_20_s0/Q
2.419	0.475	tNET	RR	1	R33C15[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s42/I1
2.892	0.474	tINS	RR	6	R33C15[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s42/F
3.486	0.594	tNET	RR	1	R38C15[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s26/I3
3.860	0.373	tINS	RR	5	R38C15[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s26/F
4.423	0.564	tNET	RR	1	R36C14[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s43/I1
4.684	0.261	tINS	RF	2	R36C14[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_5_s43/F
4.693	0.009	tNET	FF	1	R36C14[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s19/I1
5.167	0.474	tINS	FR	2	R36C14[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1217_s19/F
5.555	0.388	tNET	RR	1	R38C14[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s27/I2
6.003	0.448	tINS	RR	1	R38C14[3][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s27/F
6.005	0.002	tNET	RR	1	R38C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s16/I3
6.453	0.448	tINS	RR	1	R38C14[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s16/F
6.626	0.173	tNET	RR	1	R38C13[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s6/I1
7.041	0.415	tINS	RR	1	R38C13[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s6/F
7.704	0.663	tNET	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s3/I2
8.169	0.465	tINS	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/n1225_s3/F
8.169	0.000	tNET	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.583	1.583	tNET	RR	1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1/CLK
9.525	-0.057	tSu		1	R32C12[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_usb3_lfps_detector/cnt3_0_s1

Path Statistics:

Clock Skew	-0.017
Setup Relationship	8.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.600, 100.000%
Arrival Data Path Delay	cell: 3.357, 51.105%; route: 2.868, 43.655%; tC2Q: 0.344, 5.241%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.583, 100.000%

Path24

Path Summary:

Slack	1.377
Data Arrival Time	7.945
Data Required Time	9.321
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_last_86_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.579	1.579	tNET	RR	1	R15C55[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/CLK
1.924	0.344	tC2Q	RR	36	R15C55[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/Q
2.393	0.469	tNET	RR	1	R13C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n6922_s2/I0
2.808	0.415	tINS	RR	23	R13C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n6922_s2/F
3.010	0.202	tNET	RR	1	R15C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n1928_s1/I1
3.475	0.465	tINS	RR	20	R15C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n1928_s1/F
4.139	0.664	tNET	RR	1	R18C55[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n2184_s1/I0
4.587	0.448	tINS	RR	9	R18C55[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n2184_s1/F
5.491	0.904	tNET	RR	1	R23C52[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7648_s0/I1
5.865	0.373	tINS	RR	3	R23C52[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7648_s0/F
6.011	0.146	tNET	RR	1	R22C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7475_s0/I3
6.484	0.474	tINS	RR	3	R22C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7475_s0/F
6.973	0.488	tNET	RR	1	R21C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s4/I0
7.437	0.465	tINS	RR	2	R21C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s4/F
7.945	0.507	tNET	RR	1	R18C49[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_last_86_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.601	1.601	tNET	RR	1	R18C49[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_last_86_s1/CLK
9.321	-0.280	tSu		1	R18C49[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_last_86_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.579, 100.000%
Arrival Data Path Delay	cell: 2.639, 41.463%; route: 3.382, 53.128%; tC2Q: 0.344, 5.408%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.601, 100.000%

Path25

Path Summary:

Slack	1.377
Data Arrival Time	7.945
Data Required Time	9.321
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
1.579	1.579	tNET	RR	1	R15C55[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/CLK
1.924	0.344	tC2Q	RR	36	R15C55[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_num_0_s1/Q
2.393	0.469	tNET	RR	1	R13C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n6922_s2/I0
2.808	0.415	tINS	RR	23	R13C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n6922_s2/F
3.010	0.202	tNET	RR	1	R15C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n1928_s1/I1
3.475	0.465	tINS	RR	20	R15C55[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n1928_s1/F
4.139	0.664	tNET	RR	1	R18C55[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n2184_s1/I0
4.587	0.448	tINS	RR	9	R18C55[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n2184_s1/F
5.491	0.904	tNET	RR	1	R23C52[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7648_s0/I1
5.865	0.373	tINS	RR	3	R23C52[3][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7648_s0/F
6.011	0.146	tNET	RR	1	R22C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7475_s0/I3
6.484	0.474	tINS	RR	3	R22C52[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/n7475_s0/F
6.973	0.488	tNET	RR	1	R21C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s4/I0
7.437	0.465	tINS	RR	2	R21C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s4/F
7.945	0.507	tNET	RR	1	R18C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.601	1.601	tNET	RR	1	R18C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s1/CLK
9.321	-0.280	tSu		1	R18C49[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[1].transfer_in_mem_inst/pkt_ready_86_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.579, 100.000%
Arrival Data Path Delay	cell: 2.639, 41.463%; route: 3.382, 53.128%; tC2Q: 0.344, 5.408%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.601, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.165
Data Arrival Time	0.857
Data Required Time	0.692
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R31C38[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_2_s0/CLK
0.773	0.130	tC2Q	RR	1	R31C38[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_2_s0/Q
0.857	0.084	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/CLK
0.692	0.045	tHld		1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%

Path2

Path Summary:

Slack	0.165
Data Arrival Time	0.857
Data Required Time	0.692
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R31C38[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_1_s0/CLK
0.773	0.130	tC2Q	RR	1	R31C38[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_1_s0/Q
0.857	0.084	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/CLK
0.692	0.045	tHld		1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%

Path3

Path Summary:

Slack	0.165
Data Arrival Time	0.857
Data Required Time	0.692
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_0_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R31C38[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_0_s0/CLK
0.773	0.130	tC2Q	RR	1	R31C38[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/tx_lgood_0_s0/Q
0.857	0.084	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/CLK
0.692	0.045	tHld		1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%

Path4

Path Summary:

Slack	0.167
Data Arrival Time	0.864
Data Required Time	0.697
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.648	0.648	tNET	RR	1	R34C39[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_1_s0/CLK
0.778	0.130	tC2Q	RR	4	R34C39[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_1_s0/Q
0.864	0.086	tNET	RR	1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/CLK
0.697	0.045	tHld		1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.648, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.086, 40.000%; tC2Q: 0.130, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path5

Path Summary:

Slack	0.169
Data Arrival Time	0.868
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.650	0.650	tNET	RR	1	R36C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_2_s0/CLK
0.780	0.130	tC2Q	RR	3	R36C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/wr_pt_2_s0/Q
0.868	0.088	tNET	RR	1	R36C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R36C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R36C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLau_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.650, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.088, 40.496%; tC2Q: 0.130, 59.504%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path6

Path Summary:

Slack	0.170
Data Arrival Time	0.867
Data Required Time	0.697
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.648	0.648	tNET	RR	1	R34C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_2_s0/CLK
0.778	0.130	tC2Q	RR	3	R34C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/wr_pt_2_s0/Q
0.867	0.089	tNET	RR	1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s/CLK
0.697	0.045	tHld		1	R34C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLpma_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.648, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path7

Path Summary:

Slack	0.170
Data Arrival Time	0.869
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.651	0.651	tNET	RR	1	R32C37[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/CLK
0.780	0.130	tC2Q	RR	3	R32C37[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_2_s0/Q
0.869	0.089	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.651, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path8

Path Summary:

Slack	0.172
Data Arrival Time	0.864
Data Required Time	0.692
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R32C39[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_1_s0/CLK
0.773	0.130	tC2Q	RR	4	R32C39[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/wr_pt_1_s0/Q
0.864	0.091	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s/CLK
0.692	0.045	tHld		1	R32C38	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLgood_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.091, 41.224%; tC2Q: 0.130, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%

Path9

Path Summary:

Slack	0.173
Data Arrival Time	0.872
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R35C36[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/CLK
0.783	0.130	tC2Q	RR	3	R35C36[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_2_s0/Q
0.872	0.089	tNET	RR	1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path10

Path Summary:

Slack	0.173
Data Arrival Time	0.872
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.651	0.651	tNET	RR	1	R32C37[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/CLK
0.780	0.130	tC2Q	RR	4	R32C37[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_1_s0/Q
0.872	0.092	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.651, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.092, 41.463%; tC2Q: 0.130, 58.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path11

Path Summary:

Slack	0.174
Data Arrival Time	0.873
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_0_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.651	0.651	tNET	RR	1	R32C37[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_0_s0/CLK
0.780	0.130	tC2Q	RR	5	R32C37[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/wr_pt_0_s0/Q
0.873	0.093	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R33C37	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLcrd_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.651, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 41.700%; tC2Q: 0.130, 58.300%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path12

Path Summary:

Slack	0.175
Data Arrival Time	0.871
Data Required Time	0.697
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.655	0.655	tNET	RR	1	R34C37[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_2_s0/CLK
0.785	0.130	tC2Q	RR	3	R34C37[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_2_s0/Q
0.871	0.086	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/CLK
0.697	0.045	tHld		1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.655, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.086, 40.000%; tC2Q: 0.130, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path13

Path Summary:

Slack	0.175
Data Arrival Time	0.873
Data Required Time	0.698
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_2_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.640	0.640	tNET	RR	1	R31C31[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_pt_1_s0/CLK
0.769	0.130	tC2Q	RR	10	R31C31[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_pt_1_s0/Q
0.873	0.103	tNET	RR	1	R35C30	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_2_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R35C30	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_2_s/CLK
0.698	0.045	tHld		1	R35C30	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_wr_cnt_res_mem_wr_cnt_0_2_s

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.640, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.402%; tC2Q: 0.130, 55.598%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%

Path14

Path Summary:

Slack	0.175
Data Arrival Time	0.874
Data Required Time	0.699
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R35C36[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s0/CLK
0.783	0.130	tC2Q	RR	4	R35C36[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/wr_pt_1_s0/Q
0.874	0.092	tNET	RR	1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.654	0.654	tNET	RR	1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s/CLK
0.699	0.045	tHld		1	R36C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLbad_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.092, 41.463%; tC2Q: 0.130, 58.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.654, 100.000%

Path15

Path Summary:

Slack	0.177
Data Arrival Time	0.866
Data Required Time	0.688
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_2_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C36[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_2_s0/CLK
0.777	0.130	tC2Q	RR	3	R32C36[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_2_s0/Q
0.866	0.089	tNET	RR	1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/WAD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/CLK
0.688	0.045	tHld		1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%

Path16

Path Summary:

Slack	0.179
Data Arrival Time	0.876
Data Required Time	0.697
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_0_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.655	0.655	tNET	RR	1	R34C37[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_0_s0/CLK
0.785	0.130	tC2Q	RR	5	R34C37[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_0_s0/Q
0.876	0.091	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/CLK
0.697	0.045	tHld		1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.655, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.091, 41.224%; tC2Q: 0.130, 58.776%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path17

Path Summary:

Slack	0.180
Data Arrival Time	0.868
Data Required Time	0.688
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_0_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.647	0.647	tNET	RR	1	R32C36[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_0_s0/CLK
0.777	0.130	tC2Q	RR	5	R32C36[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/wr_pt_0_s0/Q
0.868	0.092	tNET	RR	1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/WAD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.643	0.643	tNET	RR	1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s/CLK
0.688	0.045	tHld		1	R31C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLtry_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.647, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.092, 41.463%; tC2Q: 0.130, 58.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.643, 100.000%

Path18

Path Summary:

Slack	0.180
Data Arrival Time	0.877
Data Required Time	0.697
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.655	0.655	tNET	RR	1	R34C37[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_1_s0/CLK
0.785	0.130	tC2Q	RR	4	R34C37[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/wr_pt_1_s0/Q
0.877	0.092	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s/CLK
0.697	0.045	tHld		1	R34C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TXLup_cache/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.655, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.092, 41.463%; tC2Q: 0.130, 58.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path19

Path Summary:

Slack	0.184
Data Arrival Time	0.873
Data Required Time	0.689
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_6_s2
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
Launch Clk	fabric_rx_clk:[R]
Latch Clk	fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					fabric_rx_clk
0.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.657	0.657	tNET	RR	1	R27C9[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_6_s2/CLK
0.787	0.130	tC2Q	RR	2	R27C9[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_6_s2/Q
0.873	0.086	tNET	RR	1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					fabric_rx_clk
0.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.656	0.656	tNET	RR	1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA
0.689	0.033	tHld		1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.657, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.086, 40.000%; tC2Q: 0.130, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.656, 100.000%

Path20

Path Summary:

Slack	0.184
Data Arrival Time	0.902
Data Required Time	0.717
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_3_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.676	0.676	tNET	RR	1	R21C33[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/CLK
0.805	0.130	tC2Q	RR	10	R21C33[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/wr_pt_1_s0/Q
0.902	0.096	tNET	RR	1	R21C34	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_3_s/WAD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.672	0.672	tNET	RR	1	R21C34	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_3_s/CLK
0.717	0.045	tHld		1	R21C34	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_3_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.096, 42.629%; tC2Q: 0.130, 57.371%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.672, 100.000%

Path21

Path Summary:

Slack	0.185
Data Arrival Time	0.874
Data Required Time	0.689
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_12_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s
Launch Clk	fabric_rx_clk:[R]
Latch Clk	fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					fabric_rx_clk
0.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.661	0.661	tNET	RR	1	R27C8[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_12_s0/CLK
0.790	0.130	tC2Q	RR	1	R27C8[2][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_elastic_buffer/coll_data_12_s0/Q
0.874	0.084	tNET	RR	1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					fabric_rx_clk
0.000	0.000	tCL	RR	519	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
0.656	0.656	tNET	RR	1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA
0.689	0.033	tHld		1	BSRAM_R28[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.661, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.656, 100.000%

Path22

Path Summary:

Slack	0.185
Data Arrival Time	0.870
Data Required Time	0.686
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.657	0.657	tNET	RR	1	R9C8[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK
0.787	0.130	tC2Q	RR	1	R9C8[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q
0.870	0.084	tNET	RR	1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.686	0.033	tHld		1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.657, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Path23

Path Summary:

Slack	0.187
Data Arrival Time	0.901
Data Required Time	0.714
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_24_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.669	0.669	tNET	RR	1	R23C38[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_24_s0/CLK
0.799	0.130	tC2Q	RR	1	R23C38[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_24_s0/Q
0.901	0.103	tNET	RR	1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.669	0.669	tNET	RR	1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/CLK
0.714	0.045	tHld		1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path24

Path Summary:

Slack	0.187
Data Arrival Time	0.901
Data Required Time	0.714
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_23_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.669	0.669	tNET	RR	1	R23C38[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_23_s0/CLK
0.799	0.130	tC2Q	RR	1	R23C38[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_word_1_23_s0/Q
0.901	0.103	tNET	RR	1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.669	0.669	tNET	RR	1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s/CLK
0.714	0.045	tHld		1	R23C36	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/usb3_TxHp_inst/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.669, 100.000%

Path25

Path Summary:

Slack	0.188
Data Arrival Time	0.874
Data Required Time	0.686
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.661	0.661	tNET	RR	1	R9C9[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
0.790	0.130	tC2Q	RR	1	R9C9[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
0.874	0.084	tNET	RR	1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.686	0.033	tHld		1	BSRAM_R10[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.661, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.410
Data Arrival Time	6.883
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.883	0.868	tNET	FF	1	R8C8[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C8[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
9.293	-0.313	tSu		1	R8C8[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.868, 68.561%; tC2Q: 0.398, 31.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path2

Path Summary:

Slack	2.410
Data Arrival Time	6.883
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.883	0.868	tNET	FF	1	R8C8[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C8[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
9.293	-0.313	tSu		1	R8C8[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.868, 68.561%; tC2Q: 0.398, 31.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path3

Path Summary:

Slack	2.410
Data Arrival Time	6.883
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.883	0.868	tNET	FF	1	R8C8[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C8[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
9.293	-0.313	tSu		1	R8C8[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.868, 68.561%; tC2Q: 0.398, 31.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path4

Path Summary:

Slack	2.410
Data Arrival Time	6.883
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.883	0.868	tNET	FF	1	R8C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
9.293	-0.313	tSu		1	R8C8[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.868, 68.561%; tC2Q: 0.398, 31.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path5

Path Summary:

Slack	2.410
Data Arrival Time	6.883
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.883	0.868	tNET	FF	1	R8C8[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C8[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
9.293	-0.313	tSu		1	R8C8[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.868, 68.561%; tC2Q: 0.398, 31.439%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path6

Path Summary:

Slack	2.431
Data Arrival Time	6.862
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.862	0.847	tNET	FF	1	R8C10[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C10[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
9.293	-0.313	tSu		1	R8C10[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.847, 68.022%; tC2Q: 0.398, 31.978%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path7

Path Summary:

Slack	2.431
Data Arrival Time	6.862
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.862	0.847	tNET	FF	1	R8C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
9.293	-0.313	tSu		1	R8C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.847, 68.022%; tC2Q: 0.398, 31.978%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path8

Path Summary:

Slack	2.431
Data Arrival Time	6.862
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.862	0.847	tNET	FF	1	R8C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
9.293	-0.313	tSu		1	R8C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.847, 68.022%; tC2Q: 0.398, 31.978%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path9

Path Summary:

Slack	2.435
Data Arrival Time	6.866
Data Required Time	9.302
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.866	0.852	tNET	FF	1	R8C9[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.615	1.615	tNET	RR	1	R8C9[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
9.302	-0.313	tSu		1	R8C9[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.852, 68.137%; tC2Q: 0.398, 31.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.615, 100.000%

Path10

Path Summary:

Slack	2.435
Data Arrival Time	6.866
Data Required Time	9.302
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.866	0.852	tNET	FF	1	R8C9[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.615	1.615	tNET	RR	1	R8C9[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
9.302	-0.313	tSu		1	R8C9[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.852, 68.137%; tC2Q: 0.398, 31.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.615, 100.000%

Path11

Path Summary:

Slack	2.435
Data Arrival Time	6.866
Data Required Time	9.302
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.866	0.852	tNET	FF	1	R8C9[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.615	1.615	tNET	RR	1	R8C9[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
9.302	-0.313	tSu		1	R8C9[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.852, 68.137%; tC2Q: 0.398, 31.863%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.615, 100.000%

Path12

Path Summary:

Slack	2.541
Data Arrival Time	6.718
Data Required Time	9.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.718	0.703	tNET	FF	1	R12C10[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.572	1.572	tNET	RR	1	R12C10[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
9.259	-0.313	tSu		1	R12C10[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.703, 63.841%; tC2Q: 0.398, 36.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.572, 100.000%

Path13

Path Summary:

Slack	2.541
Data Arrival Time	6.718
Data Required Time	9.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.718	0.703	tNET	FF	1	R12C10[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.572	1.572	tNET	RR	1	R12C10[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
9.259	-0.313	tSu		1	R12C10[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.703, 63.841%; tC2Q: 0.398, 36.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.572, 100.000%

Path14

Path Summary:

Slack	2.541
Data Arrival Time	6.718
Data Required Time	9.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.718	0.703	tNET	FF	1	R12C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.572	1.572	tNET	RR	1	R12C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
9.259	-0.313	tSu		1	R12C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.703, 63.841%; tC2Q: 0.398, 36.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.572, 100.000%

Path15

Path Summary:

Slack	2.541
Data Arrival Time	6.718
Data Required Time	9.259
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.718	0.703	tNET	FF	1	R12C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.572	1.572	tNET	RR	1	R12C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
9.259	-0.313	tSu		1	R12C10[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.703, 63.841%; tC2Q: 0.398, 36.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.572, 100.000%

Path16

Path Summary:

Slack	2.547
Data Arrival Time	6.718
Data Required Time	9.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.718	0.703	tNET	FF	1	R13C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.577	1.577	tNET	RR	1	R13C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
9.264	-0.313	tSu		1	R13C10[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	-0.039
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.703, 63.841%; tC2Q: 0.398, 36.159%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.577, 100.000%

Path17

Path Summary:

Slack	2.554
Data Arrival Time	6.731
Data Required Time	9.285
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.731	0.717	tNET	FF	1	R8C7[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R8C7[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
9.285	-0.313	tSu		1	R8C7[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.717, 64.279%; tC2Q: 0.398, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path18

Path Summary:

Slack	2.554
Data Arrival Time	6.731
Data Required Time	9.285
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.731	0.717	tNET	FF	1	R8C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R8C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
9.285	-0.313	tSu		1	R8C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.717, 64.279%; tC2Q: 0.398, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path19

Path Summary:

Slack	2.554
Data Arrival Time	6.731
Data Required Time	9.285
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.731	0.717	tNET	FF	1	R8C7[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R8C7[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
9.285	-0.313	tSu		1	R8C7[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.717, 64.279%; tC2Q: 0.398, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path20

Path Summary:

Slack	2.554
Data Arrival Time	6.731
Data Required Time	9.285
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.731	0.717	tNET	FF	1	R8C7[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R8C7[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
9.285	-0.313	tSu		1	R8C7[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.717, 64.279%; tC2Q: 0.398, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path21

Path Summary:

Slack	2.554
Data Arrival Time	6.731
Data Required Time	9.285
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.731	0.717	tNET	FF	1	R8C7[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.598	1.598	tNET	RR	1	R8C7[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
9.285	-0.313	tSu		1	R8C7[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.717, 64.279%; tC2Q: 0.398, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.598, 100.000%

Path22

Path Summary:

Slack	2.584
Data Arrival Time	6.709
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.709	0.694	tNET	FF	1	R8C6[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C6[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
9.293	-0.313	tSu		1	R8C6[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.694, 63.543%; tC2Q: 0.398, 36.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path23

Path Summary:

Slack	2.584
Data Arrival Time	6.709
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.709	0.694	tNET	FF	1	R8C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
9.293	-0.313	tSu		1	R8C6[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.694, 63.543%; tC2Q: 0.398, 36.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path24

Path Summary:

Slack	2.584
Data Arrival Time	6.709
Data Required Time	9.293
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.709	0.694	tNET	FF	1	R8C6[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.606	1.606	tNET	RR	1	R8C6[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
9.293	-0.313	tSu		1	R8C6[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.010
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.694, 63.543%; tC2Q: 0.398, 36.457%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.606, 100.000%

Path25

Path Summary:

Slack	2.633
Data Arrival Time	6.646
Data Required Time	9.279
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	pclk:[F]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
4.000	4.000					active clock edge time
4.000	0.000					pclk
4.000	0.000	tCL	FF	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.617	1.617	tNET	FF	1	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.015	0.398	tC2Q	FF	62	R11C3[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
6.646	0.631	tNET	FF	1	R9C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					pclk
8.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
9.591	1.591	tNET	RR	1	R9C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
9.279	-0.313	tSu		1	R9C7[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.025
Setup Relationship	4.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.617, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.631, 61.311%; tC2Q: 0.398, 38.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.591, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.280
Data Arrival Time	1.584
Data Required Time	1.304
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_0_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.584	0.103	tNET	RR	1	R36C4[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C4[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_0_s1/CLK
1.304	-0.048	tHld		1	R36C4[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%

Path2

Path Summary:

Slack	0.284
Data Arrival Time	1.584
Data Required Time	1.300
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_1_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.584	0.103	tNET	RR	1	R36C3[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.348	1.348	tNET	RR	1	R36C3[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_1_s1/CLK
1.300	-0.048	tHld		1	R36C3[3][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/state_1_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.348, 100.000%

Path3

Path Summary:

Slack	0.284
Data Arrival Time	1.584
Data Required Time	1.300
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_1_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.584	0.103	tNET	RR	1	R36C3[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.348	1.348	tNET	RR	1	R36C3[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_1_s1/CLK
1.300	-0.048	tHld		1	R36C3[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_1_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.348, 100.000%

Path4

Path Summary:

Slack	0.284
Data Arrival Time	1.584
Data Required Time	1.300
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_2_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.584	0.103	tNET	RR	1	R36C3[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.348	1.348	tNET	RR	1	R36C3[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_2_s1/CLK
1.300	-0.048	tHld		1	R36C3[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_value_2_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 44.186%; tC2Q: 0.130, 55.814%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.348, 100.000%

Path5

Path Summary:

Slack	0.359
Data Arrival Time	1.663
Data Required Time	1.304
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_0_s0
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.663	0.182	tNET	RR	1	R36C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_0_s0/CLK
1.304	-0.048	tHld		1	R36C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 58.382%; tC2Q: 0.130, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%

Path6

Path Summary:

Slack	0.359
Data Arrival Time	1.663
Data Required Time	1.304
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.663	0.182	tNET	RR	1	R36C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0/CLK
1.304	-0.048	tHld		1	R36C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/csr_addr_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.182, 58.382%; tC2Q: 0.130, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%

Path7

Path Summary:

Slack	0.362
Data Arrival Time	0.990
Data Required Time	0.628
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_1_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.990	0.196	tNET	RR	1	R21C41[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.676	0.676	tNET	RR	1	R21C41[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_1_s1/CLK
0.628	-0.048	tHld		1	R21C41[1][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_1_s1

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 60.221%; tC2Q: 0.130, 39.779%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path8

Path Summary:

Slack	0.362
Data Arrival Time	0.990
Data Required Time	0.628
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_2_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.990	0.196	tNET	RR	1	R21C41[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.676	0.676	tNET	RR	1	R21C41[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_2_s1/CLK
0.628	-0.048	tHld		1	R21C41[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_2_s1

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 60.221%; tC2Q: 0.130, 39.779%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path9

Path Summary:

Slack	0.362
Data Arrival Time	0.990
Data Required Time	0.628
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_4_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.990	0.196	tNET	RR	1	R21C41[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.676	0.676	tNET	RR	1	R21C41[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_4_s1/CLK
0.628	-0.048	tHld		1	R21C41[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_4_s1

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 60.221%; tC2Q: 0.130, 39.779%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path10

Path Summary:

Slack	0.362
Data Arrival Time	0.990
Data Required Time	0.628
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/ep_rst_n_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.990	0.196	tNET	RR	1	R21C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/ep_rst_n_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.676	0.676	tNET	RR	1	R21C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/ep_rst_n_s0/CLK
0.628	-0.048	tHld		1	R21C41[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/ep_rst_n_s0

Path Statistics:

Clock Skew	0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 60.221%; tC2Q: 0.130, 39.779%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.676, 100.000%

Path11

Path Summary:

Slack	0.362
Data Arrival Time	0.967
Data Required Time	0.605
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.781	0.130	tC2Q	RR	20	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
0.967	0.185	tNET	RR	1	R17C32[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R17C32[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0/CLK
0.605	-0.048	tHld		1	R17C32[2][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_6_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%

Path12

Path Summary:

Slack	0.362
Data Arrival Time	0.967
Data Required Time	0.605
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.781	0.130	tC2Q	RR	20	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
0.967	0.185	tNET	RR	1	R17C32[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R17C32[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0/CLK
0.605	-0.048	tHld		1	R17C32[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_9_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%

Path13

Path Summary:

Slack	0.362
Data Arrival Time	0.967
Data Required Time	0.605
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.652	0.652	tNET	RR	1	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/CLK
0.781	0.130	tC2Q	RR	20	R16C30[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/hp_det_s1/Q
0.967	0.185	tNET	RR	1	R17C32[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.653	0.653	tNET	RR	1	R17C32[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0/CLK
0.605	-0.048	tHld		1	R17C32[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/iu3chprx/q_11_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.652, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.653, 100.000%

Path14

Path Summary:

Slack	0.365
Data Arrival Time	0.988
Data Required Time	0.623
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_0_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.988	0.194	tNET	RR	1	R22C40[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.671	0.671	tNET	RR	1	R22C40[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_0_s1/CLK
0.623	-0.048	tHld		1	R22C40[0][B]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_0_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 60.000%; tC2Q: 0.130, 40.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.671, 100.000%

Path15

Path Summary:

Slack	0.365
Data Arrival Time	0.988
Data Required Time	0.623
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_3_s1
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.988	0.194	tNET	RR	1	R22C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.671	0.671	tNET	RR	1	R22C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_3_s1/CLK
0.623	-0.048	tHld		1	R22C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/out_dpp_seq_next_3_s1

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 60.000%; tC2Q: 0.130, 40.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.671, 100.000%

Path16

Path Summary:

Slack	0.365
Data Arrival Time	0.988
Data Required Time	0.623
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_0_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.988	0.194	tNET	RR	1	R22C40[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.671	0.671	tNET	RR	1	R22C40[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_0_s0/CLK
0.623	-0.048	tHld		1	R22C40[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_0_s0

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 60.000%; tC2Q: 0.130, 40.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.671, 100.000%

Path17

Path Summary:

Slack	0.365
Data Arrival Time	0.988
Data Required Time	0.623
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_3_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.988	0.194	tNET	RR	1	R22C40[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.671	0.671	tNET	RR	1	R22C40[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_3_s0/CLK
0.623	-0.048	tHld		1	R22C40[3][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_3_s0

Path Statistics:

Clock Skew	0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 60.000%; tC2Q: 0.130, 40.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.671, 100.000%

Path18

Path Summary:

Slack	0.365
Data Arrival Time	0.990
Data Required Time	0.625
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_1_s0
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.990	0.196	tNET	RR	1	R21C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.672	0.672	tNET	RR	1	R21C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_1_s0/CLK
0.625	-0.048	tHld		1	R21C40[0][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/rty_seq_latch_1_s0

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 60.221%; tC2Q: 0.130, 39.779%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.672, 100.000%

Path19

Path Summary:

Slack	0.366
Data Arrival Time	0.986
Data Required Time	0.620
From	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0
To	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/burst_in_act_s2
Launch Clk	pclk:[R]
Latch Clk	pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.664	0.664	tNET	RR	1	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/CLK
0.794	0.130	tC2Q	RR	39	R24C39[1][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/port_rst_n_s0/Q
0.986	0.193	tNET	RR	1	R24C42[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/burst_in_act_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pclk
0.000	0.000	tCL	RR	5247	R0C1	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
0.668	0.668	tNET	RR	1	R24C42[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/burst_in_act_s2/CLK
0.620	-0.048	tHld		1	R24C42[2][A]	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/burst_in_act_s2

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.664, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.193, 59.777%; tC2Q: 0.130, 40.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.668, 100.000%

Path20

Path Summary:

Slack	0.367
Data Arrival Time	1.668
Data Required Time	1.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_10_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R34C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.349	1.349	tNET	RR	1	R34C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_10_s1/CLK
1.302	-0.048	tHld		1	R34C2[1][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_10_s1

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.349, 100.000%

Path21

Path Summary:

Slack	0.367
Data Arrival Time	1.668
Data Required Time	1.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_11_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R34C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.349	1.349	tNET	RR	1	R34C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_11_s1/CLK
1.302	-0.048	tHld		1	R34C2[1][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_11_s1

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.349, 100.000%

Path22

Path Summary:

Slack	0.367
Data Arrival Time	1.668
Data Required Time	1.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d2_s0
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R34C2[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d2_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.349	1.349	tNET	RR	1	R34C2[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d2_s0/CLK
1.302	-0.048	tHld		1	R34C2[2][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d2_s0

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.349, 100.000%

Path23

Path Summary:

Slack	0.367
Data Arrival Time	1.668
Data Required Time	1.302
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d1_s0
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R34C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.349	1.349	tNET	RR	1	R34C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d1_s0/CLK
1.302	-0.048	tHld		1	R34C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/ffe_en_d1_s0

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.349, 100.000%

Path24

Path Summary:

Slack	0.368
Data Arrival Time	1.668
Data Required Time	1.300
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_1_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R33C2[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.348	1.348	tNET	RR	1	R33C2[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_1_s1/CLK
1.300	-0.048	tHld		1	R33C2[0][A]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_1_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.348, 100.000%

Path25

Path Summary:

Slack	0.368
Data Arrival Time	1.668
Data Required Time	1.300
From	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0
To	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_2_s1
Launch Clk	drp_clk_o:[R]
Latch Clk	drp_clk_o:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.352	1.352	tNET	RR	1	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/CLK
1.481	0.130	tC2Q	RR	54	R36C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/upar_rstn_r1_s0/Q
1.668	0.187	tNET	RR	1	R33C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					drp_clk_o
0.000	0.000	tCL	RR	249	R0C1	SerDes_Top_inst/gtr12_quad_inst0/FABRIC_CM_LIFE_CLK_O
1.348	1.348	tNET	RR	1	R33C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_2_s1/CLK
1.300	-0.048	tHld		1	R33C2[0][B]	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_upar_csr/cnt0_2_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.352, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.187, 59.091%; tC2Q: 0.130, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.348, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_0_res_mem_0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_0_res_mem_0_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_0_res_mem_0_0_0_s/CLKB

MPW2

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/res_mem_2_res_mem_2_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/mem0_mem0_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/mem0_mem0_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/iu3ep0/ep0_transfer_in_mem_ping_pong/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/mem0_mem0_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKB

MPW6

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	fabric_rx_clk
Objects:	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			fabric_rx_clk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
5.640	1.640	tNET	FF	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			fabric_rx_clk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_RX_O_FABRIC_CLK
8.656	0.656	tNET	RR	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/Inst_rx_async_fifo/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA

MPW7

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_1_res_mem_1_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_1_res_mem_1_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_1_res_mem_1_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_3_res_mem_3_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_3_res_mem_3_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/gowin_add_SDPX9B_res_mem_3_res_mem_3_0_0_s/CLKB

MPW9

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_in_ep_ping_pong[1].transfer_in_mem_ping_pong_inst/GEN_TRANSFER_IN_MEM[0].transfer_in_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s/CLKB

MPW10

MPW Summary:

Slack:	2.116
Actual Width:	3.016
Required Width:	0.900
Type:	Low Pulse Width
Clock:	pclk
Objects:	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_out_ep_ping_pong[1].transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			pclk
4.000	0.000	tCL	FF	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
5.640	1.640	tNET	FF	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_out_ep_ping_pong[1].transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			pclk
8.000	0.000	tCL	RR	SerDes_Top_inst/gtr12_quad_inst0/LANE2_PCS_TX_O_FABRIC_CLK
8.656	0.656	tNET	RR	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/gen_out_ep_ping_pong[1].transfer_out_mem_ping_pong/GEN_TRANSFER_OUT_MEM[0].transfer_out_mem_inst/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
5247	pclk	0.098	1.675
1056	attached_Z	2.511	2.314
987	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3r/n6_7	4.087	2.512
519	SerDes_Top_inst/q0_lane2_fabric_rx_clk	1.272	1.664
517	SerDes_Top_inst/USB3_0_PHY_Top_inst/Inst_usb3_0_phy/internel_resetn	4.228	2.600
249	SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[2]	3.922	3.096
220	gw_gao_inst_0/control0[0]	41.958	2.685
136	USB30_Device_Controller_Top_inst/usb30_device_controller_inst/iu3l/rx_cred_idx_latch[1]	4.980	1.209
136	ltssm_state[0]	2.461	2.161
133	ltssm_state[1]	2.768	2.020

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R14C24	91.67%
R17C43	91.67%
R16C24	90.28%
R15C34	88.89%
R17C23	88.89%
R17C41	88.89%
R16C23	88.89%
R14C22	88.89%
R14C25	88.89%
R18C24	87.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name pclk -period 8 -waveform {0 4} [get_nets {pclk}]
TC_CLOCK	Actived	create_clock -name drp_clk_o -period 10 -waveform {0 5} [get_nets {SerDes_Top_inst/upar_arbiter_wrap_SerDes_Top_inst_drp_clk_o[2]}]
TC_CLOCK	Actived	create_clock -name fabric_rx_clk -period 8 -waveform {0 4} [get_nets {SerDes_Top_inst/q0_lane2_fabric_rx_clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {drp_clk_o}] -group [get_clocks {tck_pad_i}]