________________________________________________________________________
	USB 3.0 PHY Reference Design Read Me File
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Object device:
	DK_USB_GW5ART-LV15MG132P_V1.1
	GW5ART-LV15MG132PC1/I0
	GW5ART-15
	A
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File List:
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.		
├─doc
│      Readme.txt						-->  Read Me file (this file)			
│
├─prj
│   │  prj.gprj							-->  File for GOWIN FPGA Designer Project
│   │  prj.gprj.user					-->  File for GOWIN FPGA Designer Project
│   │  serdes_tmp.toml					-->  File for GOWIN FPGA Designer Project
│   │  serdesCsr_change.txt				-->  File for GOWIN FPGA Designer Project
│   │
│   ├─impl
│   │  └─temp
│   │    prj_process_config.json	
│   │
│   └─src
│       │  top.cst						-->  File for GOWIN FPGA Designer Project
│       │  top.sdc                      -->  File for GOWIN FPGA Designer Project
│       │  pll_init.v                   -->  File for GOWIN FPGA Designer Project
│       │  top.sv                       -->  File for GOWIN FPGA Designer Project
│       │
│       ├─desc_gen_cdc
│       │      usb_descrip_gen.c        -->  File for descriptor generation
│       │      usb_descrip_gen.exe      -->  File for descriptor generation
│       │
│       ├─gowin_pll
│       │      gowin_pll.ipc			-->  File for gowin_pll generation
│       │      gowin_pll.mod			-->  File for gowin_pll generation
│       │      gowin_pll.v				-->  File for gowin_pll generation
│       │      gowin_pll_mod.v			-->  File for gowin_pll generation
│       │      gowin_pll_mod_tmp.v		-->  File for gowin_pll generation
│       │      gowin_pll_tmp.v			-->  File for gowin_pll generation
│       │
│       ├─serdes
│       │  │  serdes.csr				-->  File for GOWIN FPGA Designer Project
│       │  │  serdes.ipc                -->  File for GOWIN FPGA Designer Project
│       │  │  serdes.mod                -->  File for GOWIN FPGA Designer Project
│       │  │  serdes.v                  -->  File for GOWIN FPGA Designer Project
│       │  │  serdes_tmp.v              -->  File for GOWIN FPGA Designer Project
│       │  │
│       │  ├─upar_arbiter
│		│  │    └─temp
│       │  │      upar_arbiter.v		-->  File for GOWIN FPGA Designer Project
│       │  │      upar_arbiter.vo       -->  File for GOWIN FPGA Designer Project
│       │  │      upar_arbiter_tmp.v    -->  File for GOWIN FPGA Designer Project
│       │  │
│       │  └─usb3_0_phy
│		│        └─temp
│       │          usb3_0_phy.v			-->  File for GOWIN FPGA Designer Project
│       │          usb3_0_phy.vo        -->  File for GOWIN FPGA Designer Project
│       │          usb3_0_phy_tmp.v     -->  File for GOWIN FPGA Designer Project
│       │
│       │
│       ├─usb30_device_controller
│       │      transfer_in_mem.v			-->  File for GOWIN FPGA Designer Project
│       │      transfer_in_mem_ping_pong.v	-->  File for GOWIN FPGA Designer Project
│       │      transfer_out_mem.v			-->  File for GOWIN FPGA Designer Project
│       │      transfer_out_mem_ping_pong.v	-->  File for GOWIN FPGA Designer Project
│       │      usb3_const.vh			-->  File for GOWIN FPGA Designer Project
│       │      usb3_crc.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_descramble.v		-->  File for GOWIN FPGA Designer Project
│       │      usb3_ep.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_ep0.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_ep0in_ram.v			-->  File for GOWIN FPGA Designer Project
│       │      usb3_lfsr.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_link.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_ltssm_device.v		-->  File for GOWIN FPGA Designer Project
│       │      usb3_macro_define.v		-->  File for GOWIN FPGA Designer Project
│       │      usb3_pipe.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_protocol.v			-->  File for GOWIN FPGA Designer Project
│       │      usb3_scramble.v			-->  File for GOWIN FPGA Designer Project
│       │      usb3_TxHp.v				-->  File for GOWIN FPGA Designer Project
│       │      usb3_TxLcmd.v			-->  File for GOWIN FPGA Designer Project
│       │      USB30_Device_Controller_Top.sv	-->  File for GOWIN FPGA Designer Project
│       │      usb30_device_controller.sv		-->  File for GOWIN FPGA Designer Project
│       │
│       └─usb30_user_layer
│		      └─descriptors
│               ControlTransfer.v		-->  File for GOWIN FPGA Designer Project
│               EP1_loopback.v			-->  File for GOWIN FPGA Designer Project
│               EP2_INT.v				-->  File for GOWIN FPGA Designer Project
│               UserEndpt_define.v		-->  File for GOWIN FPGA Designer Project
│               UserLayer_top.sv		-->  File for GOWIN FPGA Designer Project
├─simulation
│  ├─modelsim
│  │  cmd.do						-->  File for simulation
│  │  run.bat						-->  File for simulation
│  │  wave.do						-->  File for simulation
│  │
│  │
├─tb
│  │  async_fifo.v					 -->  File for simulation
│  │  prim_sim.v                     -->  File for simulation
│  │  usb3_const.vh                  -->  File for simulation
│  │  usb3_crc.v                     -->  File for simulation
│  │  usb3_crc_dpp32_host.v          -->  File for simulation
│  │  usb3_descramble.v              -->  File for simulation
│  │  usb3_host_link.v               -->  File for simulation
│  │  usb3_host_protocol.v           -->  File for simulation
│  │  usb3_lfsr.v                    -->  File for simulation
│  │  usb3_ltssm_host.v              -->  File for simulation
│  │  usb3_pipe.v                    -->  File for simulation
│  │  usb3_scramble.v                -->  File for simulation
│  │  usb3_top_device.v              -->  File for simulation
│  │  usb3_top_host.v                -->  File for simulation
│  │  usb3_top_tusb1310a_host.v      -->  File for simulation
│  │  usb_3_0_sim_top.v              -->  File for simulation
│  │
│  └─serdes
│      │  serdes.csr				 -->  File for simulation
│      │  serdes.ipc                 -->  File for simulation
│      │  serdes.mod                 -->  File for simulation
│      │  serdes.v                   -->  File for simulation
│      │  serdes_tmp.v               -->  File for simulation
│      │
│      ├─upar_arbiter				 -->  File for simulation
│      │     upar_arbiter.v          -->  File for simulation
│      │     upar_arbiter.vo         -->  File for simulation
│      │     upar_arbiter_tmp.v      -->  File for simulation
│      │
│      └─usb3_0_phy
│            usb30phy_vg.vg								 -->  File for simulation


				
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HOW TO OPEN A PROJECT IN GOWIN FPGA Designer:
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1. Unzip the respective design files.
2. Launch GOWIN FPGA Designer and select "File -> Open -> Project"
3. In the Open Project dialog, enter the Project location -- "project",select the project"prj.gprj".
4. Click Finish. Now the project is successfully loaded. 

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HOW TO RUN SYNTHESIZE, PLACE AND ROUTE, IP CORE GENERATION, AND TIMING ANALYSIS IN GOWIN FPGA Designer:
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1. Click the Process tab in the process panel of the GOWIN FPGA Designer dashboard. 
   Double click on Synthsize. This will bring the design through synthesis.
2. Click the Process tab in the process panel of the GOWIN FPGA Designer dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
3. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.
4. Click on "Project -> Configuration -> Place & Route" to configurate the Post-Place File 
   and SDF File of the design.
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HOW TO RUN SIMULATION
1. User can run functional simulation by software Modelsim. 
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HOW TO  GENERATE IP CORE
1. Click the IP Core Generator tab in the Window panel of the GOWIN FPGA Designer dashboard.
   Double click on "SerDes" and choose USB 3.0 PHY. This will generate the IP Core for the design.
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