Synthesis Messages

Report Title	GowinSynthesis Report
Design File	D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\SERDES_IP\data\Upar_Arbiter\upar_arbiter_wrap.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.9.03 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Thu Apr 25 14:28:35 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	\~upar_arbiter_wrap.SerDes_Top
Synthesis Process	Running parser:     CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.463s, Peak memory usage = 79.512MB Running netlist conversion:     CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 79.512MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 79.512MB     Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 79.512MB     Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 79.512MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 79.512MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 79.512MB     Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 79.512MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 79.512MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 79.512MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 79.512MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 79.512MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 79.512MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 79.512MB Generate output files:     CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 85.820MB
Total Time and Memory Usage	CPU time = 0h 0m 0.852s, Elapsed time = 0h 0m 0.913s, Peak memory usage = 85.820MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	919
I/O Buf	919
IBUF	563
OBUF	356
Register	993
DFFCE	993
LUT	650
LUT2	162
LUT3	289
LUT4	199
INV	1
INV	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	651(651 LUT, 0 ALU) / 138240	<1%
Register	993 / 139140	<1%
--Register as Latch	0 / 139140	0%
--Register as FF	993 / 139140	<1%
BSRAM	0 / 340	0%

Timing

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
upar_clk_i	Base	10.000	100.0	0.000	5.000			upar_clk_i_ibuf/I

Max Frequency Summary:

No.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	upar_clk_i	100.000(MHz)	210.416(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	5.248
Data Arrival Time	5.101
Data Required Time	10.349
From	u_upar_arbiter/cur_state_0_s0
To	u_upar_arbiter/upar_addr_o_0_s1
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
0.413	0.413	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
0.795	0.382	tC2Q	RR	10	u_upar_arbiter/cur_state_0_s0/Q
1.207	0.413	tNET	RR	1	u_upar_arbiter/n1084_s1/I0
1.786	0.579	tINS	RR	43	u_upar_arbiter/n1084_s1/F
2.199	0.413	tNET	RR	1	u_upar_arbiter/n1084_s0/I2
2.706	0.507	tINS	RR	2	u_upar_arbiter/n1084_s0/F
3.119	0.413	tNET	RR	1	u_upar_arbiter/next_state_0_s15/I0
3.698	0.579	tINS	RR	25	u_upar_arbiter/next_state_0_s15/F
4.110	0.413	tNET	RR	1	u_upar_arbiter/n1052_s1/I0
4.689	0.579	tINS	RR	1	u_upar_arbiter/n1052_s1/F
5.101	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
10.413	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_0_s1/CLK
10.349	-0.064	tSu		1	u_upar_arbiter/upar_addr_o_0_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay:	cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:

Slack	5.248
Data Arrival Time	5.101
Data Required Time	10.349
From	u_upar_arbiter/cur_state_0_s0
To	u_upar_arbiter/upar_addr_o_1_s1
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
0.413	0.413	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
0.795	0.382	tC2Q	RR	10	u_upar_arbiter/cur_state_0_s0/Q
1.207	0.413	tNET	RR	1	u_upar_arbiter/n1084_s1/I0
1.786	0.579	tINS	RR	43	u_upar_arbiter/n1084_s1/F
2.199	0.413	tNET	RR	1	u_upar_arbiter/n1084_s0/I2
2.706	0.507	tINS	RR	2	u_upar_arbiter/n1084_s0/F
3.119	0.413	tNET	RR	1	u_upar_arbiter/next_state_0_s15/I0
3.698	0.579	tINS	RR	25	u_upar_arbiter/next_state_0_s15/F
4.110	0.413	tNET	RR	1	u_upar_arbiter/n1051_s1/I0
4.689	0.579	tINS	RR	1	u_upar_arbiter/n1051_s1/F
5.101	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
10.413	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_1_s1/CLK
10.349	-0.064	tSu		1	u_upar_arbiter/upar_addr_o_1_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay:	cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:

Slack	5.248
Data Arrival Time	5.101
Data Required Time	10.349
From	u_upar_arbiter/cur_state_0_s0
To	u_upar_arbiter/upar_addr_o_2_s1
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
0.413	0.413	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
0.795	0.382	tC2Q	RR	10	u_upar_arbiter/cur_state_0_s0/Q
1.207	0.413	tNET	RR	1	u_upar_arbiter/n1084_s1/I0
1.786	0.579	tINS	RR	43	u_upar_arbiter/n1084_s1/F
2.199	0.413	tNET	RR	1	u_upar_arbiter/n1084_s0/I2
2.706	0.507	tINS	RR	2	u_upar_arbiter/n1084_s0/F
3.119	0.413	tNET	RR	1	u_upar_arbiter/next_state_0_s15/I0
3.698	0.579	tINS	RR	25	u_upar_arbiter/next_state_0_s15/F
4.110	0.413	tNET	RR	1	u_upar_arbiter/n1050_s1/I0
4.689	0.579	tINS	RR	1	u_upar_arbiter/n1050_s1/F
5.101	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
10.413	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_2_s1/CLK
10.349	-0.064	tSu		1	u_upar_arbiter/upar_addr_o_2_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay:	cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:

Slack	5.248
Data Arrival Time	5.101
Data Required Time	10.349
From	u_upar_arbiter/cur_state_0_s0
To	u_upar_arbiter/upar_addr_o_3_s1
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
0.413	0.413	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
0.795	0.382	tC2Q	RR	10	u_upar_arbiter/cur_state_0_s0/Q
1.207	0.413	tNET	RR	1	u_upar_arbiter/n1084_s1/I0
1.786	0.579	tINS	RR	43	u_upar_arbiter/n1084_s1/F
2.199	0.413	tNET	RR	1	u_upar_arbiter/n1084_s0/I2
2.706	0.507	tINS	RR	2	u_upar_arbiter/n1084_s0/F
3.119	0.413	tNET	RR	1	u_upar_arbiter/next_state_0_s15/I0
3.698	0.579	tINS	RR	25	u_upar_arbiter/next_state_0_s15/F
4.110	0.413	tNET	RR	1	u_upar_arbiter/n1049_s1/I0
4.689	0.579	tINS	RR	1	u_upar_arbiter/n1049_s1/F
5.101	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
10.413	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_3_s1/CLK
10.349	-0.064	tSu		1	u_upar_arbiter/upar_addr_o_3_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay:	cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:

Slack	5.248
Data Arrival Time	5.101
Data Required Time	10.349
From	u_upar_arbiter/cur_state_0_s0
To	u_upar_arbiter/upar_addr_o_4_s1
Launch Clk	upar_clk_i[R]
Latch Clk	upar_clk_i[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				upar_clk_i
0.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
0.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
0.413	0.413	tNET	RR	1	u_upar_arbiter/cur_state_0_s0/CLK
0.795	0.382	tC2Q	RR	10	u_upar_arbiter/cur_state_0_s0/Q
1.207	0.413	tNET	RR	1	u_upar_arbiter/n1084_s1/I0
1.786	0.579	tINS	RR	43	u_upar_arbiter/n1084_s1/F
2.199	0.413	tNET	RR	1	u_upar_arbiter/n1084_s0/I2
2.706	0.507	tINS	RR	2	u_upar_arbiter/n1084_s0/F
3.119	0.413	tNET	RR	1	u_upar_arbiter/next_state_0_s15/I0
3.698	0.579	tINS	RR	25	u_upar_arbiter/next_state_0_s15/F
4.110	0.413	tNET	RR	1	u_upar_arbiter/n1048_s1/I0
4.689	0.579	tINS	RR	1	u_upar_arbiter/n1048_s1/F
5.101	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				upar_clk_i
10.000	0.000	tCL	RR	1	upar_clk_i_ibuf/I
10.000	0.000	tINS	RR	993	upar_clk_i_ibuf/O
10.413	0.413	tNET	RR	1	u_upar_arbiter/upar_addr_o_4_s1/CLK
10.349	-0.064	tSu		1	u_upar_arbiter/upar_addr_o_4_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay:	cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.413, 100.000%