<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>beta</Version>
    <Device id="GW5AST-138B" package="FCPBGA676A" speed="1" partNumber="GW5AST-LV138FPG676AES"/>
    <FileList>
        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/USB30DEVICECONTROLLER/data/USB30_Device_Controller_Top.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/USB30DEVICECONTROLLER/data/usb30_device_controller.v" type="verilog"/>
    </FileList>
    <OptionList>
        <Option type="disable_insert_pad" value="1"/>
        <Option type="enable_dsrm" value="0"/>
        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/USB30DEVICECONTROLLER/data"/>
        <Option type="include_path" value="E:/myWork/IP/releaseVerify/version/1.9.9.03/Gowin_USB3.0_Device_Controller_RefDesign/prj/src/usb30_device_controller/temp/"/>
        <Option type="output_file" value="USB30_Device_Controller.vg"/>
        <Option type="output_template" value="USB30_Device_Controller_tmp.v"/>
        <Option type="ram_balance" value="1"/>
        <Option type="ram_rw_check" value="1"/>
        <Option type="verilog_language" value="sysv-2017"/>
    </OptionList>
</Project>
