Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Tue Jan 16 10:14:05 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.185s, Peak memory usage = 49.207MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 49.207MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 49.207MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 49.207MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 49.207MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 49.207MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 49.207MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 49.207MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 49.207MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.086s, Peak memory usage = 49.207MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 49.207MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 49.207MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 76.672MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 76.672MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 76.672MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 76.672MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 186 |
| I/O Buf | 186 |
| IBUF | 69 |
| OBUF | 117 |
| Register | 1440 |
| DFF | 194 |
| DFFE | 830 |
| DFFR | 11 |
| DFFP | 5 |
| DFFPE | 4 |
| DFFC | 180 |
| DFFCE | 216 |
| LUT | 970 |
| LUT2 | 69 |
| LUT3 | 601 |
| LUT4 | 300 |
| ALU | 40 |
| ALU | 40 |
| INV | 11 |
| INV | 11 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1021(981 LUT, 40 ALU) / 20736 | 5% |
| Register | 1440 / 16173 | 9% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1440 / 16173 | 9% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.0(MHz) | 145.7(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.138 |
| Data Arrival Time | 7.869 |
| Data Required Time | 11.007 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0 |
| 2.880 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 3.354 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 3.457 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.931 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/I2 |
| 4.384 | 0.453 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/F |
| 4.858 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s49/I0 |
| 5.375 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s49/F |
| 5.849 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s51/I1 |
| 6.404 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s51/F |
| 6.878 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I0 |
| 7.395 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F |
| 7.869 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.803, 41.058%; route: 3.792, 55.544%; tC2Q: 0.232, 3.398% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 3.138 |
| Data Arrival Time | 7.869 |
| Data Required Time | 11.007 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0 |
| 2.880 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 3.354 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 3.457 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.931 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/I2 |
| 4.384 | 0.453 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/F |
| 4.858 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I1 |
| 5.413 | 0.555 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F |
| 5.887 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s48/I0 |
| 6.404 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s48/F |
| 6.878 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s49/I0 |
| 7.395 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s49/F |
| 7.869 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.803, 41.058%; route: 3.792, 55.544%; tC2Q: 0.232, 3.398% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:| Slack | 3.138 |
| Data Arrival Time | 7.869 |
| Data Required Time | 11.007 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0 |
| 2.880 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 3.354 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 3.457 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.931 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/I2 |
| 4.384 | 0.453 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/F |
| 4.858 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I1 |
| 5.413 | 0.555 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F |
| 5.887 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s67/I0 |
| 6.404 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s67/F |
| 6.878 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s52/I0 |
| 7.395 | 0.517 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s52/F |
| 7.869 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.803, 41.058%; route: 3.792, 55.544%; tC2Q: 0.232, 3.398% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:| Slack | 3.164 |
| Data Arrival Time | 7.843 |
| Data Required Time | 11.007 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0 |
| 2.880 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 3.354 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 3.457 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.931 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/I2 |
| 4.384 | 0.453 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/F |
| 4.858 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/I1 |
| 5.413 | 0.555 | tINS | FF | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s57/F |
| 5.887 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s57/I1 |
| 6.442 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s57/F |
| 6.916 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s56/I2 |
| 7.369 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s56/F |
| 7.843 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.777, 40.832%; route: 3.792, 55.757%; tC2Q: 0.232, 3.411% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:| Slack | 3.164 |
| Data Arrival Time | 7.843 |
| Data Required Time | 11.007 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_22_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I0 |
| 2.880 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 3.354 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 3.457 | 0.103 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.931 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/I2 |
| 4.384 | 0.453 | tINS | FF | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s62/F |
| 4.858 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s61/I1 |
| 5.413 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s61/F |
| 5.887 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s58/I1 |
| 6.442 | 0.555 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s58/F |
| 6.916 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s56/I2 |
| 7.369 | 0.453 | tINS | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s56/F |
| 7.843 | 0.474 | tNET | FF | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1440 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.777, 40.832%; route: 3.792, 55.757%; tC2Q: 0.232, 3.411% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |