Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\I2CMASTER\data\I2C_MASTER_TOP.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\I2CMASTER\data\I2C_MASTER.vp |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Tue Jan 16 10:15:35 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | I2C_MASTER_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 36.711MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 36.711MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 36.711MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 36.711MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.711MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 36.711MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 36.711MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 36.711MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 36.711MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 36.711MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 36.711MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 36.711MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.581s, Peak memory usage = 65.496MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 65.496MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 65.496MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.7s, Elapsed time = 0h 0m 0.713s, Peak memory usage = 65.496MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 29 |
| I/O Buf | 29 |
| IBUF | 18 |
| OBUF | 9 |
| IOBUF | 2 |
| Register | 124 |
| DFF | 1 |
| DFFP | 5 |
| DFFPE | 2 |
| DFFC | 23 |
| DFFCE | 93 |
| LUT | 216 |
| LUT2 | 27 |
| LUT3 | 75 |
| LUT4 | 114 |
| INV | 1 |
| INV | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 217(217 LUT, 0 ALU) / 20736 | 2% |
| Register | 124 / 16173 | <1% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 124 / 16173 | <1% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_CLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_CLK | 100.0(MHz) | 205.9(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.143 |
| Data Arrival Time | 5.864 |
| Data Required Time | 11.007 |
| From | u_i2c_master/bit_controller/cnt_10_s1 |
| To | u_i2c_master/bit_controller/cnt_14_s1 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_10_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 4 | u_i2c_master/bit_controller/cnt_10_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s3/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n13_s3/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n13_s1/I1 |
| 3.332 | 0.555 | tINS | FF | 4 | u_i2c_master/bit_controller/n13_s1/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s1/I1 |
| 4.361 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s1/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n32_s0/I1 |
| 5.390 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n32_s0/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/cnt_14_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/cnt_14_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/cnt_14_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.220, 46.039%; route: 2.370, 49.150%; tC2Q: 0.232, 4.811% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 5.181 |
| Data Arrival Time | 5.826 |
| Data Required Time | 11.007 |
| From | u_i2c_master/byte_controller/c_state_2_s0 |
| To | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
| 2.303 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
| 3.294 | 0.517 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
| 3.768 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
| 4.323 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
| 4.797 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s2/I1 |
| 5.352 | 0.555 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s2/F |
| 5.826 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0/CLK |
| 11.007 | -0.035 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.182, 45.610%; route: 2.370, 49.541%; tC2Q: 0.232, 4.849% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:| Slack | 5.181 |
| Data Arrival Time | 5.826 |
| Data Required Time | 11.007 |
| From | u_i2c_master/byte_controller/c_state_2_s0 |
| To | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_i2c_master/byte_controller/c_state_2_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 8 | u_i2c_master/byte_controller/c_state_2_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n208_s4/I1 |
| 2.303 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n208_s4/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s5/I0 |
| 3.294 | 0.517 | tINS | FF | 1 | u_i2c_master/byte_controller/n200_s5/F |
| 3.768 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n200_s3/I1 |
| 4.323 | 0.555 | tINS | FF | 2 | u_i2c_master/byte_controller/n200_s3/F |
| 4.797 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/n199_s2/I1 |
| 5.352 | 0.555 | tINS | FF | 1 | u_i2c_master/byte_controller/n199_s2/F |
| 5.826 | 0.474 | tNET | FF | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0/CLK |
| 11.007 | -0.035 | tSu | 1 | u_i2c_master/byte_controller/CORE_CMD_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.182, 45.610%; route: 2.370, 49.541%; tC2Q: 0.232, 4.849% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:| Slack | 5.219 |
| Data Arrival Time | 5.788 |
| Data Required Time | 11.007 |
| From | u_i2c_master/bit_controller/c_state_3_s1 |
| To | u_i2c_master/bit_controller/SDA_OEN_s1 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_3_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 6 | u_i2c_master/bit_controller/c_state_3_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n227_s6/I1 |
| 2.303 | 0.555 | tINS | FF | 7 | u_i2c_master/bit_controller/n227_s6/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n226_s4/I1 |
| 3.332 | 0.555 | tINS | FF | 4 | u_i2c_master/bit_controller/n226_s4/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s8/I0 |
| 4.324 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s8/F |
| 4.798 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n230_s1/I0 |
| 5.315 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n230_s1/F |
| 5.789 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/SDA_OEN_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/SDA_OEN_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.144, 45.175%; route: 2.370, 49.937%; tC2Q: 0.232, 4.888% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:| Slack | 5.219 |
| Data Arrival Time | 5.788 |
| Data Required Time | 11.007 |
| From | u_i2c_master/bit_controller/c_state_14_s1 |
| To | u_i2c_master/bit_controller/CMD_ACK_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/c_state_14_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 5 | u_i2c_master/bit_controller/c_state_14_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n123_s2/I1 |
| 2.303 | 0.555 | tINS | FF | 11 | u_i2c_master/bit_controller/n123_s2/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s4/I1 |
| 3.332 | 0.555 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s4/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s2/I0 |
| 4.324 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s2/F |
| 4.798 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/n250_s1/I0 |
| 5.315 | 0.517 | tINS | FF | 1 | u_i2c_master/bit_controller/n250_s1/F |
| 5.789 | 0.474 | tNET | FF | 1 | u_i2c_master/bit_controller/CMD_ACK_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 124 | I_CLK_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_i2c_master/bit_controller/CMD_ACK_s0/CLK |
| 11.007 | -0.035 | tSu | 1 | u_i2c_master/bit_controller/CMD_ACK_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.144, 45.175%; route: 2.370, 49.937%; tC2Q: 0.232, 4.888% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |