| Report Title |
Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\impl\gwsynthesis\IIC_MASTER.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\top.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_DCSCM_LTPI_RefDesign20240124\project\IIC_MASTER\src\top.sdc |
| Tool Version |
V1.9.9.01 (64-bit) |
| Part Number |
GW2A-LV18PG256C8/I7 |
| Device |
GW2A-18 |
| Created Time |
Mon Jan 29 10:51:59 2024
|
| Legal Announcement |
Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
108.348 |
| Quiescent Power (mW) |
93.110 |
| Dynamic Power (mW) |
15.238 |
| Junction Temperature |
28.469 |
| Theta JA |
32.020 |
| Max Allowed Ambient Temperature |
81.531 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
14.296 |
61.515 |
75.811 |
| VCCX |
2.500 |
0.165 |
11.364 |
28.822 |
| VCCIO25 |
2.500 |
0.020 |
0.143 |
0.406 |
| VCCIO33 |
3.300 |
0.145 |
0.857 |
3.308 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
3.657 |
NA |
12.500 |
| IO |
5.099
| 3.992
| 3.472
|
| PLL |
10.460
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| top |
14.117 |
14.117(14.076) |
| top/u0_syspll_rPLL/ |
10.460 |
10.460(0.000) |
| top/u1_apb2local/ |
0.012 |
0.012(0.000) |
| top/u_Uart_to_Bus_Top/ |
1.952 |
1.952(1.952) |
| top/u_Uart_to_Bus_Top/uart_bus_core/ |
1.952 |
1.952(1.792) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/ |
1.792 |
1.792(1.792) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/ |
0.069 |
0.069(0.000) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/ |
0.856 |
0.856(0.856) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/ |
0.785 |
0.785(0.615) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/ |
0.615 |
0.615(0.000) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/ |
0.071 |
0.071(0.000) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/ |
0.867 |
0.867(0.867) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/ |
0.777 |
0.777(0.634) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/ |
0.634 |
0.634(0.000) |
| top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/ |
0.090 |
0.090(0.000) |
| top/u_apb2local/ |
0.034 |
0.034(0.000) |
| top/u_i2c_master_cfgport/ |
0.283 |
0.283(0.277) |
| top/u_i2c_master_cfgport/U_I2C_MASTER_Top/ |
0.277 |
0.277(0.277) |
| top/u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/ |
0.277 |
0.277(0.210) |
| top/u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/bit_controller/ |
0.136 |
0.136(0.000) |
| top/u_i2c_master_cfgport/U_I2C_MASTER_Top/u_i2c_master/byte_controller/ |
0.075 |
0.075(0.000) |
| top/u_local2reg/ |
1.335 |
1.335(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| w_clk100m |
100.000 |
3.671 |
| i_clk |
50.000 |
10.460 |