Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\LTPI\data\dcscm_ltpi_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\LTPI\data\ltpi_core_encryption.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jan 24 09:27:11 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DCSCM_LTPI_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.489s, Peak memory usage = 81.594MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 81.594MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.297s, Peak memory usage = 81.594MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 81.594MB Optimizing Phase 2: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.587s, Peak memory usage = 81.594MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 81.594MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 81.594MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 81.594MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 81.594MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.4s, Peak memory usage = 81.594MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 81.594MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 81.594MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 100.512MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.265s, Peak memory usage = 100.512MB Generate output files: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.238s, Peak memory usage = 100.512MB |
| Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 100.512MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 407 |
| I/O Buf | 379 |
| IBUF | 211 |
| OBUF | 166 |
| IOBUF | 2 |
| Register | 2740 |
| DFF | 198 |
| DFFE | 368 |
| DFFS | 54 |
| DFFSE | 164 |
| DFFR | 299 |
| DFFRE | 1497 |
| DFFP | 3 |
| DFFC | 87 |
| DFFCE | 70 |
| LUT | 2722 |
| LUT2 | 321 |
| LUT3 | 804 |
| LUT4 | 1597 |
| ALU | 643 |
| ALU | 643 |
| INV | 41 |
| INV | 41 |
| IOLOGIC | 3 |
| IDES10 | 1 |
| OSER10 | 2 |
| CLOCK | 3 |
| CLKDIV | 2 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3406(2763 LUT, 643 ALU) / 20736 | 17% |
| Register | 2740 / 16173 | 17% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2740 / 16173 | 17% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| ref_clk_i | Base | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ||
| lvds_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | lvds_rx_clk_i_ibuf/I | ||
| clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I | ||
| cfg_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | cfg_clk_i_ibuf/I | ||
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.5 | 0.000 | 40.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.3 | 0.000 | 60.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3 |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk | Generated | 50.000 | 20.0 | 0.000 | 25.000 | lvds_rx_clk_i_ibuf/I | lvds_rx_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Generated | 200.000 | 5.0 | 0.000 | 100.000 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.000(MHz) | 144.613(MHz) | 7 | TOP |
| 2 | cfg_clk_i | 100.000(MHz) | 183.150(MHz) | 6 | TOP |
| 3 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk | 20.000(MHz) | 170.999(MHz) | 6 | TOP |
| 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | 5.000(MHz) | 261.233(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.085 |
| Data Arrival Time | 7.922 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
| 1.275 | 0.232 | tC2Q | RF | 20 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/I1 |
| 2.303 | 0.555 | tINS | FF | 8 | u_ltpi_core/u_ltpi_main/DATA_CHANNEL.u_ltpi_datchl_controller/u_datchl_ctrl_fsm/n747_s7/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/I1 |
| 3.332 | 0.555 | tINS | FF | 17 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1984_s2/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/I1 |
| 4.361 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n261_s56/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/I1 |
| 5.390 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s69/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s67/I1 |
| 6.419 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s67/F |
| 6.893 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s65/I1 |
| 7.448 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n259_s65/F |
| 7.922 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.330, 48.401%; route: 3.318, 48.227%; tC2Q: 0.232, 3.372% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 3.085 |
| Data Arrival Time | 7.922 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 19 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/I1 |
| 3.332 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/I1 |
| 4.361 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I1 |
| 5.390 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/I1 |
| 6.419 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/F |
| 6.893 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/I1 |
| 7.448 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/F |
| 7.922 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.330, 48.401%; route: 3.318, 48.227%; tC2Q: 0.232, 3.372% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:| Slack | 3.161 |
| Data Arrival Time | 7.846 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_1_s0 |
| To | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_1_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 6 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/nl_gpio_max_frm_cnt_o_1_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s25/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s25/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s21/I1 |
| 3.332 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s21/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s14/I0 |
| 4.324 | 0.517 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s14/F |
| 4.798 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/I1 |
| 5.352 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s7/F |
| 5.826 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/I1 |
| 6.381 | 0.555 | tINS | FF | 8 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_7_s3/F |
| 6.855 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n114_s3/I0 |
| 7.372 | 0.517 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/n114_s3/F |
| 7.846 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/GPIO.u_ltpi_gpio/NL_GPIO_index_o_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.254, 47.825%; route: 3.318, 48.765%; tC2Q: 0.232, 3.410% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:| Slack | 3.184 |
| Data Arrival Time | 7.823 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 19 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/I1 |
| 3.332 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/I1 |
| 4.361 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I1 |
| 5.390 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/I1 |
| 6.419 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/F |
| 6.893 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I1 |
| 7.463 | 0.570 | tINS | FR | 5 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.823 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.345, 49.329%; route: 3.204, 47.250%; tC2Q: 0.232, 3.421% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:| Slack | 3.184 |
| Data Arrival Time | 7.823 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 19 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s24/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/I1 |
| 3.332 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s17/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/I1 |
| 4.361 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s13/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I1 |
| 5.390 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/I1 |
| 6.419 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s2/F |
| 6.893 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I1 |
| 7.463 | 0.570 | tINS | FR | 5 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.823 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2051 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.345, 49.329%; route: 3.204, 47.250%; tC2Q: 0.232, 3.421% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |