Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\LTPI\data\dcscm_ltpi_top.v C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\LTPI\data\ltpi_core_encryption.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jan 24 09:28:28 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | LTPI_HPM_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.451s, Peak memory usage = 82.422MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 82.422MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.316s, Peak memory usage = 82.422MB Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 82.422MB Optimizing Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.389s, Peak memory usage = 82.422MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 82.422MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 82.422MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 82.422MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 82.422MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.424s, Peak memory usage = 82.422MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 82.422MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 82.422MB Tech-Mapping Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 100.441MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.306s, Peak memory usage = 100.441MB Generate output files: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.262s, Peak memory usage = 100.484MB |
| Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 100.484MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 407 |
| I/O Buf | 379 |
| IBUF | 174 |
| OBUF | 203 |
| IOBUF | 2 |
| Register | 2857 |
| DFF | 188 |
| DFFE | 373 |
| DFFS | 54 |
| DFFSE | 153 |
| DFFR | 264 |
| DFFRE | 1658 |
| DFFP | 3 |
| DFFC | 85 |
| DFFCE | 79 |
| LUT | 2851 |
| LUT2 | 361 |
| LUT3 | 798 |
| LUT4 | 1692 |
| ALU | 658 |
| ALU | 658 |
| SSRAM | 1 |
| RAM16SDP1 | 1 |
| INV | 40 |
| INV | 40 |
| IOLOGIC | 3 |
| IDES10 | 1 |
| OSER10 | 2 |
| CLOCK | 3 |
| CLKDIV | 2 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3555(2891 LUT, 658 ALU, 1 RAM16) / 20736 | 18% |
| Register | 2857 / 16173 | 18% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2857 / 16173 | 18% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| ref_clk_i | Base | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ||
| lvds_rx_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | lvds_rx_clk_i_ibuf/I | ||
| clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_i_ibuf/I | ||
| cfg_clk_i | Base | 10.000 | 100.0 | 0.000 | 5.000 | cfg_clk_i_ibuf/I | ||
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.5 | 0.000 | 40.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.3 | 0.000 | 60.000 | ref_clk_i_ibuf/I | ref_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3 |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk | Generated | 50.000 | 20.0 | 0.000 | 25.000 | lvds_rx_clk_i_ibuf/I | lvds_rx_clk_i | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT |
| u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Generated | 200.000 | 5.0 | 0.000 | 100.000 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT | u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.000(MHz) | 134.102(MHz) | 8 | TOP |
| 2 | cfg_clk_i | 100.000(MHz) | 159.719(MHz) | 7 | TOP |
| 3 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u2_CLKDIV/CLKOUT.default_gen_clk | 20.000(MHz) | 172.117(MHz) | 6 | TOP |
| 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | 5.000(MHz) | 276.167(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.543 |
| Data Arrival Time | 8.464 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
| 1.275 | 0.232 | tC2Q | RF | 20 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/I1 |
| 2.303 | 0.555 | tINS | FF | 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/I3 |
| 3.148 | 0.371 | tINS | FF | 18 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/F |
| 3.622 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/I1 |
| 4.177 | 0.555 | tINS | FF | 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/F |
| 4.651 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/I1 |
| 5.206 | 0.555 | tINS | FF | 3 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/F |
| 5.680 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/I2 |
| 6.133 | 0.453 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/F |
| 6.607 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/I2 |
| 7.060 | 0.453 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/F |
| 7.534 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s8/I1 |
| 8.104 | 0.570 | tINS | FR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s8/F |
| 8.464 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.512, 47.319%; route: 3.678, 49.555%; tC2Q: 0.232, 3.126% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 2.546 |
| Data Arrival Time | 8.462 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_12_s0 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_12_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 23 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_12_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s26/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s26/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s37/I1 |
| 3.332 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s37/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s8/I2 |
| 4.260 | 0.453 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s8/F |
| 4.734 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/I1 |
| 5.288 | 0.555 | tINS | FF | 3 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/F |
| 5.762 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/I2 |
| 6.215 | 0.453 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/F |
| 6.689 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/I3 |
| 7.060 | 0.371 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/F |
| 7.534 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/I2 |
| 7.987 | 0.453 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/F |
| 8.462 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.395, 45.761%; route: 3.792, 51.112%; tC2Q: 0.232, 3.127% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:| Slack | 2.786 |
| Data Arrival Time | 8.221 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
| 1.275 | 0.232 | tC2Q | RF | 20 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/I1 |
| 2.303 | 0.555 | tINS | FF | 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/I3 |
| 3.148 | 0.371 | tINS | FF | 18 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/F |
| 3.622 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/I1 |
| 4.177 | 0.555 | tINS | FF | 4 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/F |
| 4.651 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/I1 |
| 5.206 | 0.555 | tINS | FF | 3 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/F |
| 5.680 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/I2 |
| 6.133 | 0.453 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/F |
| 6.607 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/I2 |
| 7.060 | 0.453 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/F |
| 7.534 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s14/I3 |
| 7.861 | 0.327 | tINS | FR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s14/F |
| 8.221 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.269, 45.536%; route: 3.678, 51.232%; tC2Q: 0.232, 3.232% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:| Slack | 3.187 |
| Data Arrival Time | 7.820 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_4_s0 |
| To | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_4_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 9 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_4_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s31/I1 |
| 2.303 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s31/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s30/I1 |
| 3.332 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s30/F |
| 3.806 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s17/I1 |
| 4.361 | 0.555 | tINS | FF | 2 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s17/F |
| 4.835 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s7/I1 |
| 5.390 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s7/F |
| 5.864 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s6/I1 |
| 6.419 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s6/F |
| 6.893 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s3/I2 |
| 7.346 | 0.453 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s3/F |
| 7.820 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 3.228, 47.625%; route: 3.318, 48.952%; tC2Q: 0.232, 3.423% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:| Slack | 3.220 |
| Data Arrival Time | 7.787 |
| Data Required Time | 11.007 |
| From | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_0_s0 |
| To | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_0_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 7 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_0_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/I0 |
| 3.294 | 0.517 | tINS | FF | 6 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/F |
| 3.768 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s135/I0 |
| 4.286 | 0.517 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s135/F |
| 4.760 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s130/I1 |
| 5.314 | 0.555 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s130/F |
| 5.788 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s140/I3 |
| 6.159 | 0.371 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s140/F |
| 6.633 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s137/I0 |
| 6.736 | 0.103 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s137/O |
| 7.210 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s119/I1 |
| 7.313 | 0.103 | tINS | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n736_s119/O |
| 7.787 | 0.474 | tNET | FF | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2162 | clk_i_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.721, 40.341%; route: 3.792, 56.219%; tC2Q: 0.232, 3.440% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |