Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\impl\gwsynthesis\HPM_LTPI.vg |
| Physical Constraints File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\src\top.cst |
| Timing Constraint File | E:\15_LTPI\godbless\my_self_v8\Gowin_DCSCM_LTPI_RefDesign1\project\DCSCM_LTPI_HPM\src\top.sdc |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jan 24 09:31:33 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.95V 85C C8/I7 |
| Hold Delay Model | Fast 1.05V 0C C8/I7 |
| Numbers of Paths Analyzed | 29378 |
| Numbers of Endpoints Analyzed | 13959 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|
| i_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | i_clk | ||
| RX_CLK_P | Base | 6.660 | 150.150 | 0.000 | 3.330 | RX_CLK_P | ||
| rxdiv5clk | Generated | 33.300 | 30.030 | 0.000 | 16.650 | RX_CLK_P | RX_CLK_P | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/clk5div |
| w_clk25m | Generated | 40.000 | 25.000 | 0.000 | 20.000 | i_clk | i_clk | w_clk25m |
| w_clk60m | Generated | 16.667 | 60.000 | 0.000 | 8.333 | i_clk | i_clk | w_clk60m |
| u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTP |
| u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 33.333 | 30.000 | 0.000 | 16.667 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD |
| u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 50.000 | 20.000 | 0.000 | 25.000 | i_clk_ibuf/I | i_clk | u0_syspll_rPLL/rpll_inst/CLKOUTD3 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Generated | 40.000 | 25.000 | 0.000 | 20.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Generated | 80.000 | 12.500 | 0.000 | 40.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 120.000 | 8.333 | 0.000 | 60.000 | u1_CLKDIV/CLKOUT | w_clk25m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Generated | 200.000 | 5.000 | 0.000 | 100.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | rxdiv5clk | 30.030(MHz) | 203.663(MHz) | 6 | TOP |
| 2 | w_clk25m | 25.000(MHz) | 76.154(MHz) | 10 | TOP |
| 3 | w_clk60m | 60.000(MHz) | 134.745(MHz) | 7 | TOP |
| 4 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | 5.000(MHz) | 357.993(MHz) | 2 | TOP |
No timing paths to get frequency of i_clk!
No timing paths to get frequency of RX_CLK_P!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| i_clk | Setup | 0.000 | 0 |
| i_clk | Hold | 0.000 | 0 |
| RX_CLK_P | Setup | 0.000 | 0 |
| RX_CLK_P | Hold | 0.000 | 0 |
| rxdiv5clk | Setup | 0.000 | 0 |
| rxdiv5clk | Hold | 0.000 | 0 |
| w_clk25m | Setup | 0.000 | 0 |
| w_clk25m | Hold | 0.000 | 0 |
| w_clk60m | Setup | 0.000 | 0 |
| w_clk60m | Hold | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
| u0_syspll_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
| u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 9.245 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.386 |
| 2 | 9.245 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.386 |
| 3 | 9.430 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.202 |
| 4 | 9.614 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 7.018 |
| 5 | 9.635 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_20_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.997 |
| 6 | 9.690 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.941 |
| 7 | 9.695 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx3_data_6_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.937 |
| 8 | 9.728 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx7_data_2_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.904 |
| 9 | 9.791 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.840 |
| 10 | 9.791 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.840 |
| 11 | 9.791 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.840 |
| 12 | 9.869 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.763 |
| 13 | 9.875 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_0_s12/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.756 |
| 14 | 9.898 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/D | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.734 |
| 15 | 9.930 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_27_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.702 |
| 16 | 9.930 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_36_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.702 |
| 17 | 9.961 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_19_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.670 |
| 18 | 10.117 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_45_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.514 |
| 19 | 10.117 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_54_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.514 |
| 20 | 10.121 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s1/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.511 |
| 21 | 10.241 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_63_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.391 |
| 22 | 10.246 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_1_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.386 |
| 23 | 10.246 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_2_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.386 |
| 24 | 10.246 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_6_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.386 |
| 25 | 10.246 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 6.386 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.289 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/D | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.664 |
| 2 | 0.293 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/D | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
| 3 | 0.293 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_4_G[4]_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/D | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.669 |
| 4 | 0.296 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[6]_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/D | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.671 |
| 5 | 0.307 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/D | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | -0.000 | -0.329 | 0.682 |
| 6 | 0.318 | u_ltpi_hpm/u_ltpi_core/r2_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/RESET | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.329 |
| 7 | 0.319 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_plus_s0/RESET | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.330 |
| 8 | 0.324 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.335 |
| 9 | 0.324 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.335 |
| 10 | 0.324 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.335 |
| 11 | 0.324 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_7_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.335 |
| 12 | 0.324 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_0_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.335 |
| 13 | 0.324 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_1_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.335 |
| 14 | 0.324 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_2_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.335 |
| 15 | 0.324 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_3_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.335 |
| 16 | 0.327 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_0_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.338 |
| 17 | 0.327 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_1_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.338 |
| 18 | 0.327 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_4_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.338 |
| 19 | 0.327 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_7_s0/CE | w_clk60m:[R] | w_clk60m:[R] | 0.000 | 0.000 | 0.338 |
| 20 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.338 |
| 21 | 0.327 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_18_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.338 |
| 22 | 0.330 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_14_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.341 |
| 23 | 0.330 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.341 |
| 24 | 0.330 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.341 |
| 25 | 0.330 | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CE | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 0.341 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 2.189 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] | 3.333 | -0.547 | 1.626 |
| 2 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_0_s3/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 3 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_1_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 4 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_2_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 5 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_3_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 6 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_4_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 7 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_5_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 8 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_6_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 9 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_8_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 10 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_9_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 11 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_1_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 12 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_3_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 13 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_4_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 14 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_7_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 15 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_1_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 16 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_2_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 17 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_3_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 18 | 12.292 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_4_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.339 |
| 19 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_1_s3/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 20 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_0_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 21 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/command_rd_wrn_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 22 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_2_s1/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 23 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_2_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 24 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_5_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
| 25 | 12.300 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_6_s0/CLEAR | w_clk60m:[R] | w_clk60m:[R] | 16.667 | 0.000 | 4.331 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.789 | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN | w_clk60m:[R] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] | -0.000 | -0.516 | 1.350 |
| 2 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 3 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 4 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 5 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 6 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 7 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 8 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 9 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 10 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 11 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 12 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 13 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 14 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 15 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 16 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 17 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 18 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 19 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 20 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 21 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 22 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 23 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 24 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
| 25 | 1.074 | r_clk25_cnt_5_s0/Q | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR | w_clk25m:[R] | w_clk25m:[R] | 0.000 | 0.000 | 1.085 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | r_clk60_cnt_4_s0 |
| 2 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | r_clk60_cnt_3_s0 |
| 3 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | r_clk60_cnt_2_s0 |
| 4 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | r_clk60_cnt_1_s0 |
| 5 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/detfrm_tramsit_cnt_20_s0 |
| 6 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/advfrm_tramsit_cnt_18_s0 |
| 7 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_17_s0 |
| 8 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_1_s0 |
| 9 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_24_s0 |
| 10 | 7.256 | 8.256 | 1.000 | Low Pulse Width | w_clk60m | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 9.245 |
| Data Arrival Time | 7.630 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 13 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q |
| 0.914 | 0.438 | tNET | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/I2 |
| 1.431 | 0.517 | tINS | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/F |
| 2.309 | 0.878 | tNET | FF | 1 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/I3 |
| 2.680 | 0.371 | tINS | FF | 2 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/F |
| 3.805 | 1.125 | tNET | FF | 1 | R36C15[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s8/I0 |
| 4.375 | 0.570 | tINS | FR | 2 | R36C15[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s8/F |
| 4.549 | 0.174 | tNET | RR | 1 | R35C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/I3 |
| 4.920 | 0.371 | tINS | RF | 3 | R35C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/F |
| 5.580 | 0.660 | tNET | FF | 1 | R38C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/I2 |
| 6.150 | 0.570 | tINS | FR | 1 | R38C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/F |
| 6.323 | 0.172 | tNET | RR | 1 | R38C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/I3 |
| 6.840 | 0.517 | tINS | RF | 2 | R38C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/F |
| 7.630 | 0.790 | tNET | FF | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.916, 39.478%; route: 4.238, 57.381%; tC2Q: 0.232, 3.141% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
| Slack | 9.245 |
| Data Arrival Time | 7.630 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 13 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q |
| 0.914 | 0.438 | tNET | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/I2 |
| 1.431 | 0.517 | tINS | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/F |
| 2.309 | 0.878 | tNET | FF | 1 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/I3 |
| 2.680 | 0.371 | tINS | FF | 2 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/F |
| 3.805 | 1.125 | tNET | FF | 1 | R36C15[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s8/I0 |
| 4.375 | 0.570 | tINS | FR | 2 | R36C15[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s8/F |
| 4.549 | 0.174 | tNET | RR | 1 | R35C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/I3 |
| 4.920 | 0.371 | tINS | RF | 3 | R35C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1044_s4/F |
| 5.580 | 0.660 | tNET | FF | 1 | R38C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/I2 |
| 6.150 | 0.570 | tINS | FR | 1 | R38C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s6/F |
| 6.323 | 0.172 | tNET | RR | 1 | R38C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/I3 |
| 6.840 | 0.517 | tINS | RF | 2 | R38C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s3/F |
| 7.259 | 0.419 | tNET | FF | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/I2 |
| 7.630 | 0.371 | tINS | FF | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1041_s3/F |
| 7.630 | 0.000 | tNET | FF | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.287, 44.501%; route: 3.867, 52.359%; tC2Q: 0.232, 3.141% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
| Slack | 9.430 |
| Data Arrival Time | 7.445 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 22 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.591 | 1.116 | tNET | FF | 1 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/I1 |
| 2.108 | 0.517 | tINS | FF | 2 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/F |
| 3.089 | 0.981 | tNET | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/I3 |
| 3.542 | 0.453 | tINS | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/F |
| 3.696 | 0.154 | tNET | FF | 1 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/I2 |
| 4.213 | 0.517 | tINS | FF | 3 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/F |
| 4.879 | 0.666 | tNET | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I2 |
| 5.434 | 0.555 | tINS | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.831 | 0.397 | tNET | FF | 1 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I1 |
| 6.293 | 0.462 | tINS | FR | 2 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
| 6.469 | 0.176 | tNET | RR | 1 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
| 6.931 | 0.462 | tINS | RR | 5 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.445 | 0.514 | tNET | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.966, 41.184%; route: 4.004, 55.595%; tC2Q: 0.232, 3.221% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
| Slack | 9.614 |
| Data Arrival Time | 7.261 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 22 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.591 | 1.116 | tNET | FF | 1 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/I1 |
| 2.108 | 0.517 | tINS | FF | 2 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/F |
| 3.089 | 0.981 | tNET | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/I3 |
| 3.542 | 0.453 | tINS | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/F |
| 3.696 | 0.154 | tNET | FF | 1 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/I2 |
| 4.213 | 0.517 | tINS | FF | 3 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/F |
| 4.879 | 0.666 | tNET | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I2 |
| 5.434 | 0.555 | tINS | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.831 | 0.397 | tNET | FF | 1 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I1 |
| 6.293 | 0.462 | tINS | FR | 2 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
| 6.469 | 0.176 | tNET | RR | 1 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
| 6.931 | 0.462 | tINS | RR | 5 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.261 | 0.331 | tNET | RR | 1 | R39C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r_lock_temp_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.966, 42.262%; route: 3.820, 54.432%; tC2Q: 0.232, 3.306% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
| Slack | 9.635 |
| Data Arrival Time | 7.240 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_20_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 7.240 | 1.968 | tNET | RR | 1 | R25C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_20_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R25C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_20_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R25C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_20_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 33.986%; route: 4.387, 62.698%; tC2Q: 0.232, 3.316% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
| Slack | 9.690 |
| Data Arrival Time | 7.185 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 12 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q |
| 2.079 | 1.603 | tNET | FF | 1 | R44C16[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/I0 |
| 2.649 | 0.570 | tINS | FR | 1 | R44C16[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/F |
| 2.650 | 0.001 | tNET | RR | 1 | R44C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/I0 |
| 3.167 | 0.517 | tINS | RF | 6 | R44C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/F |
| 3.752 | 0.585 | tNET | FF | 1 | R45C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s14/I2 |
| 4.322 | 0.570 | tINS | FR | 1 | R45C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s14/F |
| 4.323 | 0.001 | tNET | RR | 1 | R45C18[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s10/I0 |
| 4.694 | 0.371 | tINS | RF | 2 | R45C18[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s10/F |
| 5.356 | 0.662 | tNET | FF | 1 | R47C21[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s9/I0 |
| 5.873 | 0.517 | tINS | FF | 3 | R47C21[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s9/F |
| 6.538 | 0.665 | tNET | FF | 1 | R45C24[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s12/I3 |
| 7.000 | 0.462 | tINS | FR | 1 | R45C24[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s12/F |
| 7.185 | 0.185 | tNET | RR | 1 | R44C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.007, 43.321%; route: 3.702, 53.337%; tC2Q: 0.232, 3.342% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
| Slack | 9.695 |
| Data Arrival Time | 7.180 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx3_data_6_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R22C12[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/CLK |
| 0.475 | 0.232 | tC2Q | RF | 20 | R22C12[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_1_s11/Q |
| 2.283 | 1.807 | tNET | FF | 1 | R43C7[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/UART.u_ltpi_uart/watch_s2/I2 |
| 2.736 | 0.453 | tINS | FF | 6 | R43C7[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/UART.u_ltpi_uart/watch_s2/F |
| 3.947 | 1.211 | tNET | FF | 1 | R25C10[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1759_s8/I3 |
| 4.400 | 0.453 | tINS | FF | 5 | R25C10[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1759_s8/F |
| 4.830 | 0.431 | tNET | FF | 1 | R25C12[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s5/I0 |
| 5.347 | 0.517 | tINS | FF | 1 | R25C12[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s5/F |
| 5.744 | 0.397 | tNET | FF | 1 | R25C13[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s4/I2 |
| 6.197 | 0.453 | tINS | FF | 1 | R25C13[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s4/F |
| 6.610 | 0.413 | tNET | FF | 1 | R22C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s3/I0 |
| 7.180 | 0.570 | tINS | FR | 1 | R22C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1760_s3/F |
| 7.180 | 0.000 | tNET | RR | 1 | R22C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx3_data_6_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R22C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx3_data_6_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R22C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx3_data_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.446, 35.260%; route: 4.259, 61.396%; tC2Q: 0.232, 3.344% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
| Slack | 9.728 |
| Data Arrival Time | 7.147 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx7_data_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R21C23[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/CLK |
| 0.475 | 0.232 | tC2Q | RF | 51 | R21C23[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s1/Q |
| 1.522 | 1.047 | tNET | FF | 1 | R25C6[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1798_s5/I0 |
| 2.039 | 0.517 | tINS | FF | 82 | R25C6[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1798_s5/F |
| 3.764 | 1.725 | tNET | FF | 1 | R20C9[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1727_s6/I3 |
| 4.319 | 0.555 | tINS | FF | 8 | R20C9[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1727_s6/F |
| 4.589 | 0.270 | tNET | FF | 1 | R20C7[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s5/I1 |
| 5.138 | 0.549 | tINS | FR | 1 | R20C7[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s5/F |
| 5.140 | 0.001 | tNET | RR | 1 | R20C7[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s4/I2 |
| 5.695 | 0.555 | tINS | RF | 1 | R20C7[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s4/F |
| 6.577 | 0.882 | tNET | FF | 1 | R20C8[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s3/I0 |
| 7.147 | 0.570 | tINS | FR | 1 | R20C8[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n1732_s3/F |
| 7.147 | 0.000 | tNET | RR | 1 | R20C8[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx7_data_2_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R20C8[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx7_data_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R20C8[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx7_data_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.746, 39.775%; route: 3.926, 56.865%; tC2Q: 0.232, 3.360% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
| Slack | 9.791 |
| Data Arrival Time | 7.084 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 22 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.591 | 1.116 | tNET | FF | 1 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/I1 |
| 2.108 | 0.517 | tINS | FF | 2 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/F |
| 3.089 | 0.981 | tNET | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/I3 |
| 3.542 | 0.453 | tINS | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/F |
| 3.696 | 0.154 | tNET | FF | 1 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/I2 |
| 4.213 | 0.517 | tINS | FF | 3 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/F |
| 4.879 | 0.666 | tNET | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I2 |
| 5.434 | 0.555 | tINS | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.831 | 0.397 | tNET | FF | 1 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I1 |
| 6.293 | 0.462 | tINS | FR | 2 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
| 6.469 | 0.176 | tNET | RR | 1 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
| 6.931 | 0.462 | tINS | RR | 5 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.084 | 0.153 | tNET | RR | 1 | R39C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.966, 43.360%; route: 3.642, 53.248%; tC2Q: 0.232, 3.392% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
| Slack | 9.791 |
| Data Arrival Time | 7.084 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 22 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.591 | 1.116 | tNET | FF | 1 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/I1 |
| 2.108 | 0.517 | tINS | FF | 2 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/F |
| 3.089 | 0.981 | tNET | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/I3 |
| 3.542 | 0.453 | tINS | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/F |
| 3.696 | 0.154 | tNET | FF | 1 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/I2 |
| 4.213 | 0.517 | tINS | FF | 3 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/F |
| 4.879 | 0.666 | tNET | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I2 |
| 5.434 | 0.555 | tINS | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.831 | 0.397 | tNET | FF | 1 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I1 |
| 6.293 | 0.462 | tINS | FR | 2 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
| 6.469 | 0.176 | tNET | RR | 1 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
| 6.931 | 0.462 | tINS | RR | 5 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.084 | 0.153 | tNET | RR | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.966, 43.360%; route: 3.642, 53.248%; tC2Q: 0.232, 3.392% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
| Slack | 9.791 |
| Data Arrival Time | 7.084 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 22 | R35C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_8_s0/Q |
| 1.591 | 1.116 | tNET | FF | 1 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/I1 |
| 2.108 | 0.517 | tINS | FF | 2 | R36C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s62/F |
| 3.089 | 0.981 | tNET | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/I3 |
| 3.542 | 0.453 | tINS | FF | 1 | R36C18[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s36/F |
| 3.696 | 0.154 | tNET | FF | 1 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/I2 |
| 4.213 | 0.517 | tINS | FF | 3 | R36C18[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s15/F |
| 4.879 | 0.666 | tNET | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/I2 |
| 5.434 | 0.555 | tINS | FF | 1 | R38C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s5/F |
| 5.831 | 0.397 | tNET | FF | 1 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/I1 |
| 6.293 | 0.462 | tINS | FR | 2 | R39C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s1/F |
| 6.469 | 0.176 | tNET | RR | 1 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/I0 |
| 6.931 | 0.462 | tINS | RR | 5 | R39C16[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1040_s0/F |
| 7.084 | 0.153 | tNET | RR | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R39C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.966, 43.360%; route: 3.642, 53.248%; tC2Q: 0.232, 3.392% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
| Slack | 9.869 |
| Data Arrival Time | 7.006 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 12 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q |
| 2.079 | 1.603 | tNET | FF | 1 | R44C16[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/I0 |
| 2.649 | 0.570 | tINS | FR | 1 | R44C16[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s4/F |
| 2.650 | 0.001 | tNET | RR | 1 | R44C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/I0 |
| 3.167 | 0.517 | tINS | RF | 6 | R44C16[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n570_s3/F |
| 3.752 | 0.585 | tNET | FF | 1 | R45C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s14/I2 |
| 4.322 | 0.570 | tINS | FR | 1 | R45C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s14/F |
| 4.323 | 0.001 | tNET | RR | 1 | R45C18[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s10/I0 |
| 4.694 | 0.371 | tINS | RF | 2 | R45C18[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s10/F |
| 5.356 | 0.662 | tNET | FF | 1 | R47C21[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s9/I0 |
| 5.873 | 0.517 | tINS | FF | 3 | R47C21[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s9/F |
| 6.400 | 0.527 | tNET | FF | 1 | R45C25[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s10/I3 |
| 6.862 | 0.462 | tINS | FR | 1 | R45C25[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s10/F |
| 7.006 | 0.144 | tNET | RR | 1 | R45C25[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C25[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C25[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.007, 44.465%; route: 3.524, 52.104%; tC2Q: 0.232, 3.431% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
| Slack | 9.875 |
| Data Arrival Time | 7.000 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_0_s12 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R25C10[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_0_s12/CLK |
| 0.475 | 0.232 | tC2Q | RF | 20 | R25C10[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx_frm_offset_0_s12/Q |
| 1.171 | 0.696 | tNET | FF | 1 | R22C12[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/I0 |
| 1.720 | 0.549 | tINS | FR | 4 | R22C12[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/tx9_data_7_s4/F |
| 1.725 | 0.005 | tNET | RR | 1 | R22C12[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/I3 |
| 2.178 | 0.453 | tINS | RF | 18 | R22C12[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/n2657_s1/F |
| 3.235 | 1.056 | tNET | FF | 1 | R25C22[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/I1 |
| 3.688 | 0.453 | tINS | FF | 4 | R25C22[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s78/F |
| 4.338 | 0.650 | tNET | FF | 1 | R21C22[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/I1 |
| 4.709 | 0.371 | tINS | FF | 3 | R21C22[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/n273_s72/F |
| 4.722 | 0.013 | tNET | FF | 1 | R21C22[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/I2 |
| 5.184 | 0.462 | tINS | FR | 2 | R21C22[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_1_s8/F |
| 5.359 | 0.176 | tNET | RR | 1 | R21C23[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/I2 |
| 5.908 | 0.549 | tINS | RR | 2 | R21C23[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s10/F |
| 5.911 | 0.003 | tNET | RR | 1 | R21C23[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s8/I1 |
| 6.460 | 0.549 | tINS | RR | 1 | R21C23[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s8/F |
| 7.000 | 0.540 | tNET | RR | 1 | R24C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R24C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R24C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_controller/rstate_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 8 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.386, 50.115%; route: 3.138, 46.452%; tC2Q: 0.232, 3.434% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
| Slack | 9.898 |
| Data Arrival Time | 6.977 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 13 | R38C14[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/rx_data_temp_21_s0/Q |
| 0.914 | 0.438 | tNET | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/I2 |
| 1.431 | 0.517 | tINS | FF | 1 | R36C13[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s47/F |
| 2.309 | 0.878 | tNET | FF | 1 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/I3 |
| 2.680 | 0.371 | tINS | FF | 2 | R36C13[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s21/F |
| 3.902 | 1.222 | tNET | FF | 1 | R38C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s9/I1 |
| 4.472 | 0.570 | tINS | FR | 2 | R38C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1042_s9/F |
| 4.646 | 0.174 | tNET | RR | 1 | R38C17[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s13/I3 |
| 5.201 | 0.555 | tINS | RF | 1 | R38C17[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s13/F |
| 5.857 | 0.656 | tNET | FF | 1 | R41C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s6/I2 |
| 6.427 | 0.570 | tINS | FR | 1 | R41C15[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s6/F |
| 6.428 | 0.001 | tNET | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s3/I2 |
| 6.977 | 0.549 | tINS | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/n1043_s3/F |
| 6.977 | 0.000 | tNET | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R41C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/sync_offset_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.132, 46.510%; route: 3.370, 50.045%; tC2Q: 0.232, 3.445% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
| Slack | 9.930 |
| Data Arrival Time | 6.945 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_27_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.945 | 1.672 | tNET | RR | 1 | R18C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_27_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R18C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_27_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R18C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_27_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 35.484%; route: 4.092, 61.055%; tC2Q: 0.232, 3.462% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
| Slack | 9.930 |
| Data Arrival Time | 6.945 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_36_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.945 | 1.672 | tNET | RR | 1 | R18C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_36_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R18C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_36_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R18C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_36_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 35.484%; route: 4.092, 61.055%; tC2Q: 0.232, 3.462% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
| Slack | 9.961 |
| Data Arrival Time | 6.914 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_19_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.914 | 1.641 | tNET | RR | 1 | R26C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_19_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R26C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_19_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R26C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 35.650%; route: 4.060, 60.872%; tC2Q: 0.232, 3.478% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
| Slack | 10.117 |
| Data Arrival Time | 6.758 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_45_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.758 | 1.485 | tNET | RR | 1 | R18C9[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_45_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R18C9[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_45_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R18C9[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_45_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 36.504%; route: 3.904, 59.935%; tC2Q: 0.232, 3.561% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
| Slack | 10.117 |
| Data Arrival Time | 6.758 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_54_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.758 | 1.485 | tNET | RR | 1 | R18C9[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_54_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R18C9[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_54_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R18C9[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_54_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 36.504%; route: 3.904, 59.935%; tC2Q: 0.232, 3.561% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
| Slack | 10.121 |
| Data Arrival Time | 6.754 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 12 | R18C10[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/Opera_local_I2C_channel_cpbl_0_s0/Q |
| 2.000 | 1.524 | tNET | FF | 1 | R44C19[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s6/I0 |
| 2.371 | 0.371 | tINS | FF | 1 | R44C19[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s6/F |
| 2.541 | 0.170 | tNET | FF | 1 | R45C19[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s5/I0 |
| 2.994 | 0.453 | tINS | FF | 5 | R45C19[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s5/F |
| 3.259 | 0.265 | tNET | FF | 1 | R44C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s3/I1 |
| 3.814 | 0.555 | tINS | FF | 4 | R44C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n650_s3/F |
| 4.483 | 0.669 | tNET | FF | 1 | R47C21[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s11/I0 |
| 4.945 | 0.462 | tINS | FR | 2 | R47C21[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_1_s11/F |
| 4.947 | 0.003 | tNET | RR | 1 | R47C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_4_s15/I0 |
| 5.400 | 0.453 | tINS | RF | 2 | R47C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_4_s15/F |
| 6.061 | 0.660 | tNET | FF | 1 | R44C23[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s10/I3 |
| 6.610 | 0.549 | tINS | FR | 1 | R44C23[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s10/F |
| 6.754 | 0.144 | tNET | RR | 1 | R44C23[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s1/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C23[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C23[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/relay_state_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.843, 43.667%; route: 3.436, 52.769%; tC2Q: 0.232, 3.563% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
| Slack | 10.241 |
| Data Arrival Time | 6.634 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_63_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.724 | 1.051 | tNET | FF | 1 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/I2 |
| 5.273 | 0.549 | tINS | FR | 64 | R29C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_en_s4/F |
| 6.634 | 1.362 | tNET | RR | 1 | R21C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_63_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R21C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_63_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R21C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/cfgfrm_get_63_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 37.208%; route: 3.781, 59.162%; tC2Q: 0.232, 3.630% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
| Slack | 10.246 |
| Data Arrival Time | 6.629 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.303 | 0.630 | tNET | FF | 1 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/I2 |
| 4.852 | 0.549 | tINS | FR | 80 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/F |
| 6.629 | 1.777 | tNET | RR | 1 | R26C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R26C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_1_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R26C17[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 37.240%; route: 3.776, 59.127%; tC2Q: 0.232, 3.633% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
| Slack | 10.246 |
| Data Arrival Time | 6.629 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_2_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.303 | 0.630 | tNET | FF | 1 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/I2 |
| 4.852 | 0.549 | tINS | FR | 80 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/F |
| 6.629 | 1.777 | tNET | RR | 1 | R17C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R17C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_2_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R17C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 37.240%; route: 3.776, 59.127%; tC2Q: 0.232, 3.633% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
| Slack | 10.246 |
| Data Arrival Time | 6.629 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_6_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.303 | 0.630 | tNET | FF | 1 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/I2 |
| 4.852 | 0.549 | tINS | FR | 80 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/F |
| 6.629 | 1.777 | tNET | RR | 1 | R26C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R26C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_6_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R26C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 37.240%; route: 3.776, 59.127%; tC2Q: 0.232, 3.633% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
| Slack | 10.246 |
| Data Arrival Time | 6.629 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 3 | R39C21[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/rx_frm_offset_o_3_s0/Q |
| 1.408 | 0.932 | tNET | FF | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/I1 |
| 1.978 | 0.570 | tINS | FR | 1 | R29C19[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s4/F |
| 1.979 | 0.001 | tNET | RR | 1 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/I0 |
| 2.350 | 0.371 | tINS | RF | 3 | R29C19[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n4007_s2/F |
| 2.772 | 0.422 | tNET | FF | 1 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/I0 |
| 3.143 | 0.371 | tINS | FF | 3 | R31C20[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s1/F |
| 3.156 | 0.013 | tNET | FF | 1 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/I3 |
| 3.673 | 0.517 | tINS | FF | 11 | R31C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n6145_s0/F |
| 4.303 | 0.630 | tNET | FF | 1 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/I2 |
| 4.852 | 0.549 | tINS | FR | 80 | R30C11[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/n341_s1/F |
| 6.629 | 1.777 | tNET | RR | 1 | R22C5[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R22C5[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R22C5[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/advfrm_get_o_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.378, 37.240%; route: 3.776, 59.127%; tC2Q: 0.232, 3.633% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.289 |
| Data Arrival Time | 200.848 |
| Data Required Time | 200.560 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R16C4[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/CLK |
| 200.385 | 0.201 | tC2Q | RF | 1 | R16C4[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[1]_s0/Q |
| 200.502 | 0.117 | tNET | FF | 1 | R16C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s5/I1 |
| 200.734 | 0.232 | tINS | FF | 1 | R16C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s5/F |
| 200.734 | 0.000 | tNET | FF | 1 | R16C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s2/I0 |
| 200.786 | 0.052 | tINS | FF | 1 | R16C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s2/O |
| 200.786 | 0.000 | tNET | FF | 1 | R16C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s0/I1 |
| 200.838 | 0.052 | tINS | FF | 1 | R16C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_7_G[0]_s0/O |
| 200.848 | 0.010 | tNET | FF | 1 | R16C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 200.514 | 0.184 | tNET | RR | 1 | R16C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0/CLK |
| 200.549 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 | |||
| 200.560 | 0.011 | tHld | 1 | R16C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_1_s0 |
Path Statistics:
| Clock Skew | 0.329 |
| Hold Relationship | -0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.336, 50.612%; route: 0.127, 19.112%; tC2Q: 0.201, 30.277% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
| Slack | 0.293 |
| Data Arrival Time | 200.853 |
| Data Required Time | 200.560 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R13C4[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/CLK |
| 200.385 | 0.201 | tC2Q | RF | 1 | R13C4[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_5_G[3]_s0/Q |
| 200.507 | 0.122 | tNET | FF | 1 | R14C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s5/I1 |
| 200.739 | 0.232 | tINS | FF | 1 | R14C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s5/F |
| 200.739 | 0.000 | tNET | FF | 1 | R14C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s2/I0 |
| 200.791 | 0.052 | tINS | FF | 1 | R14C4[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s2/O |
| 200.791 | 0.000 | tNET | FF | 1 | R14C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s0/I1 |
| 200.843 | 0.052 | tINS | FF | 1 | R14C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_21_G[0]_s0/O |
| 200.853 | 0.010 | tNET | FF | 1 | R14C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 200.514 | 0.184 | tNET | RR | 1 | R14C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0/CLK |
| 200.549 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 | |||
| 200.560 | 0.011 | tHld | 1 | R14C4[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_3_s0 |
Path Statistics:
| Clock Skew | 0.329 |
| Hold Relationship | -0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
| Slack | 0.293 |
| Data Arrival Time | 200.853 |
| Data Required Time | 200.560 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_4_G[4]_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R13C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_4_G[4]_s0/CLK |
| 200.385 | 0.201 | tC2Q | RF | 1 | R13C6[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_4_G[4]_s0/Q |
| 200.507 | 0.122 | tNET | FF | 1 | R13C5[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s3/I1 |
| 200.739 | 0.232 | tINS | FF | 1 | R13C5[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s3/F |
| 200.739 | 0.000 | tNET | FF | 1 | R13C5[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s1/I0 |
| 200.791 | 0.052 | tINS | FF | 1 | R13C5[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s1/O |
| 200.791 | 0.000 | tNET | FF | 1 | R13C5[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s0/I0 |
| 200.843 | 0.052 | tINS | FF | 1 | R13C5[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_28_G[0]_s0/O |
| 200.853 | 0.010 | tNET | FF | 1 | R13C5[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 200.514 | 0.184 | tNET | RR | 1 | R13C5[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0/CLK |
| 200.549 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 | |||
| 200.560 | 0.011 | tHld | 1 | R13C5[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_4_s0 |
Path Statistics:
| Clock Skew | 0.329 |
| Hold Relationship | -0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.336, 50.239%; route: 0.132, 19.707%; tC2Q: 0.201, 30.054% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
| Slack | 0.296 |
| Data Arrival Time | 200.855 |
| Data Required Time | 200.560 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[6]_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R13C5[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[6]_s0/CLK |
| 200.386 | 0.202 | tC2Q | RR | 1 | R13C5[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_mem_RAMREG_6_G[6]_s0/Q |
| 200.510 | 0.123 | tNET | RR | 1 | R13C7[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s4/I1 |
| 200.742 | 0.232 | tINS | RF | 1 | R13C7[3][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s4/F |
| 200.742 | 0.000 | tNET | FF | 1 | R13C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s1/I1 |
| 200.794 | 0.052 | tINS | FF | 1 | R13C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s1/O |
| 200.794 | 0.000 | tNET | FF | 1 | R13C7[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s0/I0 |
| 200.846 | 0.052 | tINS | FF | 1 | R13C7[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/mem_RAMOUT_42_G[0]_s0/O |
| 200.855 | 0.010 | tNET | FF | 1 | R13C7[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 200.514 | 0.184 | tNET | RR | 1 | R13C7[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0/CLK |
| 200.549 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 | |||
| 200.560 | 0.011 | tHld | 1 | R13C7[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/dout_r_6_s0 |
Path Statistics:
| Clock Skew | 0.329 |
| Hold Relationship | -0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.336, 50.065%; route: 0.133, 19.836%; tC2Q: 0.202, 30.099% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
| Slack | 0.307 |
| Data Arrival Time | 200.867 |
| Data Required Time | 200.560 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R13C6[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/CLK |
| 200.386 | 0.202 | tC2Q | RR | 1 | R13C6[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_s0/Q |
| 200.867 | 0.480 | tNET | RR | 1 | R13C2[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 200.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 200.514 | 0.184 | tNET | RR | 1 | R13C2[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/CLK |
| 200.549 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 | |||
| 200.560 | 0.011 | tHld | 1 | R13C2[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 |
Path Statistics:
| Clock Skew | 0.329 |
| Hold Relationship | -0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.480, 70.391%; tC2Q: 0.202, 29.609% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
| Slack | 0.318 |
| Data Arrival Time | 0.513 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/r2_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R31C25[0][B] | u_ltpi_hpm/u_ltpi_core/r2_rstn_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 1 | R31C25[0][B] | u_ltpi_hpm/u_ltpi_core/r2_rstn_s0/Q |
| 0.513 | 0.127 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.127, 38.638%; tC2Q: 0.202, 61.362% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
| Slack | 0.319 |
| Data Arrival Time | 0.844 |
| Data Required Time | 0.525 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_plus_s0 |
| Launch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 0.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 0.514 | 0.184 | tNET | RR | 1 | R13C2[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/CLK |
| 0.716 | 0.202 | tC2Q | RR | 2 | R13C2[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_d1_s0/Q |
| 0.844 | 0.128 | tNET | RR | 1 | R13C2[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_plus_s0/RESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT.default_gen_clk | ||||
| 0.329 | 0.329 | tCL | RR | 29 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/CLKOUT |
| 0.514 | 0.184 | tNET | RR | 1 | R13C2[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_plus_s0/CLK |
| 0.525 | 0.011 | tHld | 1 | R13C2[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u_clk_cross/wr_flag_plus_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.128, 38.865%; tC2Q: 0.202, 61.135% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.519 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.519 | 0.133 | tNET | RR | 1 | R20C33[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C33[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C33[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_rw_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.701%; tC2Q: 0.202, 60.299% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.519 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.519 | 0.133 | tNET | RR | 1 | R20C36[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C36[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C36[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.701%; tC2Q: 0.202, 60.299% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.519 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.519 | 0.133 | tNET | RR | 1 | R20C34[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C34[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C34[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.701%; tC2Q: 0.202, 60.299% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.519 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_7_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.519 | 0.133 | tNET | RR | 1 | R20C36[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C36[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_7_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C36[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.701%; tC2Q: 0.202, 60.299% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.520 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_0_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 5 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q |
| 0.520 | 0.133 | tNET | RR | 1 | R34C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R34C15[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.520 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 5 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q |
| 0.520 | 0.133 | tNET | RR | 1 | R34C15[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R34C15[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.520 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_2_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 5 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q |
| 0.520 | 0.133 | tNET | RR | 1 | R34C15[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_2_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R34C15[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
| Slack | 0.324 |
| Data Arrival Time | 0.520 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_3_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 5 | R34C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/r2_sync_valid_s0/Q |
| 0.520 | 0.133 | tNET | RR | 1 | R34C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R34C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_3_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R34C15[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/u_sync_10b/o_rx_frm_offset_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_0_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 10 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R38C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R38C24[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 10 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R38C24[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R38C24[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_4_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 10 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R38C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_4_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R38C24[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_7_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 10 | R38C24[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/r1_en_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R38C24[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R38C24[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_7_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R38C24[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_decoder_8b10b_nolut/dout_o_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R18C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R18C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.237%; tC2Q: 0.202, 59.763% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
| Slack | 0.327 |
| Data Arrival Time | 0.522 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_18_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.522 | 0.136 | tNET | RR | 1 | R18C35[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_18_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R18C35[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_18_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C35[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.136, 40.237%; tC2Q: 0.202, 59.763% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
| Slack | 0.330 |
| Data Arrival Time | 0.525 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_14_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.525 | 0.139 | tNET | RR | 1 | R20C37[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_14_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C37[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_14_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C37[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_wdata_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.139, 40.762%; tC2Q: 0.202, 59.238% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
| Slack | 0.330 |
| Data Arrival Time | 0.525 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.525 | 0.139 | tNET | RR | 1 | R20C37[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C37[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C37[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.139, 40.762%; tC2Q: 0.202, 59.238% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
| Slack | 0.330 |
| Data Arrival Time | 0.525 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.525 | 0.139 | tNET | RR | 1 | R20C37[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C37[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C37[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.139, 40.762%; tC2Q: 0.202, 59.238% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
| Slack | 0.330 |
| Data Arrival Time | 0.525 |
| Data Required Time | 0.195 |
| From | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 52 | R20C35[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/rx_fifo_valid_s0/Q |
| 0.525 | 0.139 | tNET | RR | 1 | R20C37[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C37[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C37[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.139, 40.762%; tC2Q: 0.202, 59.238% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 2.189 |
| Data Arrival Time | 118.536 |
| Data Required Time | 120.725 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 116.667 | 116.667 | active clock edge time | ||||
| 116.667 | 0.000 | w_clk60m | ||||
| 116.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 116.910 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 117.141 | 0.231 | tC2Q | RR | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 118.536 | 1.395 | tNET | RR | 1 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 120.000 | 120.000 | active clock edge time | ||||
| 120.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | ||||
| 120.415 | 0.415 | tCL | RR | 2 | PLL_R[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
| 120.790 | 0.375 | tNET | RR | 5 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/HCLKIN |
| 120.755 | -0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV | |||
| 120.725 | -0.030 | tSu | 1 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Path Statistics:
| Clock Skew | 0.547 |
| Setup Relationship | 3.333 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.395, 85.795%; tC2Q: 0.231, 14.205% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path2
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_0_s3 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C18[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_0_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C18[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_0_s3/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C18[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_0_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_1_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C18[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C18[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_1_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C18[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C18[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_3_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C18[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C18[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_3_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C18[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_4_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_4_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C17[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_5_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_5_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C17[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_6_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C17[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C17[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_6_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C17[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_8_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_8_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C17[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_9_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C17[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C17[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_9_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C17[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/target_scl_hold_count_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R45C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_1_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_3_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R45C19[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C19[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_3_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C19[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_4_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R45C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_4_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_7_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R45C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_7_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C19[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_1_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_1_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C16[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_2_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_2_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C16[0][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_3_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_3_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C16[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
| Slack | 12.292 |
| Data Arrival Time | 4.583 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_4_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.583 | 2.064 | tNET | FF | 1 | R44C16[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C16[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_4_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C16[2][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/setup_timeout_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.439%; route: 3.654, 84.214%; tC2Q: 0.232, 5.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_1_s3 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R45C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_1_s3/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_1_s3/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C12[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_1_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_0_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R45C20[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C20[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_0_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C20[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/command_rd_wrn_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R45C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/command_rd_wrn_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/command_rd_wrn_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C15[2][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/command_rd_wrn_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_2_s1 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R45C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_2_s1/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C12[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/controller_bit_count_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_2_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R45C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R45C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_2_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R45C20[1][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_5_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R44C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_5_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C19[0][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
| Slack | 12.300 |
| Data Arrival Time | 4.575 |
| Data Required Time | 16.875 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_6_s0 |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | w_clk60m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk60m | ||||
| 0.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 0.243 | 0.243 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 2.066 | 1.590 | tNET | FF | 1 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/I2 |
| 2.519 | 0.453 | tINS | FF | 67 | R45C7[3][A] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/n456_s1/F |
| 4.575 | 2.056 | tNET | FF | 1 | R44C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 16.667 | 16.667 | active clock edge time | ||||
| 16.667 | 0.000 | w_clk60m | ||||
| 16.667 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.910 | 0.243 | tNET | RR | 1 | R44C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_6_s0/CLK |
| 16.875 | -0.035 | tSu | 1 | R44C19[1][B] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/SMBUS.u_ltpi_smbus/SMBus[0].u_smbus_relay_target_0/scl_high_count_timeout_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 16.667 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 0.453, 10.458%; route: 3.646, 84.186%; tC2Q: 0.232, 5.356% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.789 |
| Data Arrival Time | 201.534 |
| Data Required Time | 200.745 |
| From | u_ltpi_hpm/u_ltpi_core/r_rstn_s0 |
| To | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
| Launch Clk | w_clk60m:[R] |
| Latch Clk | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | w_clk60m | ||||
| 200.000 | 0.000 | tCL | RR | 2032 | PLL_L[0] | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 200.184 | 0.184 | tNET | RR | 1 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/CLK |
| 200.385 | 0.201 | tC2Q | RF | 24 | R31C25[1][A] | u_ltpi_hpm/u_ltpi_core/r_rstn_s0/Q |
| 201.534 | 1.149 | tNET | FF | 1 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/RESETN |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 200.000 | 200.000 | active clock edge time | ||||
| 200.000 | 0.000 | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT.default_gen_clk | ||||
| 200.415 | 0.415 | tCL | RR | 2 | PLL_R[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/pll_top_inst/u_reconfig_pll_ip/rpll_inst/CLKOUT |
| 200.700 | 0.285 | tNET | RR | 5 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV/HCLKIN |
| 200.735 | 0.035 | tUnc | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV | |||
| 200.745 | 0.010 | tHld | 1 | TOPSIDE[0] | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/u_ltpi_phy_tx_inf/u_lvds_phy_tx/u1_CLKDIV |
Path Statistics:
| Clock Skew | 0.516 |
| Hold Relationship | -0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.149, 85.106%; tC2Q: 0.201, 14.894% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.285, 100.000% |
Path2
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R21C39[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R21C39[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R21C39[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C41[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_req_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C41[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C41[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C41[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/fsm_st_curr_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C48[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C48[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C48[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C48[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C48[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C48[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C43[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C43[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C43[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C43[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C43[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C43[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C43[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C48[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C48[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C48[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R21C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R21C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R21C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R21C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R21C47[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C47[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C47[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C50[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C50[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C50[1][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R20C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C50[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C50[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C50[1][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C52[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C52[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C52[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C50[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C50[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C50[0][B] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
| Slack | 1.074 |
| Data Arrival Time | 1.269 |
| Data Required Time | 0.195 |
| From | r_clk25_cnt_5_s0 |
| To | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0 |
| Launch Clk | w_clk25m:[R] |
| Latch Clk | w_clk25m:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R20C2[2][B] | r_clk25_cnt_5_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 822 | R20C2[2][B] | r_clk25_cnt_5_s0/Q |
| 1.269 | 0.883 | tNET | RR | 1 | R22C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | w_clk25m | ||||
| 0.000 | 0.000 | tCL | RR | 3919 | LEFTSIDE[0] | u1_CLKDIV/CLKOUT |
| 0.184 | 0.184 | tNET | RR | 1 | R22C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C50[0][A] | u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/tx_fifo_wdata_20_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.883, 81.382%; tC2Q: 0.202, 18.618% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | r_clk60_cnt_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | r_clk60_cnt_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | r_clk60_cnt_4_s0/CLK |
MPW2
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | r_clk60_cnt_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | r_clk60_cnt_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | r_clk60_cnt_3_s0/CLK |
MPW3
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | r_clk60_cnt_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | r_clk60_cnt_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | r_clk60_cnt_2_s0/CLK |
MPW4
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | r_clk60_cnt_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | r_clk60_cnt_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | r_clk60_cnt_1_s0/CLK |
MPW5
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/detfrm_tramsit_cnt_20_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/detfrm_tramsit_cnt_20_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/detfrm_tramsit_cnt_20_s0/CLK |
MPW6
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/advfrm_tramsit_cnt_18_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/advfrm_tramsit_cnt_18_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/advfrm_tramsit_cnt_18_s0/CLK |
MPW7
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_17_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_17_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_17_s0/CLK |
MPW8
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/cfgaptfrm_tramsit_cnt_1_s0/CLK |
MPW9
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_24_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_24_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_24_s0/CLK |
MPW10
MPW Summary:
| Slack: | 7.256 |
| Actual Width: | 8.256 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | w_clk60m |
| Objects: | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | w_clk60m | ||
| 8.333 | 0.000 | tCL | FF | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 8.595 | 0.261 | tNET | FF | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 16.667 | 0.000 | active clock edge time | ||
| 16.667 | 0.000 | w_clk60m | ||
| 16.667 | 0.000 | tCL | RR | u0_syspll_rPLL/rpll_inst/CLKOUT |
| 16.851 | 0.184 | tNET | RR | u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_tx/opefrm_tramsit_cnt_20_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 3919 | w_clk25m | 26.869 | 0.261 |
| 2032 | w_clk60m | 2.189 | 0.261 |
| 822 | r_clk25_cnt[5] | 36.606 | 1.604 |
| 307 | n5753_6 | 10.914 | 1.854 |
| 245 | n814_4 | 12.124 | 2.064 |
| 206 | clk5div | 28.390 | 0.261 |
| 196 | rd_ptr[2] | 36.673 | 0.996 |
| 192 | rd_ptr[2] | 35.891 | 1.935 |
| 155 | n1033_6 | 13.307 | 2.020 |
| 145 | phy_rx_rstn | 14.048 | 1.610 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R44C35 | 93.06% |
| R8C36 | 88.89% |
| R7C38 | 88.89% |
| R49C35 | 88.89% |
| R43C35 | 88.89% |
| R44C34 | 88.89% |
| R45C33 | 88.89% |
| R45C35 | 88.89% |
| R35C17 | 87.50% |
| R16C15 | 87.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name i_clk -period 20 -waveform {0 10} [get_ports {i_clk}] |
| TC_CLOCK | Actived | create_clock -name RX_CLK_P -period 6.66 -waveform {0 3.33} [get_ports {RX_CLK_P}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name rxdiv5clk -source [get_ports {RX_CLK_P}] -master_clock RX_CLK_P -divide_by 5 -multiply_by 1 [get_nets {u_ltpi_hpm/u_ltpi_core/u_ltpi_main/u_ltpi_phy/u_ltpi_phy_rx/u_ltpi_phy_rx_inf/u_lvds_phy_rx/clk5div}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name w_clk25m -source [get_ports {i_clk}] -master_clock i_clk -divide_by 2 -multiply_by 1 [get_nets {w_clk25m}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name w_clk60m -source [get_ports {i_clk}] -master_clock i_clk -divide_by 5 -multiply_by 6 [get_nets {w_clk60m}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {w_clk60m}] -group [get_clocks {w_clk25m}] -group [get_clocks {i_clk} ] -group [get_clocks {rxdiv5clk} ] |